root / hw / arm_timer.c @ 09b26c5e
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/*
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* ARM PrimeCell Timer modules.
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "vl.h" |
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#include "arm_pic.h" |
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/* Common timer implementation. */
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#define TIMER_CTRL_ONESHOT (1 << 0) |
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#define TIMER_CTRL_32BIT (1 << 1) |
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#define TIMER_CTRL_DIV1 (0 << 2) |
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#define TIMER_CTRL_DIV16 (1 << 2) |
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#define TIMER_CTRL_DIV256 (2 << 2) |
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#define TIMER_CTRL_IE (1 << 5) |
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#define TIMER_CTRL_PERIODIC (1 << 6) |
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#define TIMER_CTRL_ENABLE (1 << 7) |
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typedef struct { |
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int64_t next_time; |
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int64_t expires; |
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int64_t loaded; |
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QEMUTimer *timer; |
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uint32_t control; |
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uint32_t count; |
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uint32_t limit; |
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int raw_freq;
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int freq;
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int int_level;
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void *pic;
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int irq;
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} arm_timer_state; |
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/* Calculate the new expiry time of the given timer. */
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static void arm_timer_reload(arm_timer_state *s) |
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{ |
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int64_t delay; |
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s->loaded = s->expires; |
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delay = muldiv64(s->count, ticks_per_sec, s->freq); |
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if (delay == 0) |
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delay = 1;
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s->expires += delay; |
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} |
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/* Check all active timers, and schedule the next timer interrupt. */
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static void arm_timer_update(arm_timer_state *s, int64_t now) |
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{ |
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int64_t next; |
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/* Ignore disabled timers. */
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if ((s->control & TIMER_CTRL_ENABLE) == 0) |
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return;
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/* Ignore expired one-shot timers. */
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if (s->count == 0 && (s->control & TIMER_CTRL_ONESHOT)) |
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return;
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if (s->expires - now <= 0) { |
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/* Timer has expired. */
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s->int_level = 1;
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if (s->control & TIMER_CTRL_ONESHOT) {
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/* One-shot. */
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s->count = 0;
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} else {
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if ((s->control & TIMER_CTRL_PERIODIC) == 0) { |
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/* Free running. */
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if (s->control & TIMER_CTRL_32BIT)
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s->count = 0xffffffff;
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else
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s->count = 0xffff;
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} else {
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/* Periodic. */
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s->count = s->limit; |
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} |
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} |
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} |
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while (s->expires - now <= 0) { |
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arm_timer_reload(s); |
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} |
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/* Update interrupts. */
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if (s->int_level && (s->control & TIMER_CTRL_IE)) {
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pic_set_irq_new(s->pic, s->irq, 1);
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} else {
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pic_set_irq_new(s->pic, s->irq, 0);
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} |
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next = now; |
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if (next - s->expires < 0) |
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next = s->expires; |
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/* Schedule the next timer interrupt. */
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if (next == now) {
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qemu_del_timer(s->timer); |
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s->next_time = 0;
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} else if (next != s->next_time) { |
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qemu_mod_timer(s->timer, next); |
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s->next_time = next; |
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} |
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} |
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/* Return the current value of the timer. */
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static uint32_t arm_timer_getcount(arm_timer_state *s, int64_t now)
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{ |
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int64_t elapsed; |
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int64_t period; |
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if (s->count == 0) |
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return 0; |
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if ((s->control & TIMER_CTRL_ENABLE) == 0) |
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return s->count;
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elapsed = now - s->loaded; |
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period = s->expires - s->loaded; |
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/* If the timer should have expired then return 0. This can happen
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when the host timer signal doesnt occur immediately. It's better to
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have a timer appear to sit at zero for a while than have it wrap
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around before the guest interrupt is raised. */
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/* ??? Could we trigger the interrupt here? */
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if (elapsed > period)
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return 0; |
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/* We need to calculate count * elapsed / period without overfowing.
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Scale both elapsed and period so they fit in a 32-bit int. */
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while (period != (int32_t)period) {
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period >>= 1;
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elapsed >>= 1;
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} |
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return ((uint64_t)s->count * (uint64_t)(int32_t)elapsed)
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/ (int32_t)period; |
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} |
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uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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{ |
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arm_timer_state *s = (arm_timer_state *)opaque; |
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switch (offset >> 2) { |
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case 0: /* TimerLoad */ |
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case 6: /* TimerBGLoad */ |
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return s->limit;
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case 1: /* TimerValue */ |
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return arm_timer_getcount(s, qemu_get_clock(vm_clock));
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case 2: /* TimerControl */ |
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return s->control;
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case 4: /* TimerRIS */ |
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return s->int_level;
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case 5: /* TimerMIS */ |
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if ((s->control & TIMER_CTRL_IE) == 0) |
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return 0; |
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return s->int_level;
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default:
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cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n", offset);
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return 0; |
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} |
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} |
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static void arm_timer_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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arm_timer_state *s = (arm_timer_state *)opaque; |
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int64_t now; |
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now = qemu_get_clock(vm_clock); |
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switch (offset >> 2) { |
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case 0: /* TimerLoad */ |
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s->limit = value; |
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s->count = value; |
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s->expires = now; |
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arm_timer_reload(s); |
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break;
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case 1: /* TimerValue */ |
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/* ??? Linux seems to want to write to this readonly register.
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Ignore it. */
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break;
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case 2: /* TimerControl */ |
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Pause the timer if it is running. This may cause some
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inaccuracy dure to rounding, but avoids a whole lot of other
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messyness. */
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s->count = arm_timer_getcount(s, now); |
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} |
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s->control = value; |
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s->freq = s->raw_freq; |
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/* ??? Need to recalculate expiry time after changing divisor. */
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switch ((value >> 2) & 3) { |
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case 1: s->freq >>= 4; break; |
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case 2: s->freq >>= 8; break; |
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} |
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Restart the timer if still enabled. */
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s->expires = now; |
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arm_timer_reload(s); |
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} |
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break;
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case 3: /* TimerIntClr */ |
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s->int_level = 0;
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break;
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case 6: /* TimerBGLoad */ |
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s->limit = value; |
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break;
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default:
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cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n", offset);
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} |
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arm_timer_update(s, now); |
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} |
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static void arm_timer_tick(void *opaque) |
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{ |
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int64_t now; |
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now = qemu_get_clock(vm_clock); |
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arm_timer_update((arm_timer_state *)opaque, now); |
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} |
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static void *arm_timer_init(uint32_t freq, void *pic, int irq) |
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{ |
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arm_timer_state *s; |
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s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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s->pic = pic; |
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s->irq = irq; |
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s->raw_freq = s->freq = 1000000;
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s->control = TIMER_CTRL_IE; |
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s->count = 0xffffffff;
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s->timer = qemu_new_timer(vm_clock, arm_timer_tick, s); |
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/* ??? Save/restore. */
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return s;
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} |
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/* ARM PrimeCell SP804 dual timer module.
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Docs for this device don't seem to be publicly available. This
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implementation is based on gueswork, the linux kernel sources and the
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Integrator/CP timer modules. */
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typedef struct { |
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/* Include a pseudo-PIC device to merge the two interrupt sources. */
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arm_pic_handler handler; |
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void *timer[2]; |
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int level[2]; |
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uint32_t base; |
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/* The output PIC device. */
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void *pic;
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int irq;
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} sp804_state; |
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static void sp804_set_irq(void *opaque, int irq, int level) |
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{ |
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sp804_state *s = (sp804_state *)opaque; |
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s->level[irq] = level; |
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pic_set_irq_new(s->pic, s->irq, s->level[0] || s->level[1]); |
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} |
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static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) |
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{ |
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sp804_state *s = (sp804_state *)opaque; |
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/* ??? Don't know the PrimeCell ID for this device. */
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offset -= s->base; |
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if (offset < 0x20) { |
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return arm_timer_read(s->timer[0], offset); |
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} else {
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return arm_timer_read(s->timer[1], offset - 0x20); |
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} |
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} |
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static void sp804_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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sp804_state *s = (sp804_state *)opaque; |
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offset -= s->base; |
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if (offset < 0x20) { |
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arm_timer_write(s->timer[0], offset, value);
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} else {
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arm_timer_write(s->timer[1], offset - 0x20, value); |
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} |
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} |
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static CPUReadMemoryFunc *sp804_readfn[] = {
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sp804_read, |
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sp804_read, |
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sp804_read |
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}; |
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static CPUWriteMemoryFunc *sp804_writefn[] = {
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sp804_write, |
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sp804_write, |
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sp804_write |
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}; |
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void sp804_init(uint32_t base, void *pic, int irq) |
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{ |
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int iomemtype;
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sp804_state *s; |
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s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
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s->handler = sp804_set_irq; |
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s->base = base; |
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s->pic = pic; |
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s->irq = irq; |
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/* ??? The timers are actually configurable between 32kHz and 1MHz, but
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we don't implement that. */
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s->timer[0] = arm_timer_init(1000000, s, 0); |
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s->timer[1] = arm_timer_init(1000000, s, 1); |
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iomemtype = cpu_register_io_memory(0, sp804_readfn,
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sp804_writefn, s); |
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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/* ??? Save/restore. */
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} |
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/* Integrator/CP timer module. */
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typedef struct { |
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void *timer[3]; |
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uint32_t base; |
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} icp_pit_state; |
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static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) |
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{ |
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icp_pit_state *s = (icp_pit_state *)opaque; |
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int n;
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/* ??? Don't know the PrimeCell ID for this device. */
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offset -= s->base; |
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n = offset >> 8;
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if (n > 3) |
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cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
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return arm_timer_read(s->timer[n], offset & 0xff); |
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} |
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static void icp_pit_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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icp_pit_state *s = (icp_pit_state *)opaque; |
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int n;
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offset -= s->base; |
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n = offset >> 8;
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if (n > 3) |
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cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
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arm_timer_write(s->timer[n], offset & 0xff, value);
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} |
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static CPUReadMemoryFunc *icp_pit_readfn[] = {
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icp_pit_read, |
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icp_pit_read, |
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icp_pit_read |
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}; |
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static CPUWriteMemoryFunc *icp_pit_writefn[] = {
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icp_pit_write, |
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icp_pit_write, |
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icp_pit_write |
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}; |
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void icp_pit_init(uint32_t base, void *pic, int irq) |
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{ |
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int iomemtype;
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icp_pit_state *s; |
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s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
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s->base = base; |
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/* Timer 0 runs at the system clock speed (40MHz). */
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s->timer[0] = arm_timer_init(40000000, pic, irq); |
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/* The other two timers run at 1MHz. */
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s->timer[1] = arm_timer_init(1000000, pic, irq + 1); |
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s->timer[2] = arm_timer_init(1000000, pic, irq + 2); |
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iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
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icp_pit_writefn, s); |
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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/* ??? Save/restore. */
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} |
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