Revision 09b926d4
| b/hw/xio3130_downstream.c | ||
|---|---|---|
| 42 | 42 |
pcie_cap_flr_write_config(d, address, val, len); |
| 43 | 43 |
pcie_cap_slot_write_config(d, address, val, len); |
| 44 | 44 |
msi_write_config(d, address, val, len); |
| 45 |
/* TODO: AER */
|
|
| 45 |
pcie_aer_write_config(d, address, val, len);
|
|
| 46 | 46 |
} |
| 47 | 47 |
|
| 48 | 48 |
static void xio3130_downstream_reset(DeviceState *qdev) |
| ... | ... | |
| 61 | 61 |
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
| 62 | 62 |
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
| 63 | 63 |
int rc; |
| 64 |
int tmp; |
|
| 64 | 65 |
|
| 65 | 66 |
rc = pci_bridge_initfn(d); |
| 66 | 67 |
if (rc < 0) {
|
| ... | ... | |
| 76 | 77 |
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
| 77 | 78 |
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
| 78 | 79 |
if (rc < 0) {
|
| 79 |
return rc;
|
|
| 80 |
goto err_bridge;
|
|
| 80 | 81 |
} |
| 81 | 82 |
rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
| 82 | 83 |
XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); |
| 83 | 84 |
if (rc < 0) {
|
| 84 |
return rc;
|
|
| 85 |
goto err_bridge;
|
|
| 85 | 86 |
} |
| 86 | 87 |
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, |
| 87 | 88 |
p->port); |
| 88 | 89 |
if (rc < 0) {
|
| 89 |
return rc;
|
|
| 90 |
goto err_msi;
|
|
| 90 | 91 |
} |
| 91 | 92 |
pcie_cap_flr_init(d); /* TODO: implement FLR */ |
| 92 | 93 |
pcie_cap_deverr_init(d); |
| ... | ... | |
| 94 | 95 |
pcie_chassis_create(s->chassis); |
| 95 | 96 |
rc = pcie_chassis_add_slot(s); |
| 96 | 97 |
if (rc < 0) {
|
| 97 |
return rc;
|
|
| 98 |
goto err_pcie_cap;
|
|
| 98 | 99 |
} |
| 99 | 100 |
pcie_cap_ari_init(d); |
| 100 |
/* TODO: AER */ |
|
| 101 |
rc = pcie_aer_init(d, XIO3130_AER_OFFSET); |
|
| 102 |
if (rc < 0) {
|
|
| 103 |
goto err; |
|
| 104 |
} |
|
| 101 | 105 |
|
| 102 | 106 |
return 0; |
| 107 |
|
|
| 108 |
err: |
|
| 109 |
pcie_chassis_del_slot(s); |
|
| 110 |
err_pcie_cap: |
|
| 111 |
pcie_cap_exit(d); |
|
| 112 |
err_msi: |
|
| 113 |
msi_uninit(d); |
|
| 114 |
err_bridge: |
|
| 115 |
tmp = pci_bridge_exitfn(d); |
|
| 116 |
assert(!tmp); |
|
| 117 |
return rc; |
|
| 103 | 118 |
} |
| 104 | 119 |
|
| 105 | 120 |
static int xio3130_downstream_exitfn(PCIDevice *d) |
| 106 | 121 |
{
|
| 107 |
/* TODO: AER */ |
|
| 108 |
msi_uninit(d); |
|
| 122 |
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
|
| 123 |
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
|
| 124 |
PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
|
| 125 |
|
|
| 126 |
pcie_aer_exit(d); |
|
| 127 |
pcie_chassis_del_slot(s); |
|
| 109 | 128 |
pcie_cap_exit(d); |
| 129 |
msi_uninit(d); |
|
| 110 | 130 |
return pci_bridge_exitfn(d); |
| 111 | 131 |
} |
| 112 | 132 |
|
| ... | ... | |
| 144 | 164 |
.post_load = pcie_cap_slot_post_load, |
| 145 | 165 |
.fields = (VMStateField[]) {
|
| 146 | 166 |
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), |
| 147 |
/* TODO: AER */ |
|
| 167 |
VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, |
|
| 168 |
vmstate_pcie_aer_log, PCIEAERLog), |
|
| 148 | 169 |
VMSTATE_END_OF_LIST() |
| 149 | 170 |
} |
| 150 | 171 |
}; |
| ... | ... | |
| 166 | 187 |
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
|
| 167 | 188 |
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
|
| 168 | 189 |
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
|
| 169 |
/* TODO: AER */ |
|
| 190 |
DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
|
|
| 191 |
port.br.dev.exp.aer_log.log_max, |
|
| 192 |
PCIE_AER_LOG_MAX_DEFAULT), |
|
| 170 | 193 |
DEFINE_PROP_END_OF_LIST(), |
| 171 | 194 |
} |
| 172 | 195 |
}; |
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