Revision 09d85fb8
| b/target-i386/op_helper.c | ||
|---|---|---|
| 4350 | 4350 |
CPU86_LDouble tmp; |
| 4351 | 4351 |
target_ulong addr; |
| 4352 | 4352 |
|
| 4353 |
/* The operand must be 16 byte aligned */ |
|
| 4354 |
if (ptr & 0xf) {
|
|
| 4355 |
raise_exception(EXCP0D_GPF); |
|
| 4356 |
} |
|
| 4357 |
|
|
| 4353 | 4358 |
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
| 4354 | 4359 |
fptag = 0; |
| 4355 | 4360 |
for(i = 0; i < 8; i++) {
|
| ... | ... | |
| 4406 | 4411 |
CPU86_LDouble tmp; |
| 4407 | 4412 |
target_ulong addr; |
| 4408 | 4413 |
|
| 4414 |
/* The operand must be 16 byte aligned */ |
|
| 4415 |
if (ptr & 0xf) {
|
|
| 4416 |
raise_exception(EXCP0D_GPF); |
|
| 4417 |
} |
|
| 4418 |
|
|
| 4409 | 4419 |
env->fpuc = lduw(ptr); |
| 4410 | 4420 |
fpus = lduw(ptr + 2); |
| 4411 | 4421 |
fptag = lduw(ptr + 4); |
| b/target-i386/translate.c | ||
|---|---|---|
| 7502 | 7502 |
switch(op) {
|
| 7503 | 7503 |
case 0: /* fxsave */ |
| 7504 | 7504 |
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
| 7505 |
(s->flags & HF_EM_MASK))
|
|
| 7505 |
(s->prefix & PREFIX_LOCK))
|
|
| 7506 | 7506 |
goto illegal_op; |
| 7507 |
if (s->flags & HF_TS_MASK) {
|
|
| 7507 |
if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
|
|
| 7508 | 7508 |
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
| 7509 | 7509 |
break; |
| 7510 | 7510 |
} |
| ... | ... | |
| 7516 | 7516 |
break; |
| 7517 | 7517 |
case 1: /* fxrstor */ |
| 7518 | 7518 |
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
| 7519 |
(s->flags & HF_EM_MASK))
|
|
| 7519 |
(s->prefix & PREFIX_LOCK))
|
|
| 7520 | 7520 |
goto illegal_op; |
| 7521 |
if (s->flags & HF_TS_MASK) {
|
|
| 7521 |
if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
|
|
| 7522 | 7522 |
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
| 7523 | 7523 |
break; |
| 7524 | 7524 |
} |
Also available in: Unified diff