root / target-i386 / machine.c @ 09d85fb8
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#include "hw/hw.h" |
|---|---|
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#include "hw/boards.h" |
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#include "hw/pc.h" |
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#include "hw/isa.h" |
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#include "host-utils.h" |
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|
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#include "exec-all.h" |
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#include "kvm.h" |
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|
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static void cpu_put_seg(QEMUFile *f, SegmentCache *dt) |
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{
|
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qemu_put_be32(f, dt->selector); |
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qemu_put_betl(f, dt->base); |
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qemu_put_be32(f, dt->limit); |
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qemu_put_be32(f, dt->flags); |
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} |
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|
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static void cpu_get_seg(QEMUFile *f, SegmentCache *dt) |
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{
|
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dt->selector = qemu_get_be32(f); |
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dt->base = qemu_get_betl(f); |
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dt->limit = qemu_get_be32(f); |
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dt->flags = qemu_get_be32(f); |
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} |
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|
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void cpu_save(QEMUFile *f, void *opaque) |
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{
|
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CPUState *env = opaque; |
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uint16_t fptag, fpus, fpuc, fpregs_format; |
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uint32_t hflags; |
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int32_t a20_mask; |
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int32_t pending_irq; |
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int i, bit;
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|
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cpu_synchronize_state(env); |
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|
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for(i = 0; i < CPU_NB_REGS; i++) |
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qemu_put_betls(f, &env->regs[i]); |
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qemu_put_betls(f, &env->eip); |
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qemu_put_betls(f, &env->eflags); |
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hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
|
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qemu_put_be32s(f, &hflags); |
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|
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/* FPU */
|
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fpuc = env->fpuc; |
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fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
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fptag = 0;
|
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for(i = 0; i < 8; i++) { |
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fptag |= ((!env->fptags[i]) << i); |
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} |
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|
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qemu_put_be16s(f, &fpuc); |
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qemu_put_be16s(f, &fpus); |
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qemu_put_be16s(f, &fptag); |
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|
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#ifdef USE_X86LDOUBLE
|
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fpregs_format = 0;
|
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#else
|
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fpregs_format = 1;
|
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#endif
|
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qemu_put_be16s(f, &fpregs_format); |
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|
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for(i = 0; i < 8; i++) { |
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#ifdef USE_X86LDOUBLE
|
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{
|
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uint64_t mant; |
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uint16_t exp; |
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/* we save the real CPU data (in case of MMX usage only 'mant'
|
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contains the MMX register */
|
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cpu_get_fp80(&mant, &exp, env->fpregs[i].d); |
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qemu_put_be64(f, mant); |
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qemu_put_be16(f, exp); |
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} |
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#else
|
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/* if we use doubles for float emulation, we save the doubles to
|
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avoid losing information in case of MMX usage. It can give
|
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problems if the image is restored on a CPU where long
|
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doubles are used instead. */
|
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qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
|
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#endif
|
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} |
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|
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for(i = 0; i < 6; i++) |
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cpu_put_seg(f, &env->segs[i]); |
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cpu_put_seg(f, &env->ldt); |
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cpu_put_seg(f, &env->tr); |
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cpu_put_seg(f, &env->gdt); |
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cpu_put_seg(f, &env->idt); |
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|
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qemu_put_be32s(f, &env->sysenter_cs); |
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qemu_put_betls(f, &env->sysenter_esp); |
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qemu_put_betls(f, &env->sysenter_eip); |
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|
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qemu_put_betls(f, &env->cr[0]);
|
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qemu_put_betls(f, &env->cr[2]);
|
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qemu_put_betls(f, &env->cr[3]);
|
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qemu_put_betls(f, &env->cr[4]);
|
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|
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for(i = 0; i < 8; i++) |
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qemu_put_betls(f, &env->dr[i]); |
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|
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/* MMU */
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a20_mask = (int32_t) env->a20_mask; |
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qemu_put_sbe32s(f, &a20_mask); |
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|
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/* XMM */
|
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qemu_put_be32s(f, &env->mxcsr); |
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for(i = 0; i < CPU_NB_REGS; i++) { |
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qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
|
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qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
|
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} |
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|
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#ifdef TARGET_X86_64
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qemu_put_be64s(f, &env->efer); |
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qemu_put_be64s(f, &env->star); |
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qemu_put_be64s(f, &env->lstar); |
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qemu_put_be64s(f, &env->cstar); |
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qemu_put_be64s(f, &env->fmask); |
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qemu_put_be64s(f, &env->kernelgsbase); |
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#endif
|
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qemu_put_be32s(f, &env->smbase); |
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|
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qemu_put_be64s(f, &env->pat); |
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qemu_put_be32s(f, &env->hflags2); |
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|
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qemu_put_be64s(f, &env->vm_hsave); |
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qemu_put_be64s(f, &env->vm_vmcb); |
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qemu_put_be64s(f, &env->tsc_offset); |
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qemu_put_be64s(f, &env->intercept); |
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qemu_put_be16s(f, &env->intercept_cr_read); |
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qemu_put_be16s(f, &env->intercept_cr_write); |
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qemu_put_be16s(f, &env->intercept_dr_read); |
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qemu_put_be16s(f, &env->intercept_dr_write); |
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qemu_put_be32s(f, &env->intercept_exceptions); |
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qemu_put_8s(f, &env->v_tpr); |
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|
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/* MTRRs */
|
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for(i = 0; i < 11; i++) |
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qemu_put_be64s(f, &env->mtrr_fixed[i]); |
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qemu_put_be64s(f, &env->mtrr_deftype); |
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for(i = 0; i < 8; i++) { |
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qemu_put_be64s(f, &env->mtrr_var[i].base); |
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qemu_put_be64s(f, &env->mtrr_var[i].mask); |
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} |
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|
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/* KVM-related states */
|
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|
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/* There can only be one pending IRQ set in the bitmap at a time, so try
|
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to find it and save its number instead (-1 for none). */
|
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pending_irq = -1;
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for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) { |
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if (env->interrupt_bitmap[i]) {
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bit = ctz64(env->interrupt_bitmap[i]); |
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pending_irq = i * 64 + bit;
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break;
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} |
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} |
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qemu_put_sbe32s(f, &pending_irq); |
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qemu_put_be32s(f, &env->mp_state); |
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qemu_put_be64s(f, &env->tsc); |
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|
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/* MCE */
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qemu_put_be64s(f, &env->mcg_cap); |
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if (env->mcg_cap) {
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qemu_put_be64s(f, &env->mcg_status); |
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qemu_put_be64s(f, &env->mcg_ctl); |
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for (i = 0; i < (env->mcg_cap & 0xff); i++) { |
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qemu_put_be64s(f, &env->mce_banks[4*i]);
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qemu_put_be64s(f, &env->mce_banks[4*i + 1]); |
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qemu_put_be64s(f, &env->mce_banks[4*i + 2]); |
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qemu_put_be64s(f, &env->mce_banks[4*i + 3]); |
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} |
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} |
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qemu_put_be64s(f, &env->tsc_aux); |
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} |
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|
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#ifdef USE_X86LDOUBLE
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/* XXX: add that in a FPU generic layer */
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union x86_longdouble {
|
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uint64_t mant; |
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uint16_t exp; |
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}; |
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|
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#define MANTD1(fp) (fp & ((1LL << 52) - 1)) |
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#define EXPBIAS1 1023 |
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#define EXPD1(fp) ((fp >> 52) & 0x7FF) |
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#define SIGND1(fp) ((fp >> 32) & 0x80000000) |
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|
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static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp) |
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{
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int e;
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/* mantissa */
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p->mant = (MANTD1(temp) << 11) | (1LL << 63); |
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/* exponent + sign */
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e = EXPD1(temp) - EXPBIAS1 + 16383;
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e |= SIGND1(temp) >> 16;
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p->exp = e; |
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} |
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#endif
|
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|
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int cpu_load(QEMUFile *f, void *opaque, int version_id) |
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{
|
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CPUState *env = opaque; |
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int i, guess_mmx;
|
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uint32_t hflags; |
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uint16_t fpus, fpuc, fptag, fpregs_format; |
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int32_t a20_mask; |
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int32_t pending_irq; |
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|
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cpu_synchronize_state(env); |
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if (version_id < 3 || version_id > CPU_SAVE_VERSION) |
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return -EINVAL;
|
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for(i = 0; i < CPU_NB_REGS; i++) |
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qemu_get_betls(f, &env->regs[i]); |
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qemu_get_betls(f, &env->eip); |
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qemu_get_betls(f, &env->eflags); |
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qemu_get_be32s(f, &hflags); |
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|
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qemu_get_be16s(f, &fpuc); |
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qemu_get_be16s(f, &fpus); |
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qemu_get_be16s(f, &fptag); |
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qemu_get_be16s(f, &fpregs_format); |
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|
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/* NOTE: we cannot always restore the FPU state if the image come
|
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from a host with a different 'USE_X86LDOUBLE' define. We guess
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if we are in an MMX state to restore correctly in that case. */
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guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0); |
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for(i = 0; i < 8; i++) { |
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uint64_t mant; |
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uint16_t exp; |
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|
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switch(fpregs_format) {
|
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case 0: |
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mant = qemu_get_be64(f); |
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exp = qemu_get_be16(f); |
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#ifdef USE_X86LDOUBLE
|
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env->fpregs[i].d = cpu_set_fp80(mant, exp); |
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#else
|
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/* difficult case */
|
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if (guess_mmx)
|
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env->fpregs[i].mmx.MMX_Q(0) = mant;
|
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else
|
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env->fpregs[i].d = cpu_set_fp80(mant, exp); |
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#endif
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break;
|
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case 1: |
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mant = qemu_get_be64(f); |
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#ifdef USE_X86LDOUBLE
|
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{
|
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union x86_longdouble *p;
|
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/* difficult case */
|
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p = (void *)&env->fpregs[i];
|
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if (guess_mmx) {
|
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p->mant = mant; |
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p->exp = 0xffff;
|
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} else {
|
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fp64_to_fp80(p, mant); |
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} |
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} |
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#else
|
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env->fpregs[i].mmx.MMX_Q(0) = mant;
|
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#endif
|
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break;
|
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default:
|
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return -EINVAL;
|
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} |
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} |
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|
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env->fpuc = fpuc; |
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/* XXX: restore FPU round state */
|
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env->fpstt = (fpus >> 11) & 7; |
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env->fpus = fpus & ~0x3800;
|
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fptag ^= 0xff;
|
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for(i = 0; i < 8; i++) { |
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env->fptags[i] = (fptag >> i) & 1;
|
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} |
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|
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for(i = 0; i < 6; i++) |
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cpu_get_seg(f, &env->segs[i]); |
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cpu_get_seg(f, &env->ldt); |
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cpu_get_seg(f, &env->tr); |
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cpu_get_seg(f, &env->gdt); |
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cpu_get_seg(f, &env->idt); |
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|
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qemu_get_be32s(f, &env->sysenter_cs); |
| 286 |
if (version_id >= 7) { |
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qemu_get_betls(f, &env->sysenter_esp); |
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qemu_get_betls(f, &env->sysenter_eip); |
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} else {
|
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env->sysenter_esp = qemu_get_be32(f); |
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env->sysenter_eip = qemu_get_be32(f); |
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} |
| 293 |
|
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qemu_get_betls(f, &env->cr[0]);
|
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qemu_get_betls(f, &env->cr[2]);
|
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qemu_get_betls(f, &env->cr[3]);
|
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qemu_get_betls(f, &env->cr[4]);
|
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|
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for(i = 0; i < 8; i++) |
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qemu_get_betls(f, &env->dr[i]); |
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cpu_breakpoint_remove_all(env, BP_CPU); |
| 302 |
cpu_watchpoint_remove_all(env, BP_CPU); |
| 303 |
for (i = 0; i < 4; i++) |
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hw_breakpoint_insert(env, i); |
| 305 |
|
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/* MMU */
|
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qemu_get_sbe32s(f, &a20_mask); |
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env->a20_mask = a20_mask; |
| 309 |
|
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qemu_get_be32s(f, &env->mxcsr); |
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for(i = 0; i < CPU_NB_REGS; i++) { |
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qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
|
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qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
|
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} |
| 315 |
|
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#ifdef TARGET_X86_64
|
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qemu_get_be64s(f, &env->efer); |
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qemu_get_be64s(f, &env->star); |
| 319 |
qemu_get_be64s(f, &env->lstar); |
| 320 |
qemu_get_be64s(f, &env->cstar); |
| 321 |
qemu_get_be64s(f, &env->fmask); |
| 322 |
qemu_get_be64s(f, &env->kernelgsbase); |
| 323 |
#endif
|
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if (version_id >= 4) { |
| 325 |
qemu_get_be32s(f, &env->smbase); |
| 326 |
} |
| 327 |
if (version_id >= 5) { |
| 328 |
qemu_get_be64s(f, &env->pat); |
| 329 |
qemu_get_be32s(f, &env->hflags2); |
| 330 |
if (version_id < 6) |
| 331 |
qemu_get_be32s(f, &env->halted); |
| 332 |
|
| 333 |
qemu_get_be64s(f, &env->vm_hsave); |
| 334 |
qemu_get_be64s(f, &env->vm_vmcb); |
| 335 |
qemu_get_be64s(f, &env->tsc_offset); |
| 336 |
qemu_get_be64s(f, &env->intercept); |
| 337 |
qemu_get_be16s(f, &env->intercept_cr_read); |
| 338 |
qemu_get_be16s(f, &env->intercept_cr_write); |
| 339 |
qemu_get_be16s(f, &env->intercept_dr_read); |
| 340 |
qemu_get_be16s(f, &env->intercept_dr_write); |
| 341 |
qemu_get_be32s(f, &env->intercept_exceptions); |
| 342 |
qemu_get_8s(f, &env->v_tpr); |
| 343 |
} |
| 344 |
|
| 345 |
if (version_id >= 8) { |
| 346 |
/* MTRRs */
|
| 347 |
for(i = 0; i < 11; i++) |
| 348 |
qemu_get_be64s(f, &env->mtrr_fixed[i]); |
| 349 |
qemu_get_be64s(f, &env->mtrr_deftype); |
| 350 |
for(i = 0; i < 8; i++) { |
| 351 |
qemu_get_be64s(f, &env->mtrr_var[i].base); |
| 352 |
qemu_get_be64s(f, &env->mtrr_var[i].mask); |
| 353 |
} |
| 354 |
} |
| 355 |
|
| 356 |
if (version_id >= 9) { |
| 357 |
qemu_get_sbe32s(f, &pending_irq); |
| 358 |
memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap)); |
| 359 |
if (pending_irq >= 0) { |
| 360 |
env->interrupt_bitmap[pending_irq / 64] |=
|
| 361 |
(uint64_t)1 << (pending_irq % 64); |
| 362 |
} |
| 363 |
qemu_get_be32s(f, &env->mp_state); |
| 364 |
qemu_get_be64s(f, &env->tsc); |
| 365 |
} |
| 366 |
|
| 367 |
if (version_id >= 10) { |
| 368 |
qemu_get_be64s(f, &env->mcg_cap); |
| 369 |
if (env->mcg_cap) {
|
| 370 |
qemu_get_be64s(f, &env->mcg_status); |
| 371 |
qemu_get_be64s(f, &env->mcg_ctl); |
| 372 |
for (i = 0; i < (env->mcg_cap & 0xff); i++) { |
| 373 |
qemu_get_be64s(f, &env->mce_banks[4*i]);
|
| 374 |
qemu_get_be64s(f, &env->mce_banks[4*i + 1]); |
| 375 |
qemu_get_be64s(f, &env->mce_banks[4*i + 2]); |
| 376 |
qemu_get_be64s(f, &env->mce_banks[4*i + 3]); |
| 377 |
} |
| 378 |
} |
| 379 |
} |
| 380 |
|
| 381 |
if (version_id >= 11) { |
| 382 |
qemu_get_be64s(f, &env->tsc_aux); |
| 383 |
} |
| 384 |
/* XXX: ensure compatiblity for halted bit ? */
|
| 385 |
/* XXX: compute redundant hflags bits */
|
| 386 |
env->hflags = hflags; |
| 387 |
tlb_flush(env, 1);
|
| 388 |
return 0; |
| 389 |
} |