target-i386: Fix exceptions for fxsave/fxrstor
This patch corrects the following aspects of exception generation infxsave/fxrstor:
tcg: allocate s->op_dead_iargs dynamically
Similarly to what is already done in tcg_liveness_analysis() whenUSE_LIVENESS_ANALYSIS is not set.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: remove dead code
bsd-user: fix "#if 0"'d printf()
Make an "#if 0"'d printf() in load_elf_binary() reflect what the actualcode does (see commit 3bc0bdcaadef1100ce2413af818d9c8e2f6319fc).
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
eepro100: Add more i825xx devices
The new devices added here are still not functional -partially because some patches are still missing,partially because I cannot test them. Neverthelessthey belong to the same family and will be supportedby this driver some day....
eepro100: Remove unused device status entries
A lot of entries are unused (they were added by copy + pastefrom other drivers during development of eepro100.c).
Removing them from nic_save, nic_load makes anyold saved status incompatible, so a new version...
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the contentof a 32-bit MSR, which can be freely set by the OS. This allows CPUlocal data to be queried by userspace.Linux uses this to allow a fast implementation of the getcpu()...
target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.Those include insertq and extrq, which are doing shift and mask onXMM registers, in two versions (immediate shift/length values andstored in another XMM register)....
target-i386: add lock mov cr0 = cr8
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode.If you use the LOCK prefix with "mov CR0", it accesses CR8 instead.This behavior is guarded by the CR8_LEGACY CPUID bit(Fn8000_0001:ECX1).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>...
tcg/i386: add support for ext{8,16}u_i32 TCG ops
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