Revision 0ae18cee hw/mips_mipssim.c
| b/hw/mips_mipssim.c | ||
|---|---|---|
| 175 | 175 |
if (serial_hds[0]) |
| 176 | 176 |
serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
| 177 | 177 |
|
| 178 |
if (nd_table[0].vlan) {
|
|
| 179 |
if (nd_table[0].model == NULL |
|
| 180 |
|| strcmp(nd_table[0].model, "mipsnet") == 0) {
|
|
| 181 |
/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ |
|
| 182 |
mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
|
| 183 |
} else if (strcmp(nd_table[0].model, "?") == 0) {
|
|
| 184 |
fprintf(stderr, "qemu: Supported NICs: mipsnet\n"); |
|
| 185 |
exit (1); |
|
| 186 |
} else {
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| 187 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
|
| 188 |
exit (1); |
|
| 189 |
} |
|
| 190 |
} |
|
| 178 |
if (nd_table[0].vlan) |
|
| 179 |
/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ |
|
| 180 |
mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
|
| 191 | 181 |
} |
| 192 | 182 |
|
| 193 | 183 |
QEMUMachine mips_mipssim_machine = {
|
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