Revision 0b36f4cd target-arm/translate.c

b/target-arm/translate.c
4783 4783
            } else if (op < 10) {
4784 4784
                /* Shift by immediate and narrow:
4785 4785
                   VSHRN, VRSHRN, VQSHRN, VQRSHRN.  */
4786
                int input_unsigned = (op == 8) ? !u : u;
4787

  
4786 4788
                shift = shift - (1 << (size + 3));
4787 4789
                size++;
4788 4790
                switch (size) {
......
4809 4811
                    if (size == 3) {
4810 4812
                        neon_load_reg64(cpu_V0, rm + pass);
4811 4813
                        if (q) {
4812
                          if (u)
4813
                            gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
4814
                          else
4815
                            gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
4814
                            if (input_unsigned) {
4815
                                gen_helper_neon_rshl_u64(cpu_V0, cpu_V0,
4816
                                                         tmp64);
4817
                            } else {
4818
                                gen_helper_neon_rshl_s64(cpu_V0, cpu_V0,
4819
                                                         tmp64);
4820
                            }
4816 4821
                        } else {
4817
                          if (u)
4818
                            gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
4819
                          else
4820
                            gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
4822
                            if (input_unsigned) {
4823
                                gen_helper_neon_shl_u64(cpu_V0, cpu_V0,
4824
                                                        tmp64);
4825
                            } else {
4826
                                gen_helper_neon_shl_s64(cpu_V0, cpu_V0,
4827
                                                        tmp64);
4828
                            }
4821 4829
                        }
4822 4830
                    } else {
4823 4831
                        tmp = neon_load_reg(rm + pass, 0);
4824
                        gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4832
                        gen_neon_shift_narrow(size, tmp, tmp2, q,
4833
                                              input_unsigned);
4825 4834
                        tmp3 = neon_load_reg(rm + pass, 1);
4826
                        gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4835
                        gen_neon_shift_narrow(size, tmp3, tmp2, q,
4836
                                              input_unsigned);
4827 4837
                        tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4828 4838
                        dead_tmp(tmp);
4829 4839
                        dead_tmp(tmp3);
4830 4840
                    }
4831 4841
                    tmp = new_tmp();
4832
                    if (op == 8 && !u) {
4833
                        gen_neon_narrow(size - 1, tmp, cpu_V0);
4842
                    if (op == 8) {
4843
                        if (u) { /* VQSHRUN / VQRSHRUN */
4844
                            gen_neon_unarrow_sats(size - 1, tmp, cpu_V0);
4845
                        } else { /* VSHRN / VRSHRN */
4846
                            gen_neon_narrow(size - 1, tmp, cpu_V0);
4847
                        }
4834 4848
                    } else {
4835
                        if (op == 8)
4836
                            gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4837
                        else
4849
                        if (u) { /* VQSHRN / VQRSHRN */
4838 4850
                            gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4851
                        } else { /* VQSHRN / VQRSHRN */
4852
                            gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4853
                        }
4839 4854
                    }
4840 4855
                    neon_store_reg(rd, pass, tmp);
4841 4856
                } /* for pass */

Also available in: Unified diff