root / hw / acpi_piix4.c @ 0b8f9be6
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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "apm.h" |
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#include "pm_smbus.h" |
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#include "pci.h" |
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#include "acpi.h" |
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0) |
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#endif
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#define ACPI_DBG_IO_ADDR 0xb044 |
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#define GPE_BASE 0xafe0 |
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#define PCI_BASE 0xae00 |
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#define PCI_EJ_BASE 0xae08 |
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struct gpe_regs {
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uint16_t sts; /* status */
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uint16_t en; /* enabled */
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}; |
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struct pci_status {
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uint32_t up; |
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uint32_t down; |
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}; |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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APMState apm; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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PMSMBus smb; |
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uint32_t smb_io_base; |
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qemu_irq irq; |
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qemu_irq cmos_s3; |
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qemu_irq smi_irq; |
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int kvm_enabled;
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|
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/* for pci hotplug */
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struct gpe_regs gpe;
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struct pci_status pci0_status;
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} PIIX4PMState; |
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{ |
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uint32_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); |
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return d & 0xffffff; |
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} |
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static int get_pmsts(PIIX4PMState *s) |
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{ |
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int64_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, |
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get_ticks_per_sec()); |
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if (d >= s->tmr_overflow_time)
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s->pmsts |= ACPI_BITMASK_TIMER_STATUS; |
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return s->pmsts;
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} |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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int64_t expire_time; |
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pmsts = get_pmsts(s); |
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sci_level = (((pmsts & s->pmen) & |
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(ACPI_BITMASK_RT_CLOCK_ENABLE | |
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ACPI_BITMASK_POWER_BUTTON_ENABLE | |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS)) { |
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expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), |
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PM_TIMER_FREQUENCY); |
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qemu_mod_timer(s->tmr_timer, expire_time); |
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} else {
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qemu_del_timer(s->tmr_timer); |
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} |
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} |
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static void pm_tmr_timer(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_update_sci(s); |
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} |
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = get_pmsts(s); |
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if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, |
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get_ticks_per_sec()); |
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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} |
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s->pmsts &= ~val; |
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pm_update_sci(s); |
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} |
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break;
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case 0x02: |
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s->pmen = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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{ |
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int sus_typ;
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s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE); |
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if (val & ACPI_BITMASK_SLEEP_ENABLE) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7; |
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switch(sus_typ) {
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case 0: /* soft power off */ |
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qemu_system_shutdown_request(); |
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break;
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case 1: |
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/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
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Pretend that resume was caused by power button */
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s->pmsts |= (ACPI_BITMASK_WAKE_STATUS | |
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ACPI_BITMASK_POWER_BUTTON_STATUS); |
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qemu_system_reset_request(); |
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if (s->cmos_s3) {
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qemu_irq_raise(s->cmos_s3); |
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} |
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default:
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break;
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} |
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} |
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} |
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break;
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default:
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break;
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} |
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PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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val = get_pmsts(s); |
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break;
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case 0x02: |
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val = s->pmen; |
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break;
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case 0x04: |
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val = s->pmcntrl; |
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break;
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default:
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val = 0;
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break;
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} |
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PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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// PIIX4PMState *s = opaque;
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PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val); |
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x08: |
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val = get_pmtmr(s); |
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break;
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default:
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val = 0;
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break;
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} |
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PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val;
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} |
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static void apm_ctrl_changed(uint32_t val, void *arg) |
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{ |
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PIIX4PMState *s = arg; |
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE; |
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} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE; |
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} |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
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} |
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static void pm_io_space_update(PIIX4PMState *s) |
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{ |
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uint32_t pm_io_base; |
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if (s->dev.config[0x80] & 1) { |
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
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} |
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} |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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pci_default_write_config(d, address, val, len); |
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if (range_covers_byte(address, len, 0x80)) |
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pm_io_space_update((PIIX4PMState *)d); |
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} |
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
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static const VMStateDescription vmstate_acpi = { |
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.name = "piix4_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState), |
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VMSTATE_UINT16(pmsts, PIIX4PMState), |
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VMSTATE_UINT16(pmen, PIIX4PMState), |
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VMSTATE_UINT16(pmcntrl, PIIX4PMState), |
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr_timer, PIIX4PMState), |
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VMSTATE_INT64(tmr_overflow_time, PIIX4PMState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
302 |
|
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static void piix4_reset(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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uint8_t *pci_conf = s->dev.config; |
307 |
|
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pci_conf[0x58] = 0; |
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pci_conf[0x59] = 0; |
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pci_conf[0x5a] = 0; |
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pci_conf[0x5b] = 0; |
312 |
|
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02; |
316 |
} |
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} |
318 |
|
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static void piix4_powerdown(void *opaque, int irq, int power_failing) |
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{ |
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PIIX4PMState *s = opaque; |
322 |
|
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if (!s) {
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qemu_system_shutdown_request(); |
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} else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) { |
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s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS; |
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pm_update_sci(s); |
328 |
} |
329 |
} |
330 |
|
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static int piix4_pm_initfn(PCIDevice *dev) |
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{ |
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PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
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uint8_t *pci_conf; |
335 |
|
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pci_conf = s->dev.config; |
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
338 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
339 |
pci_conf[0x06] = 0x80; |
340 |
pci_conf[0x07] = 0x02; |
341 |
pci_conf[0x08] = 0x03; // revision number |
342 |
pci_conf[0x09] = 0x00; |
343 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
344 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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pci_conf[0x3d] = 0x01; // interrupt pin 1 |
346 |
|
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pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
348 |
|
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/* APM */
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apm_init(&s->apm, apm_ctrl_changed, s); |
351 |
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
353 |
|
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if (s->kvm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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356 |
* support SMM mode. */
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357 |
pci_conf[0x5B] = 0x02; |
358 |
} |
359 |
|
360 |
/* XXX: which specification is used ? The i82731AB has different
|
361 |
mappings */
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362 |
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
363 |
pci_conf[0x63] = 0x60; |
364 |
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
365 |
(serial_hds[1] != NULL ? 0x90 : 0); |
366 |
|
367 |
pci_conf[0x90] = s->smb_io_base | 1; |
368 |
pci_conf[0x91] = s->smb_io_base >> 8; |
369 |
pci_conf[0xd2] = 0x09; |
370 |
register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
371 |
register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); |
372 |
|
373 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
374 |
|
375 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
|
376 |
|
377 |
pm_smbus_init(&s->dev.qdev, &s->smb); |
378 |
qemu_register_reset(piix4_reset, s); |
379 |
piix4_acpi_system_hot_add_init(dev->bus, s); |
380 |
|
381 |
return 0; |
382 |
} |
383 |
|
384 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
385 |
qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, |
386 |
int kvm_enabled)
|
387 |
{ |
388 |
PCIDevice *dev; |
389 |
PIIX4PMState *s; |
390 |
|
391 |
dev = pci_create(bus, devfn, "PIIX4_PM");
|
392 |
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
393 |
|
394 |
s = DO_UPCAST(PIIX4PMState, dev, dev); |
395 |
s->irq = sci_irq; |
396 |
s->cmos_s3 = cmos_s3; |
397 |
s->smi_irq = smi_irq; |
398 |
s->kvm_enabled = kvm_enabled; |
399 |
|
400 |
qdev_init_nofail(&dev->qdev); |
401 |
|
402 |
return s->smb.smbus;
|
403 |
} |
404 |
|
405 |
static PCIDeviceInfo piix4_pm_info = {
|
406 |
.qdev.name = "PIIX4_PM",
|
407 |
.qdev.desc = "PM",
|
408 |
.qdev.size = sizeof(PIIX4PMState),
|
409 |
.qdev.vmsd = &vmstate_acpi, |
410 |
.init = piix4_pm_initfn, |
411 |
.config_write = pm_write_config, |
412 |
.qdev.props = (Property[]) { |
413 |
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), |
414 |
DEFINE_PROP_END_OF_LIST(), |
415 |
} |
416 |
}; |
417 |
|
418 |
static void piix4_pm_register(void) |
419 |
{ |
420 |
pci_qdev_register(&piix4_pm_info); |
421 |
} |
422 |
|
423 |
device_init(piix4_pm_register); |
424 |
|
425 |
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
426 |
{ |
427 |
if (addr & 1) |
428 |
return (val >> 8) & 0xff; |
429 |
return val & 0xff; |
430 |
} |
431 |
|
432 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
433 |
{ |
434 |
uint32_t val = 0;
|
435 |
struct gpe_regs *g = opaque;
|
436 |
switch (addr) {
|
437 |
case GPE_BASE:
|
438 |
case GPE_BASE + 1: |
439 |
val = gpe_read_val(g->sts, addr); |
440 |
break;
|
441 |
case GPE_BASE + 2: |
442 |
case GPE_BASE + 3: |
443 |
val = gpe_read_val(g->en, addr); |
444 |
break;
|
445 |
default:
|
446 |
break;
|
447 |
} |
448 |
|
449 |
PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
|
450 |
return val;
|
451 |
} |
452 |
|
453 |
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) |
454 |
{ |
455 |
if (addr & 1) |
456 |
*cur = (*cur & 0xff) | (val << 8); |
457 |
else
|
458 |
*cur = (*cur & 0xff00) | (val & 0xff); |
459 |
} |
460 |
|
461 |
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) |
462 |
{ |
463 |
uint16_t x1, x0 = val & 0xff;
|
464 |
int shift = (addr & 1) ? 8 : 0; |
465 |
|
466 |
x1 = (*cur >> shift) & 0xff;
|
467 |
|
468 |
x1 = x1 & ~x0; |
469 |
|
470 |
*cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); |
471 |
} |
472 |
|
473 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
474 |
{ |
475 |
struct gpe_regs *g = opaque;
|
476 |
switch (addr) {
|
477 |
case GPE_BASE:
|
478 |
case GPE_BASE + 1: |
479 |
gpe_reset_val(&g->sts, addr, val); |
480 |
break;
|
481 |
case GPE_BASE + 2: |
482 |
case GPE_BASE + 3: |
483 |
gpe_write_val(&g->en, addr, val); |
484 |
break;
|
485 |
default:
|
486 |
break;
|
487 |
} |
488 |
|
489 |
PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
|
490 |
} |
491 |
|
492 |
static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
493 |
{ |
494 |
uint32_t val = 0;
|
495 |
struct pci_status *g = opaque;
|
496 |
switch (addr) {
|
497 |
case PCI_BASE:
|
498 |
val = g->up; |
499 |
break;
|
500 |
case PCI_BASE + 4: |
501 |
val = g->down; |
502 |
break;
|
503 |
default:
|
504 |
break;
|
505 |
} |
506 |
|
507 |
PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
|
508 |
return val;
|
509 |
} |
510 |
|
511 |
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
512 |
{ |
513 |
struct pci_status *g = opaque;
|
514 |
switch (addr) {
|
515 |
case PCI_BASE:
|
516 |
g->up = val; |
517 |
break;
|
518 |
case PCI_BASE + 4: |
519 |
g->down = val; |
520 |
break;
|
521 |
} |
522 |
|
523 |
PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
|
524 |
} |
525 |
|
526 |
static uint32_t pciej_read(void *opaque, uint32_t addr) |
527 |
{ |
528 |
PIIX4_DPRINTF("pciej read %x\n", addr);
|
529 |
return 0; |
530 |
} |
531 |
|
532 |
static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
533 |
{ |
534 |
BusState *bus = opaque; |
535 |
DeviceState *qdev, *next; |
536 |
PCIDevice *dev; |
537 |
int slot = ffs(val) - 1; |
538 |
|
539 |
QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
540 |
dev = DO_UPCAST(PCIDevice, qdev, qdev); |
541 |
if (PCI_SLOT(dev->devfn) == slot) {
|
542 |
qdev_free(qdev); |
543 |
} |
544 |
} |
545 |
|
546 |
|
547 |
PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
|
548 |
} |
549 |
|
550 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state); |
551 |
|
552 |
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
553 |
{ |
554 |
struct gpe_regs *gpe = &s->gpe;
|
555 |
struct pci_status *pci0_status = &s->pci0_status;
|
556 |
|
557 |
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe); |
558 |
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe); |
559 |
|
560 |
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); |
561 |
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); |
562 |
|
563 |
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); |
564 |
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); |
565 |
|
566 |
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
567 |
} |
568 |
|
569 |
static void enable_device(PIIX4PMState *s, int slot) |
570 |
{ |
571 |
s->gpe.sts |= 2;
|
572 |
s->pci0_status.up |= (1 << slot);
|
573 |
} |
574 |
|
575 |
static void disable_device(PIIX4PMState *s, int slot) |
576 |
{ |
577 |
s->gpe.sts |= 2;
|
578 |
s->pci0_status.down |= (1 << slot);
|
579 |
} |
580 |
|
581 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state) |
582 |
{ |
583 |
int slot = PCI_SLOT(dev->devfn);
|
584 |
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
585 |
DO_UPCAST(PCIDevice, qdev, qdev)); |
586 |
|
587 |
s->pci0_status.up = 0;
|
588 |
s->pci0_status.down = 0;
|
589 |
if (state) {
|
590 |
enable_device(s, slot); |
591 |
} else {
|
592 |
disable_device(s, slot); |
593 |
} |
594 |
if (s->gpe.en & 2) { |
595 |
qemu_set_irq(s->irq, 1);
|
596 |
qemu_set_irq(s->irq, 0);
|
597 |
} |
598 |
return 0; |
599 |
} |