Revision 0bacd130 hw/acpi.c
| b/hw/acpi.c | ||
|---|---|---|
| 53 | 53 |
qemu_irq irq; |
| 54 | 54 |
} PIIX4PMState; |
| 55 | 55 |
|
| 56 |
#define RSM_STS (1 << 15) |
|
| 57 |
#define PWRBTN_STS (1 << 8) |
|
| 56 | 58 |
#define RTC_EN (1 << 10) |
| 57 | 59 |
#define PWRBTN_EN (1 << 8) |
| 58 | 60 |
#define GBL_EN (1 << 5) |
| ... | ... | |
| 151 | 153 |
case 0: /* soft power off */ |
| 152 | 154 |
qemu_system_shutdown_request(); |
| 153 | 155 |
break; |
| 156 |
case 1: |
|
| 157 |
/* RSM_STS should be set on resume. Pretend that resume |
|
| 158 |
was caused by power button */ |
|
| 159 |
s->pmsts |= (RSM_STS | PWRBTN_STS); |
|
| 160 |
qemu_system_reset_request(); |
|
| 161 |
#if defined(TARGET_I386) |
|
| 162 |
cmos_set_s3_resume(); |
|
| 163 |
#endif |
|
| 154 | 164 |
default: |
| 155 | 165 |
break; |
| 156 | 166 |
} |
| ... | ... | |
| 471 | 481 |
return 0; |
| 472 | 482 |
} |
| 473 | 483 |
|
| 484 |
static void piix4_reset(void *opaque) |
|
| 485 |
{
|
|
| 486 |
PIIX4PMState *s = opaque; |
|
| 487 |
uint8_t *pci_conf = s->dev.config; |
|
| 488 |
|
|
| 489 |
pci_conf[0x58] = 0; |
|
| 490 |
pci_conf[0x59] = 0; |
|
| 491 |
pci_conf[0x5a] = 0; |
|
| 492 |
pci_conf[0x5b] = 0; |
|
| 493 |
} |
|
| 494 |
|
|
| 474 | 495 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
| 475 | 496 |
qemu_irq sci_irq) |
| 476 | 497 |
{
|
| ... | ... | |
| 527 | 548 |
|
| 528 | 549 |
s->smbus = i2c_init_bus(); |
| 529 | 550 |
s->irq = sci_irq; |
| 551 |
qemu_register_reset(piix4_reset, s); |
|
| 552 |
|
|
| 530 | 553 |
return s->smbus; |
| 531 | 554 |
} |
| 532 | 555 |
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