Revision 0bc472a9
| ID | 0bc472a9d6b80567c212023c5eae413f4dfb53ad |
hw/nand.c: correct the sense of the BUSY/READY status bit
The BIT6 of Status Register(SR):
SR6 behaves the same as R/B# pin
SR6 = 0 indicates the device is busy;
SR6 = 1 means the device is ready
Some NAND flash controller (i.e. ftnandc021) relies on the SR6
to determine if the NAND flash erase/program is success or error timeout.
P.S:
The exmaple NAND flash datasheet could be found at following link:
http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/8FEA549237D2F7674825795800104C26/$File/MX30LF1G08AA,%203V,%201Gb,%20v1.1.pdf
Signed-off-by: Kuo-Jung Su <dantesu@gmail.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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