Archipelago » qemu

    }

    QLIST_INIT (&s->card_head);

}

void AUD_register_card (const char *name, QEMUSoundCard *card)

    QSIMPLEQ_INIT(&block_mig_state.bmds_list);

    QSIMPLEQ_INIT(&block_mig_state.blk_list);

}

    cpu_list_unlock();

#endif

#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)

                    cpu_save, cpu_load, env);

#endif

}

    d = adb_register_device(bus, ADB_KEYBOARD, adb_kbd_request,

                            adb_kbd_reset, s);

    qemu_add_kbd_event_handler(adb_kbd_put_keycode, d);

                    adb_kbd_load, s);

}

    d = adb_register_device(bus, ADB_MOUSE, adb_mouse_request,

                            adb_mouse_reset, s);

    qemu_add_mouse_event_handler(adb_mouse_event, d, 0, "QEMU ADB Mouse");

                    adb_mouse_load, s);

}

    ads7846_int_update(s);

    return 0;

}

    s->iomemtype = cpu_register_io_memory(gic_dist_readfn,

                                          gic_dist_writefn, s);

    gic_reset(s);

}

    bh = qemu_bh_new(arm_timer_tick, s);

    s->timer = ptimer_init(bh);

    return s;

}

    iomemtype = cpu_register_io_memory(sp804_readfn,

                                       sp804_writefn, s);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    return 0;

}

    gic_init(&s->gic);

    cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);

    s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);

    return 0;

}

    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,

                                     s->vga.screen_dump, s->vga.text_update,

                                     &s->vga);

    rom_add_vga(VGABIOS_CIRRUS_FILENAME);

    /* XXX ISA-LFB support */

}

    s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);

    *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);

    qemu_register_reset(cuda_reset, s);

}

              high_page_enable ? 0x480 : -1, cpu_request_exit);

    dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,

              high_page_enable ? 0x488 : -1, cpu_request_exit);

    dma_bh = qemu_bh_new(DMA_run_bh, NULL);

}

    EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);

    cpu_unregister_io_memory(s->mmio_index);

    eeprom93xx_free(s->eeprom);

    qemu_del_vlan_client(&s->nic->nc);

    return 0;

    s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));

    memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));

    s->vmstate->name = s->nic->nc.model;

    return 0;

}

    /* Output DO is tristate, read results in 1. */

    eeprom->eedo = 1;

    logout("eeprom = 0x%p, nwords = %u\n", eeprom, nwords);

    return eeprom;

}

{

    /* Destroy EEPROM. */

    logout("eeprom = 0x%p\n", eeprom);

    qemu_free(eeprom);

}

    s->irq = irq;

    qemu_register_reset(g364fb_reset, s);

    g364fb_reset(s);

    s->ds = graphic_console_init(g364fb_update_display,

    sysbus_init_mmio(dev, 0x1000, pci_mem_config);

    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    qemu_register_reset(pci_grackle_reset, &s->host_state);

    return 0;

}

    gt64120_reset(s);

    return s->pci->bus;

}

    s->irqs = irqs[0];

    *pmem_index = cpu_register_io_memory(pic_read, pic_write, s);

                    heathrow_pic_load, s);

    qemu_register_reset(heathrow_pic_reset, s);

    return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);

                                 void *opaque);

typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);

                    int instance_id,

                    int version_id,

                    SaveStateHandler *save_state,

                    LoadStateHandler *load_state,

                    void *opaque);

                         int instance_id,

                         int version_id,

                         SaveSetParamsHandler *set_params,

                         LoadStateHandler *load_state,

                         void *opaque);

typedef void QEMUResetHandler(void *opaque);

                              void *opaque, int version_id);

extern void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,

                               void *opaque);

                                          const VMStateDescription *vmsd,

                                          void *base, int alias_id,

                                          int required_for_version);

#endif

    i2c_bus *bus;

    bus = FROM_QBUS(i2c_bus, qbus_create(&i2c_bus_info, parent, name));

    return bus;

}

    s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);

    s->irq = irq;

    qemu_register_reset(pit_reset, pit);

    register_ioport_write(base, 4, 1, pit_ioport_write, pit);

    register_ioport_read(base, 3, 1, pit_ioport_read, pit);

        register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);

        register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);

    }

    qemu_register_reset(pic_reset, s);

}

    ide_init2(&d->bus[0], irq[0]);

    ide_init2(&d->bus[1], irq[1]);

    qemu_register_reset(cmd646_reset, d);

    return 0;

}

    ide_init_ioport(&s->bus, s->iobase, s->iobase2);

    isa_init_irq(dev, &s->irq, s->isairq);

    ide_init2(&s->bus, s->irq);

    return 0;

};

    pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,

                                             pmac_ide_write, d);

    qemu_register_reset(pmac_ide_reset, d);

    return pmac_ide_memory;

    md->bus.ifs[0].mdata_size = METADATA_SIZE;

    md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);

    return &md->card;

}

    mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);

    cpu_register_physical_memory(membase, 16 << shift, mem1);

    cpu_register_physical_memory(membase2, 2 << shift, mem2);

    qemu_register_reset(mmio_ide_reset, s);

}

    pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);

    ide_bus_new(&d->bus[0], &d->dev.qdev);

    ide_bus_new(&d->bus[1], &d->dev.qdev);

    }

    qemu_get_timedate(&s->alarm, 0);

}

static int m48t59_init_isa1(ISADevice *dev)

    s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);

    *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);

    qemu_register_reset(dbdma_reset, s);

    dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);

    s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);

    *mem_index = s->mem_index;

    qemu_register_reset(macio_nvram_reset, s);

    return s;

    s->input[7] = 0x80;

    s->com = 0;

    return 0;

}

        exit(1);

    }

    qemu_register_reset(main_cpu_reset, env);

    /* fulong 2e has 256M ram. */

{

    MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;

    isa_unassign_ioport(s->io_base, 36);

    }

    mipsnet_reset(s);

}

	iomemtype = cpu_register_io_memory(mst_fpga_readfn,

		mst_fpga_writefn, s);

	cpu_register_physical_memory(base, 0x00100000, iomemtype);

	return qi;

}

       is used.  */

    s->ioaddr = s->io;

    return s;

}

    opp->irq_out = irq_out;

    opp->need_swap = 1;

    qemu_register_reset(openpic_reset, opp);

    opp->irq_raise = openpic_irq_raise;

    mpp->irq_raise = mpic_irq_raise;

    mpp->reset = mpic_reset;

    qemu_register_reset(mpic_reset, mpp);

    return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);

    QLIST_INIT(&bus->child);

    pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */

    qemu_register_reset(pci_bus_reset, bus);

}

    s->irq_mouse = mouse_irq;

    s->mask = mask;

    s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);

    cpu_register_physical_memory(base, size, s_io_memory);

    uint8_t *pci_conf;

    isa_bus_new(&d->qdev);

    pci_conf = d->config;

    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);

        qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,

                              pl011_event, s);

    }

    return 0;

}

    sysbus_init_irq(dev, &s->irq);

    s->ssi = ssi_create_bus(&dev->qdev, "ssi");

    pl022_reset(s);

    return 0;

}

    qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);

    qdev_init_gpio_out(&dev->qdev, s->out, 8);

    pl061_reset(s);

    return 0;

}

    qemu_register_reset(ppc4xx_pci_reset, controller);

    /* XXX load/save code not tested. */

    return controller->pci_state.bus;

                                   PCIE500_REG_SIZE, index);

    /* XXX load/save code not tested. */

    return controller->pci_state.bus;

    s->common.update_irq = update_irq;

    s->common.update_arg = update_arg;

    s->scancode_set = 2;

    qemu_add_kbd_event_handler(ps2_put_keycode, s);

    qemu_register_reset(ps2_kbd_reset, s);

    return s;

    s->common.update_irq = update_irq;

    s->common.update_arg = update_arg;

    qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse");

    qemu_register_reset(ps2_mouse_reset, s);

    return s;

    iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,

                                       pxa2xx_ssp_writefn, s);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

                    pxa2xx_ssp_save, pxa2xx_ssp_load, s);

    s->bus = ssi_create_bus(&dev->qdev, "ssi");

    cpu_register_physical_memory(base & ~region_size,

                    region_size + 1, iomemtype);

    return s;

}

                    pxa2xx_i2s_writefn, s);

    cpu_register_physical_memory(base, 0x100000, iomemtype);

                    pxa2xx_i2s_save, pxa2xx_i2s_load, s);

    return s;

        qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,

                        pxa2xx_fir_rx, pxa2xx_fir_event, s);

    return s;

}

    iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,

                    pxa2xx_cm_writefn, s);

    cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);

    cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);

    iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,

                    pxa2xx_mm_writefn, s);

    cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);

    s->pm_base = 0x40f00000;

    iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,

                    pxa2xx_pm_writefn, s);

    cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);

    for (i = 0; pxa27x_ssp[i].io_base; i ++);

    s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);

                    pxa2xx_rtc_writefn, s);

    cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);

    pxa2xx_rtc_init(s);

    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);

    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);

    iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,

                    pxa2xx_cm_writefn, s);

    cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);

    cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);

    iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,

                    pxa2xx_mm_writefn, s);

    cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);

    s->pm_base = 0x40f00000;

    iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,

                    pxa2xx_pm_writefn, s);

    cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);

    for (i = 0; pxa255_ssp[i].io_base; i ++);

    s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);

                    pxa2xx_rtc_writefn, s);

    cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);

    pxa2xx_rtc_init(s);

    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);

    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);

                    pxa2xx_dma_writefn, s);

    cpu_register_physical_memory(base, 0x00010000, iomemtype);

    return s;

}

                    pxa2xx_gpio_writefn, s);

    cpu_register_physical_memory(base, 0x00001000, iomemtype);

                    pxa2xx_gpio_save, pxa2xx_gpio_load, s);

    return s;

                    pxa2xx_keypad_writefn, s);

    cpu_register_physical_memory(base, 0x00100000, iomemtype);

                    pxa2xx_keypad_save, pxa2xx_keypad_load, s);

    return s;

        exit(1);

    }

                    pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);

    return s;

    /* Instantiate the actual storage */

    s->card = sd_init(bd, 0);

                    pxa2xx_mmci_save, pxa2xx_mmci_load, s);

    return s;

    /* Enable IC coprocessor access.  */

    cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);

    return qi;

}

                    pxa2xx_timer_writefn, s);

    cpu_register_physical_memory(base, 0x00001000, iomemtype);

                    pxa2xx_timer_save, pxa2xx_timer_load, s);

    return s;

    }

    qemu_register_reset(qdev_reset, dev);

    if (dev->info->vmsd) {

                                       dev->instance_id_alias,

                                       dev->alias_required_for_version);

    }

            qbus_free(bus);

        }

        if (dev->info->vmsd)

        if (dev->info->exit)

            dev->info->exit(dev);

        if (dev->opts)

    s->jazz_bus_irq = jazz_bus;

    qemu_register_reset(rc4030_reset, s);

    rc4030_reset(s);

    s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);

    s->chr = chr;

    serial_init_core(s);

    register_ioport_write(base, 8, 1, serial_ioport_write, s);

    register_ioport_read(base, 8, 1, serial_ioport_read, s);

    s->chr = chr;

    serial_init_core(s);

    if (ioregister) {

        if (be) {

                    sl_writefn, s);

    cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);

}

/* Spitz Keyboard */

    spitz_keyboard_pre_map(s);

    qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);

                    spitz_keyboard_save, spitz_keyboard_load, s);

}

    s->bl_power = 0;

    s->bl_intensity = 0x20;

                    spitz_lcdtg_save, spitz_lcdtg_load, s);

    return 0;

}

    s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");

    s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");

    return 0;

}

    qdev_init_gpio_in(&dev->qdev, ssd0323_cd, 1);

    return 0;

}

    s->mode = SSI_SD_CMD;

    bs = qdev_init_bdrv(&dev->qdev, IF_SD);

    s->sd = sd_init(bs, 1);

    return 0;

}

    s->opaque[0] = s->opaque[1] = s;

    s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]);

    s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]);

    return 0;

}

                                       ssys_writefn, s);

    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    ssys_reset(s);

    return 0;

}

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    /* ??? For now we only implement the master interface.  */

    stellaris_i2c_reset(s);

                    stellaris_i2c_save, stellaris_i2c_load, s);

    return 0;

}

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    stellaris_adc_reset(s);

    qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);

                    stellaris_adc_save, stellaris_adc_load, s);

    return 0;

}

    s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");

    qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);

                    stellaris_ssi_bus_save, stellaris_ssi_bus_load, s);

    return 0;

}

{

    stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;

    cpu_unregister_io_memory(s->mmio_index);

    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);

    stellaris_enet_reset(s);

                    stellaris_enet_save, stellaris_enet_load, s);

    return 0;

}

    }

    s->num_buttons = n;

    qemu_add_kbd_event_handler(stellaris_gamepad_put_key, s);

                    stellaris_gamepad_save, stellaris_gamepad_load, s);

}

    if (!s->rows)

        s->rows = ds_get_height(s->ds);

                    syborg_fb_save, syborg_fb_load, s);

    return 0;

}

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    s->flags = qemu_mallocz(s->num_irqs * sizeof(syborg_int_flags));

    return 0;

}

    qemu_add_kbd_event_handler(syborg_keyboard_event, s);

                    syborg_keyboard_save, syborg_keyboard_load, s);

    return 0;

}

    qemu_add_mouse_event_handler(syborg_pointer_event, s, s->absolute,

                                 "Syborg Pointer");

                    syborg_pointer_save, syborg_pointer_load, s);

    return 0;

}

    qemu_get_timedate(&tm, 0);

    s->offset = (uint64_t)mktime(&tm) * 1000000000;

    return 0;

}

    }

    s->read_fifo = qemu_mallocz(s->fifo_size * sizeof(s->read_fifo[0]));

                    syborg_serial_save, syborg_serial_load, s);

    return 0;

}

    bh = qemu_bh_new(syborg_timer_tick, s);

    s->timer = ptimer_init(bh);

    ptimer_set_freq(s->timer, s->freq);

                    syborg_timer_save, syborg_timer_load, s);

    return 0;

}

                    "QEMU TSC2005-driven Touchscreen");

    qemu_register_reset((void *) tsc2005_reset, s);

    return s;

}

    AUD_register_card(s->name, &s->card);

    qemu_register_reset((void *) tsc210x_reset, s);

                    tsc210x_save, tsc210x_load, s);

    return &s->chip;

    AUD_register_card(s->name, &s->card);

    qemu_register_reset((void *) tsc210x_reset, s);

    return &s->chip;

}

    sysbus_init_mmio(dev, 0x1000, pci_mem_config);

    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;

}

    sysbus_init_mmio(dev, 0x1000, pci_mem_config);

    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;

    s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);

    vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);

    cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);

    s->vga.bank_offset = 0;

    vga_common_init(s, VGA_RAM_SIZE);

    vga_init(s);

    s->ds = graphic_console_init(s->update, s->invalidate,

                                 s->screen_dump, s->text_update, s);

    reset_stats(s);

    qemu_add_balloon_handler(virtio_balloon_to_target, s);

    return &s->vdev;

}

    s->vq = virtio_add_queue(&s->vdev, 128, virtio_blk_handle_output);

    qemu_add_vm_change_state_handler(virtio_blk_dma_restart_cb, s);

                    virtio_blk_save, virtio_blk_load, s);

    bdrv_set_removable(s->bs, 0);

    n->vlans = qemu_mallocz(MAX_VLAN >> 3);

                    virtio_net_save, virtio_net_load, n);

    n->vmstate = qemu_add_vm_change_state_handler(virtio_net_vmstate_change, n);

    qemu_purge_queued_packets(&n->nic->nc);

    qemu_free(n->mac_table.macs);

    qemu_free(n->vlans);

     * Register for the savevm section with the virtio-console name

     * to preserve backward compat

     */

                    virtio_serial_load, vser);

    return vdev;

    vmport_register(VMMOUSE_STATUS, vmmouse_ioport_read, s);

    vmport_register(VMMOUSE_COMMAND, vmmouse_ioport_read, s);

    vmport_register(VMMOUSE_DATA, vmmouse_ioport_read, s);

    return s;

}

    vga_common_init(&s->vga, vga_ram_size);

    vga_init(&s->vga);

    vga_init_vbe(&s->vga);

    iomemtype = cpu_register_io_memory(scoop_readfn,

                    scoop_writefn, s);

    cpu_register_physical_memory(target_base, 0x1000, iomemtype);

    return s;

}

void configure_icount(const char *option)

{

    if (!option)

        return;

   of the system, so instance_id should be removed/replaced.

   Meanwhile pass -1 as instance_id if you do not already have a clearly

   distinguishing id for all instances of your device class. */

                         int instance_id,

                         int version_id,

                         SaveSetParamsHandler *set_params,

    return 0;

}

                    int instance_id,

                    int version_id,

                    SaveStateHandler *save_state,

                    LoadStateHandler *load_state,

                    void *opaque)

{

                                NULL, NULL, save_state, load_state, opaque);

}

{

    SaveStateEntry *se, *new_se;

    }

}

                                   const VMStateDescription *vmsd,

                                   void *opaque, int alias_id,

                                   int required_for_version)

    return 0;

}

{

}

{

    SaveStateEntry *se, *new_se;

    slirp->opaque = opaque;

    QTAILQ_INSERT_TAIL(&slirp_instances, slirp, entry);

{

    QTAILQ_REMOVE(&slirp_instances, slirp, entry);

    qemu_free(slirp->tftp_prefix);

    qemu_free(slirp->bootp_filename);