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1 | 827df9f3 | balrog | /*
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2 | 827df9f3 | balrog | * TI OMAP processors emulation.
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3 | 827df9f3 | balrog | *
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4 | 827df9f3 | balrog | * Copyright (C) 2007-2008 Nokia Corporation
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5 | 827df9f3 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 827df9f3 | balrog | *
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7 | 827df9f3 | balrog | * This program is free software; you can redistribute it and/or
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8 | 827df9f3 | balrog | * modify it under the terms of the GNU General Public License as
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9 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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11 | 827df9f3 | balrog | *
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12 | 827df9f3 | balrog | * This program is distributed in the hope that it will be useful,
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13 | 827df9f3 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 827df9f3 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 827df9f3 | balrog | * GNU General Public License for more details.
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16 | 827df9f3 | balrog | *
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17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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18 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 827df9f3 | balrog | */
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20 | 666daa68 | Markus Armbruster | |
21 | 666daa68 | Markus Armbruster | #include "blockdev.h" |
22 | 827df9f3 | balrog | #include "hw.h" |
23 | 827df9f3 | balrog | #include "arm-misc.h" |
24 | 827df9f3 | balrog | #include "omap.h" |
25 | 827df9f3 | balrog | #include "sysemu.h" |
26 | 827df9f3 | balrog | #include "qemu-timer.h" |
27 | 827df9f3 | balrog | #include "qemu-char.h" |
28 | 827df9f3 | balrog | #include "flash.h" |
29 | afbb5194 | balrog | #include "soc_dma.h" |
30 | 99570a40 | balrog | #include "audio/audio.h" |
31 | 827df9f3 | balrog | |
32 | 827df9f3 | balrog | /* Multichannel SPI */
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33 | 827df9f3 | balrog | struct omap_mcspi_s {
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34 | 827df9f3 | balrog | qemu_irq irq; |
35 | 827df9f3 | balrog | int chnum;
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36 | 827df9f3 | balrog | |
37 | 827df9f3 | balrog | uint32_t sysconfig; |
38 | 827df9f3 | balrog | uint32_t systest; |
39 | 827df9f3 | balrog | uint32_t irqst; |
40 | 827df9f3 | balrog | uint32_t irqen; |
41 | 827df9f3 | balrog | uint32_t wken; |
42 | 827df9f3 | balrog | uint32_t control; |
43 | 827df9f3 | balrog | |
44 | 827df9f3 | balrog | struct omap_mcspi_ch_s {
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45 | 827df9f3 | balrog | qemu_irq txdrq; |
46 | 827df9f3 | balrog | qemu_irq rxdrq; |
47 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int); |
48 | 827df9f3 | balrog | void *opaque;
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49 | 827df9f3 | balrog | |
50 | 827df9f3 | balrog | uint32_t tx; |
51 | 827df9f3 | balrog | uint32_t rx; |
52 | 827df9f3 | balrog | |
53 | 827df9f3 | balrog | uint32_t config; |
54 | 827df9f3 | balrog | uint32_t status; |
55 | 827df9f3 | balrog | uint32_t control; |
56 | 827df9f3 | balrog | } ch[4];
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57 | 827df9f3 | balrog | }; |
58 | 827df9f3 | balrog | |
59 | 827df9f3 | balrog | static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s) |
60 | 827df9f3 | balrog | { |
61 | 827df9f3 | balrog | qemu_set_irq(s->irq, s->irqst & s->irqen); |
62 | 827df9f3 | balrog | } |
63 | 827df9f3 | balrog | |
64 | 827df9f3 | balrog | static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch) |
65 | 827df9f3 | balrog | { |
66 | 827df9f3 | balrog | qemu_set_irq(ch->txdrq, |
67 | 827df9f3 | balrog | (ch->control & 1) && /* EN */ |
68 | 827df9f3 | balrog | (ch->config & (1 << 14)) && /* DMAW */ |
69 | 827df9f3 | balrog | (ch->status & (1 << 1)) && /* TXS */ |
70 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 1); /* TRM */ |
71 | 827df9f3 | balrog | qemu_set_irq(ch->rxdrq, |
72 | 827df9f3 | balrog | (ch->control & 1) && /* EN */ |
73 | 827df9f3 | balrog | (ch->config & (1 << 15)) && /* DMAW */ |
74 | 827df9f3 | balrog | (ch->status & (1 << 0)) && /* RXS */ |
75 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 2); /* TRM */ |
76 | 827df9f3 | balrog | } |
77 | 827df9f3 | balrog | |
78 | 827df9f3 | balrog | static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum) |
79 | 827df9f3 | balrog | { |
80 | 827df9f3 | balrog | struct omap_mcspi_ch_s *ch = s->ch + chnum;
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81 | 827df9f3 | balrog | |
82 | 827df9f3 | balrog | if (!(ch->control & 1)) /* EN */ |
83 | 827df9f3 | balrog | return;
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84 | 827df9f3 | balrog | if ((ch->status & (1 << 0)) && /* RXS */ |
85 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
86 | 827df9f3 | balrog | !(ch->config & (1 << 19))) /* TURBO */ |
87 | 827df9f3 | balrog | goto intr_update;
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88 | 827df9f3 | balrog | if ((ch->status & (1 << 1)) && /* TXS */ |
89 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 1) /* TRM */ |
90 | 827df9f3 | balrog | goto intr_update;
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91 | 827df9f3 | balrog | |
92 | 827df9f3 | balrog | if (!(s->control & 1) || /* SINGLE */ |
93 | 827df9f3 | balrog | (ch->config & (1 << 20))) { /* FORCE */ |
94 | 827df9f3 | balrog | if (ch->txrx)
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95 | e927bb00 | balrog | ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
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96 | e927bb00 | balrog | 1 + (0x1f & (ch->config >> 7))); |
97 | 827df9f3 | balrog | } |
98 | 827df9f3 | balrog | |
99 | 827df9f3 | balrog | ch->tx = 0;
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100 | 827df9f3 | balrog | ch->status |= 1 << 2; /* EOT */ |
101 | 827df9f3 | balrog | ch->status |= 1 << 1; /* TXS */ |
102 | 827df9f3 | balrog | if (((ch->config >> 12) & 3) != 2) /* TRM */ |
103 | 827df9f3 | balrog | ch->status |= 1 << 0; /* RXS */ |
104 | 827df9f3 | balrog | |
105 | 827df9f3 | balrog | intr_update:
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106 | 827df9f3 | balrog | if ((ch->status & (1 << 0)) && /* RXS */ |
107 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
108 | 827df9f3 | balrog | !(ch->config & (1 << 19))) /* TURBO */ |
109 | 827df9f3 | balrog | s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */ |
110 | 827df9f3 | balrog | if ((ch->status & (1 << 1)) && /* TXS */ |
111 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 1) /* TRM */ |
112 | 827df9f3 | balrog | s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */ |
113 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
114 | 827df9f3 | balrog | omap_mcspi_dmarequest_update(ch); |
115 | 827df9f3 | balrog | } |
116 | 827df9f3 | balrog | |
117 | 827df9f3 | balrog | static void omap_mcspi_reset(struct omap_mcspi_s *s) |
118 | 827df9f3 | balrog | { |
119 | 827df9f3 | balrog | int ch;
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120 | 827df9f3 | balrog | |
121 | 827df9f3 | balrog | s->sysconfig = 0;
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122 | 827df9f3 | balrog | s->systest = 0;
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123 | 827df9f3 | balrog | s->irqst = 0;
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124 | 827df9f3 | balrog | s->irqen = 0;
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125 | 827df9f3 | balrog | s->wken = 0;
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126 | 827df9f3 | balrog | s->control = 4;
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127 | 827df9f3 | balrog | |
128 | 827df9f3 | balrog | for (ch = 0; ch < 4; ch ++) { |
129 | 827df9f3 | balrog | s->ch[ch].config = 0x060000;
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130 | 827df9f3 | balrog | s->ch[ch].status = 2; /* TXS */ |
131 | 827df9f3 | balrog | s->ch[ch].control = 0;
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132 | 827df9f3 | balrog | |
133 | 827df9f3 | balrog | omap_mcspi_dmarequest_update(s->ch + ch); |
134 | 827df9f3 | balrog | } |
135 | 827df9f3 | balrog | |
136 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
137 | 827df9f3 | balrog | } |
138 | 827df9f3 | balrog | |
139 | c227f099 | Anthony Liguori | static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) |
140 | 827df9f3 | balrog | { |
141 | 827df9f3 | balrog | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
142 | 827df9f3 | balrog | int ch = 0; |
143 | 827df9f3 | balrog | uint32_t ret; |
144 | 827df9f3 | balrog | |
145 | 8da3ff18 | pbrook | switch (addr) {
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146 | 827df9f3 | balrog | case 0x00: /* MCSPI_REVISION */ |
147 | 827df9f3 | balrog | return 0x91; |
148 | 827df9f3 | balrog | |
149 | 827df9f3 | balrog | case 0x10: /* MCSPI_SYSCONFIG */ |
150 | 827df9f3 | balrog | return s->sysconfig;
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151 | 827df9f3 | balrog | |
152 | 827df9f3 | balrog | case 0x14: /* MCSPI_SYSSTATUS */ |
153 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
154 | 827df9f3 | balrog | |
155 | 827df9f3 | balrog | case 0x18: /* MCSPI_IRQSTATUS */ |
156 | 827df9f3 | balrog | return s->irqst;
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157 | 827df9f3 | balrog | |
158 | 827df9f3 | balrog | case 0x1c: /* MCSPI_IRQENABLE */ |
159 | 827df9f3 | balrog | return s->irqen;
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160 | 827df9f3 | balrog | |
161 | 827df9f3 | balrog | case 0x20: /* MCSPI_WAKEUPENABLE */ |
162 | 827df9f3 | balrog | return s->wken;
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163 | 827df9f3 | balrog | |
164 | 827df9f3 | balrog | case 0x24: /* MCSPI_SYST */ |
165 | 827df9f3 | balrog | return s->systest;
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166 | 827df9f3 | balrog | |
167 | 827df9f3 | balrog | case 0x28: /* MCSPI_MODULCTRL */ |
168 | 827df9f3 | balrog | return s->control;
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169 | 827df9f3 | balrog | |
170 | 827df9f3 | balrog | case 0x68: ch ++; |
171 | 827df9f3 | balrog | case 0x54: ch ++; |
172 | 827df9f3 | balrog | case 0x40: ch ++; |
173 | 827df9f3 | balrog | case 0x2c: /* MCSPI_CHCONF */ |
174 | 827df9f3 | balrog | return s->ch[ch].config;
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175 | 827df9f3 | balrog | |
176 | 827df9f3 | balrog | case 0x6c: ch ++; |
177 | 827df9f3 | balrog | case 0x58: ch ++; |
178 | 827df9f3 | balrog | case 0x44: ch ++; |
179 | 827df9f3 | balrog | case 0x30: /* MCSPI_CHSTAT */ |
180 | 827df9f3 | balrog | return s->ch[ch].status;
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181 | 827df9f3 | balrog | |
182 | 827df9f3 | balrog | case 0x70: ch ++; |
183 | 827df9f3 | balrog | case 0x5c: ch ++; |
184 | 827df9f3 | balrog | case 0x48: ch ++; |
185 | 827df9f3 | balrog | case 0x34: /* MCSPI_CHCTRL */ |
186 | 827df9f3 | balrog | return s->ch[ch].control;
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187 | 827df9f3 | balrog | |
188 | 827df9f3 | balrog | case 0x74: ch ++; |
189 | 827df9f3 | balrog | case 0x60: ch ++; |
190 | 827df9f3 | balrog | case 0x4c: ch ++; |
191 | 827df9f3 | balrog | case 0x38: /* MCSPI_TX */ |
192 | 827df9f3 | balrog | return s->ch[ch].tx;
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193 | 827df9f3 | balrog | |
194 | 827df9f3 | balrog | case 0x78: ch ++; |
195 | 827df9f3 | balrog | case 0x64: ch ++; |
196 | 827df9f3 | balrog | case 0x50: ch ++; |
197 | 827df9f3 | balrog | case 0x3c: /* MCSPI_RX */ |
198 | 827df9f3 | balrog | s->ch[ch].status &= ~(1 << 0); /* RXS */ |
199 | 827df9f3 | balrog | ret = s->ch[ch].rx; |
200 | 827df9f3 | balrog | omap_mcspi_transfer_run(s, ch); |
201 | 827df9f3 | balrog | return ret;
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202 | 827df9f3 | balrog | } |
203 | 827df9f3 | balrog | |
204 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
205 | 827df9f3 | balrog | return 0; |
206 | 827df9f3 | balrog | } |
207 | 827df9f3 | balrog | |
208 | c227f099 | Anthony Liguori | static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, |
209 | 827df9f3 | balrog | uint32_t value) |
210 | 827df9f3 | balrog | { |
211 | 827df9f3 | balrog | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
212 | 827df9f3 | balrog | int ch = 0; |
213 | 827df9f3 | balrog | |
214 | 8da3ff18 | pbrook | switch (addr) {
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215 | 827df9f3 | balrog | case 0x00: /* MCSPI_REVISION */ |
216 | 827df9f3 | balrog | case 0x14: /* MCSPI_SYSSTATUS */ |
217 | 827df9f3 | balrog | case 0x30: /* MCSPI_CHSTAT0 */ |
218 | 827df9f3 | balrog | case 0x3c: /* MCSPI_RX0 */ |
219 | 827df9f3 | balrog | case 0x44: /* MCSPI_CHSTAT1 */ |
220 | 827df9f3 | balrog | case 0x50: /* MCSPI_RX1 */ |
221 | 827df9f3 | balrog | case 0x58: /* MCSPI_CHSTAT2 */ |
222 | 827df9f3 | balrog | case 0x64: /* MCSPI_RX2 */ |
223 | 827df9f3 | balrog | case 0x6c: /* MCSPI_CHSTAT3 */ |
224 | 827df9f3 | balrog | case 0x78: /* MCSPI_RX3 */ |
225 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
226 | 827df9f3 | balrog | return;
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227 | 827df9f3 | balrog | |
228 | 827df9f3 | balrog | case 0x10: /* MCSPI_SYSCONFIG */ |
229 | 827df9f3 | balrog | if (value & (1 << 1)) /* SOFTRESET */ |
230 | 827df9f3 | balrog | omap_mcspi_reset(s); |
231 | 827df9f3 | balrog | s->sysconfig = value & 0x31d;
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232 | 827df9f3 | balrog | break;
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233 | 827df9f3 | balrog | |
234 | 827df9f3 | balrog | case 0x18: /* MCSPI_IRQSTATUS */ |
235 | 827df9f3 | balrog | if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) { |
236 | 827df9f3 | balrog | s->irqst &= ~value; |
237 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
238 | 827df9f3 | balrog | } |
239 | 827df9f3 | balrog | break;
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240 | 827df9f3 | balrog | |
241 | 827df9f3 | balrog | case 0x1c: /* MCSPI_IRQENABLE */ |
242 | 827df9f3 | balrog | s->irqen = value & 0x1777f;
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243 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
244 | 827df9f3 | balrog | break;
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245 | 827df9f3 | balrog | |
246 | 827df9f3 | balrog | case 0x20: /* MCSPI_WAKEUPENABLE */ |
247 | 827df9f3 | balrog | s->wken = value & 1;
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248 | 827df9f3 | balrog | break;
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249 | 827df9f3 | balrog | |
250 | 827df9f3 | balrog | case 0x24: /* MCSPI_SYST */ |
251 | 827df9f3 | balrog | if (s->control & (1 << 3)) /* SYSTEM_TEST */ |
252 | 827df9f3 | balrog | if (value & (1 << 11)) { /* SSB */ |
253 | 827df9f3 | balrog | s->irqst |= 0x1777f;
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254 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
255 | 827df9f3 | balrog | } |
256 | 827df9f3 | balrog | s->systest = value & 0xfff;
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257 | 827df9f3 | balrog | break;
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258 | 827df9f3 | balrog | |
259 | 827df9f3 | balrog | case 0x28: /* MCSPI_MODULCTRL */ |
260 | 827df9f3 | balrog | if (value & (1 << 3)) /* SYSTEM_TEST */ |
261 | 827df9f3 | balrog | if (s->systest & (1 << 11)) { /* SSB */ |
262 | 827df9f3 | balrog | s->irqst |= 0x1777f;
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263 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
264 | 827df9f3 | balrog | } |
265 | 827df9f3 | balrog | s->control = value & 0xf;
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266 | 827df9f3 | balrog | break;
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267 | 827df9f3 | balrog | |
268 | 827df9f3 | balrog | case 0x68: ch ++; |
269 | 827df9f3 | balrog | case 0x54: ch ++; |
270 | 827df9f3 | balrog | case 0x40: ch ++; |
271 | 827df9f3 | balrog | case 0x2c: /* MCSPI_CHCONF */ |
272 | 827df9f3 | balrog | if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ |
273 | 827df9f3 | balrog | omap_mcspi_dmarequest_update(s->ch + ch); |
274 | 827df9f3 | balrog | if (((value >> 12) & 3) == 3) /* TRM */ |
275 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
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276 | 827df9f3 | balrog | if (((value >> 7) & 0x1f) < 3) /* WL */ |
277 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid WL value (%i)\n",
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278 | 827df9f3 | balrog | __FUNCTION__, (value >> 7) & 0x1f); |
279 | 827df9f3 | balrog | s->ch[ch].config = value & 0x7fffff;
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280 | 827df9f3 | balrog | break;
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281 | 827df9f3 | balrog | |
282 | 827df9f3 | balrog | case 0x70: ch ++; |
283 | 827df9f3 | balrog | case 0x5c: ch ++; |
284 | 827df9f3 | balrog | case 0x48: ch ++; |
285 | 827df9f3 | balrog | case 0x34: /* MCSPI_CHCTRL */ |
286 | 827df9f3 | balrog | if (value & ~s->ch[ch].control & 1) { /* EN */ |
287 | 827df9f3 | balrog | s->ch[ch].control |= 1;
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288 | 827df9f3 | balrog | omap_mcspi_transfer_run(s, ch); |
289 | 827df9f3 | balrog | } else
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290 | 827df9f3 | balrog | s->ch[ch].control = value & 1;
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291 | 827df9f3 | balrog | break;
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292 | 827df9f3 | balrog | |
293 | 827df9f3 | balrog | case 0x74: ch ++; |
294 | 827df9f3 | balrog | case 0x60: ch ++; |
295 | 827df9f3 | balrog | case 0x4c: ch ++; |
296 | 827df9f3 | balrog | case 0x38: /* MCSPI_TX */ |
297 | 827df9f3 | balrog | s->ch[ch].tx = value; |
298 | 827df9f3 | balrog | s->ch[ch].status &= ~(1 << 1); /* TXS */ |
299 | 827df9f3 | balrog | omap_mcspi_transfer_run(s, ch); |
300 | 827df9f3 | balrog | break;
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301 | 827df9f3 | balrog | |
302 | 827df9f3 | balrog | default:
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303 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
304 | 827df9f3 | balrog | return;
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305 | 827df9f3 | balrog | } |
306 | 827df9f3 | balrog | } |
307 | 827df9f3 | balrog | |
308 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mcspi_readfn[] = { |
309 | 827df9f3 | balrog | omap_badwidth_read32, |
310 | 827df9f3 | balrog | omap_badwidth_read32, |
311 | 827df9f3 | balrog | omap_mcspi_read, |
312 | 827df9f3 | balrog | }; |
313 | 827df9f3 | balrog | |
314 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = { |
315 | 827df9f3 | balrog | omap_badwidth_write32, |
316 | 827df9f3 | balrog | omap_badwidth_write32, |
317 | 827df9f3 | balrog | omap_mcspi_write, |
318 | 827df9f3 | balrog | }; |
319 | 827df9f3 | balrog | |
320 | 827df9f3 | balrog | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
321 | 827df9f3 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
322 | 827df9f3 | balrog | { |
323 | 827df9f3 | balrog | int iomemtype;
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324 | 827df9f3 | balrog | struct omap_mcspi_s *s = (struct omap_mcspi_s *) |
325 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_mcspi_s)); |
326 | 827df9f3 | balrog | struct omap_mcspi_ch_s *ch = s->ch;
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327 | 827df9f3 | balrog | |
328 | 827df9f3 | balrog | s->irq = irq; |
329 | 827df9f3 | balrog | s->chnum = chnum; |
330 | 827df9f3 | balrog | while (chnum --) {
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331 | 827df9f3 | balrog | ch->txdrq = *drq ++; |
332 | 827df9f3 | balrog | ch->rxdrq = *drq ++; |
333 | 827df9f3 | balrog | ch ++; |
334 | 827df9f3 | balrog | } |
335 | 827df9f3 | balrog | omap_mcspi_reset(s); |
336 | 827df9f3 | balrog | |
337 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_mcspi_readfn, |
338 | 827df9f3 | balrog | omap_mcspi_writefn, s); |
339 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
340 | 827df9f3 | balrog | |
341 | 827df9f3 | balrog | return s;
|
342 | 827df9f3 | balrog | } |
343 | 827df9f3 | balrog | |
344 | 827df9f3 | balrog | void omap_mcspi_attach(struct omap_mcspi_s *s, |
345 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
346 | 827df9f3 | balrog | int chipselect)
|
347 | 827df9f3 | balrog | { |
348 | 827df9f3 | balrog | if (chipselect < 0 || chipselect >= s->chnum) |
349 | 2ac71179 | Paul Brook | hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
|
350 | 827df9f3 | balrog | |
351 | 827df9f3 | balrog | s->ch[chipselect].txrx = txrx; |
352 | 827df9f3 | balrog | s->ch[chipselect].opaque = opaque; |
353 | 827df9f3 | balrog | } |
354 | 827df9f3 | balrog | |
355 | 99570a40 | balrog | /* Enhanced Audio Controller (CODEC only) */
|
356 | 99570a40 | balrog | struct omap_eac_s {
|
357 | 99570a40 | balrog | qemu_irq irq; |
358 | 99570a40 | balrog | |
359 | 99570a40 | balrog | uint16_t sysconfig; |
360 | 99570a40 | balrog | uint8_t config[4];
|
361 | 99570a40 | balrog | uint8_t control; |
362 | 99570a40 | balrog | uint8_t address; |
363 | 99570a40 | balrog | uint16_t data; |
364 | 99570a40 | balrog | uint8_t vtol; |
365 | 99570a40 | balrog | uint8_t vtsl; |
366 | 99570a40 | balrog | uint16_t mixer; |
367 | 99570a40 | balrog | uint16_t gain[4];
|
368 | 99570a40 | balrog | uint8_t att; |
369 | 99570a40 | balrog | uint16_t max[7];
|
370 | 99570a40 | balrog | |
371 | 99570a40 | balrog | struct {
|
372 | 99570a40 | balrog | qemu_irq txdrq; |
373 | 99570a40 | balrog | qemu_irq rxdrq; |
374 | 99570a40 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int); |
375 | 99570a40 | balrog | void *opaque;
|
376 | 99570a40 | balrog | |
377 | 99570a40 | balrog | #define EAC_BUF_LEN 1024 |
378 | 99570a40 | balrog | uint32_t rxbuf[EAC_BUF_LEN]; |
379 | ab17b46d | balrog | int rxoff;
|
380 | 99570a40 | balrog | int rxlen;
|
381 | 99570a40 | balrog | int rxavail;
|
382 | 99570a40 | balrog | uint32_t txbuf[EAC_BUF_LEN]; |
383 | 99570a40 | balrog | int txlen;
|
384 | 99570a40 | balrog | int txavail;
|
385 | 99570a40 | balrog | |
386 | 99570a40 | balrog | int enable;
|
387 | 99570a40 | balrog | int rate;
|
388 | 99570a40 | balrog | |
389 | 99570a40 | balrog | uint16_t config[4];
|
390 | 99570a40 | balrog | |
391 | 99570a40 | balrog | /* These need to be moved to the actual codec */
|
392 | 99570a40 | balrog | QEMUSoundCard card; |
393 | 99570a40 | balrog | SWVoiceIn *in_voice; |
394 | 99570a40 | balrog | SWVoiceOut *out_voice; |
395 | 99570a40 | balrog | int hw_enable;
|
396 | 99570a40 | balrog | } codec; |
397 | 99570a40 | balrog | |
398 | 99570a40 | balrog | struct {
|
399 | 99570a40 | balrog | uint8_t control; |
400 | 99570a40 | balrog | uint16_t config; |
401 | 99570a40 | balrog | } modem, bt; |
402 | 99570a40 | balrog | }; |
403 | 99570a40 | balrog | |
404 | 99570a40 | balrog | static inline void omap_eac_interrupt_update(struct omap_eac_s *s) |
405 | 99570a40 | balrog | { |
406 | 99570a40 | balrog | qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ |
407 | 99570a40 | balrog | } |
408 | 99570a40 | balrog | |
409 | 99570a40 | balrog | static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) |
410 | 99570a40 | balrog | { |
411 | ab17b46d | balrog | qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) && |
412 | 99570a40 | balrog | ((s->codec.config[1] >> 12) & 1)); /* DMAREN */ |
413 | 99570a40 | balrog | } |
414 | 99570a40 | balrog | |
415 | 99570a40 | balrog | static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) |
416 | 99570a40 | balrog | { |
417 | 99570a40 | balrog | qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && |
418 | 99570a40 | balrog | ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ |
419 | 99570a40 | balrog | } |
420 | 99570a40 | balrog | |
421 | 99570a40 | balrog | static inline void omap_eac_in_refill(struct omap_eac_s *s) |
422 | 99570a40 | balrog | { |
423 | ab17b46d | balrog | int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2; |
424 | ab17b46d | balrog | int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2; |
425 | ab17b46d | balrog | int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start); |
426 | ab17b46d | balrog | int recv = 1; |
427 | ab17b46d | balrog | uint8_t *buf = (uint8_t *) s->codec.rxbuf + start; |
428 | ab17b46d | balrog | |
429 | ab17b46d | balrog | left -= leftwrap; |
430 | ab17b46d | balrog | start = 0;
|
431 | ab17b46d | balrog | while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
|
432 | ab17b46d | balrog | leftwrap)) > 0) { /* Be defensive */ |
433 | ab17b46d | balrog | start += recv; |
434 | ab17b46d | balrog | leftwrap -= recv; |
435 | ab17b46d | balrog | } |
436 | ab17b46d | balrog | if (recv <= 0) |
437 | ab17b46d | balrog | s->codec.rxavail = 0;
|
438 | ab17b46d | balrog | else
|
439 | ab17b46d | balrog | s->codec.rxavail -= start >> 2;
|
440 | ab17b46d | balrog | s->codec.rxlen += start >> 2;
|
441 | ab17b46d | balrog | |
442 | ab17b46d | balrog | if (recv > 0 && left > 0) { |
443 | ab17b46d | balrog | start = 0;
|
444 | ab17b46d | balrog | while (left && (recv = AUD_read(s->codec.in_voice,
|
445 | ab17b46d | balrog | (uint8_t *) s->codec.rxbuf + start, |
446 | ab17b46d | balrog | left)) > 0) { /* Be defensive */ |
447 | ab17b46d | balrog | start += recv; |
448 | ab17b46d | balrog | left -= recv; |
449 | ab17b46d | balrog | } |
450 | ab17b46d | balrog | if (recv <= 0) |
451 | ab17b46d | balrog | s->codec.rxavail = 0;
|
452 | ab17b46d | balrog | else
|
453 | ab17b46d | balrog | s->codec.rxavail -= start >> 2;
|
454 | ab17b46d | balrog | s->codec.rxlen += start >> 2;
|
455 | ab17b46d | balrog | } |
456 | 99570a40 | balrog | } |
457 | 99570a40 | balrog | |
458 | 99570a40 | balrog | static inline void omap_eac_out_empty(struct omap_eac_s *s) |
459 | 99570a40 | balrog | { |
460 | ab17b46d | balrog | int left = s->codec.txlen << 2; |
461 | ab17b46d | balrog | int start = 0; |
462 | ab17b46d | balrog | int sent = 1; |
463 | ab17b46d | balrog | |
464 | ab17b46d | balrog | while (left && (sent = AUD_write(s->codec.out_voice,
|
465 | ab17b46d | balrog | (uint8_t *) s->codec.txbuf + start, |
466 | ab17b46d | balrog | left)) > 0) { /* Be defensive */ |
467 | ab17b46d | balrog | start += sent; |
468 | ab17b46d | balrog | left -= sent; |
469 | ab17b46d | balrog | } |
470 | 99570a40 | balrog | |
471 | ab17b46d | balrog | if (!sent) {
|
472 | ab17b46d | balrog | s->codec.txavail = 0;
|
473 | ab17b46d | balrog | omap_eac_out_dmarequest_update(s); |
474 | ab17b46d | balrog | } |
475 | 99570a40 | balrog | |
476 | ab17b46d | balrog | if (start)
|
477 | ab17b46d | balrog | s->codec.txlen = 0;
|
478 | 99570a40 | balrog | } |
479 | 99570a40 | balrog | |
480 | 99570a40 | balrog | static void omap_eac_in_cb(void *opaque, int avail_b) |
481 | 99570a40 | balrog | { |
482 | 99570a40 | balrog | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
483 | 99570a40 | balrog | |
484 | 99570a40 | balrog | s->codec.rxavail = avail_b >> 2;
|
485 | ab17b46d | balrog | omap_eac_in_refill(s); |
486 | 99570a40 | balrog | /* TODO: possibly discard current buffer if overrun */
|
487 | ab17b46d | balrog | omap_eac_in_dmarequest_update(s); |
488 | 99570a40 | balrog | } |
489 | 99570a40 | balrog | |
490 | 99570a40 | balrog | static void omap_eac_out_cb(void *opaque, int free_b) |
491 | 99570a40 | balrog | { |
492 | 99570a40 | balrog | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
493 | 99570a40 | balrog | |
494 | 99570a40 | balrog | s->codec.txavail = free_b >> 2;
|
495 | ab17b46d | balrog | if (s->codec.txlen)
|
496 | ab17b46d | balrog | omap_eac_out_empty(s); |
497 | ab17b46d | balrog | else
|
498 | ab17b46d | balrog | omap_eac_out_dmarequest_update(s); |
499 | 99570a40 | balrog | } |
500 | 99570a40 | balrog | |
501 | 99570a40 | balrog | static void omap_eac_enable_update(struct omap_eac_s *s) |
502 | 99570a40 | balrog | { |
503 | 99570a40 | balrog | s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ |
504 | 99570a40 | balrog | (s->codec.config[1] & 2) && /* AUDEN */ |
505 | 99570a40 | balrog | s->codec.hw_enable; |
506 | 99570a40 | balrog | } |
507 | 99570a40 | balrog | |
508 | 99570a40 | balrog | static const int omap_eac_fsint[4] = { |
509 | 99570a40 | balrog | 8000,
|
510 | 99570a40 | balrog | 11025,
|
511 | 99570a40 | balrog | 22050,
|
512 | 99570a40 | balrog | 44100,
|
513 | 99570a40 | balrog | }; |
514 | 99570a40 | balrog | |
515 | 99570a40 | balrog | static const int omap_eac_fsint2[8] = { |
516 | 99570a40 | balrog | 8000,
|
517 | 99570a40 | balrog | 11025,
|
518 | 99570a40 | balrog | 22050,
|
519 | 99570a40 | balrog | 44100,
|
520 | 99570a40 | balrog | 48000,
|
521 | 99570a40 | balrog | 0, 0, 0, |
522 | 99570a40 | balrog | }; |
523 | 99570a40 | balrog | |
524 | 99570a40 | balrog | static const int omap_eac_fsint3[16] = { |
525 | 99570a40 | balrog | 8000,
|
526 | 99570a40 | balrog | 11025,
|
527 | 99570a40 | balrog | 16000,
|
528 | 99570a40 | balrog | 22050,
|
529 | 99570a40 | balrog | 24000,
|
530 | 99570a40 | balrog | 32000,
|
531 | 99570a40 | balrog | 44100,
|
532 | 99570a40 | balrog | 48000,
|
533 | 99570a40 | balrog | 0, 0, 0, 0, 0, 0, 0, 0, |
534 | 99570a40 | balrog | }; |
535 | 99570a40 | balrog | |
536 | 99570a40 | balrog | static void omap_eac_rate_update(struct omap_eac_s *s) |
537 | 99570a40 | balrog | { |
538 | 99570a40 | balrog | int fsint[3]; |
539 | 99570a40 | balrog | |
540 | 99570a40 | balrog | fsint[2] = (s->codec.config[3] >> 9) & 0xf; |
541 | 99570a40 | balrog | fsint[1] = (s->codec.config[2] >> 0) & 0x7; |
542 | 99570a40 | balrog | fsint[0] = (s->codec.config[0] >> 6) & 0x3; |
543 | 99570a40 | balrog | if (fsint[2] < 0xf) |
544 | 99570a40 | balrog | s->codec.rate = omap_eac_fsint3[fsint[2]];
|
545 | 99570a40 | balrog | else if (fsint[1] < 0x7) |
546 | 99570a40 | balrog | s->codec.rate = omap_eac_fsint2[fsint[1]];
|
547 | 99570a40 | balrog | else
|
548 | 99570a40 | balrog | s->codec.rate = omap_eac_fsint[fsint[0]];
|
549 | 99570a40 | balrog | } |
550 | 99570a40 | balrog | |
551 | 99570a40 | balrog | static void omap_eac_volume_update(struct omap_eac_s *s) |
552 | 99570a40 | balrog | { |
553 | 99570a40 | balrog | /* TODO */
|
554 | 99570a40 | balrog | } |
555 | 99570a40 | balrog | |
556 | 99570a40 | balrog | static void omap_eac_format_update(struct omap_eac_s *s) |
557 | 99570a40 | balrog | { |
558 | 1ea879e5 | malc | struct audsettings fmt;
|
559 | 99570a40 | balrog | |
560 | ab17b46d | balrog | /* The hardware buffers at most one sample */
|
561 | ab17b46d | balrog | if (s->codec.rxlen)
|
562 | ab17b46d | balrog | s->codec.rxlen = 1;
|
563 | 99570a40 | balrog | |
564 | 99570a40 | balrog | if (s->codec.in_voice) {
|
565 | 99570a40 | balrog | AUD_set_active_in(s->codec.in_voice, 0);
|
566 | 99570a40 | balrog | AUD_close_in(&s->codec.card, s->codec.in_voice); |
567 | b9d38e95 | Blue Swirl | s->codec.in_voice = NULL;
|
568 | 99570a40 | balrog | } |
569 | 99570a40 | balrog | if (s->codec.out_voice) {
|
570 | ab17b46d | balrog | omap_eac_out_empty(s); |
571 | 99570a40 | balrog | AUD_set_active_out(s->codec.out_voice, 0);
|
572 | 99570a40 | balrog | AUD_close_out(&s->codec.card, s->codec.out_voice); |
573 | b9d38e95 | Blue Swirl | s->codec.out_voice = NULL;
|
574 | ab17b46d | balrog | s->codec.txavail = 0;
|
575 | 99570a40 | balrog | } |
576 | ab17b46d | balrog | /* Discard what couldn't be written */
|
577 | ab17b46d | balrog | s->codec.txlen = 0;
|
578 | 99570a40 | balrog | |
579 | 99570a40 | balrog | omap_eac_enable_update(s); |
580 | 99570a40 | balrog | if (!s->codec.enable)
|
581 | 99570a40 | balrog | return;
|
582 | 99570a40 | balrog | |
583 | 99570a40 | balrog | omap_eac_rate_update(s); |
584 | 99570a40 | balrog | fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ |
585 | 99570a40 | balrog | fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ |
586 | 99570a40 | balrog | fmt.freq = s->codec.rate; |
587 | 99570a40 | balrog | /* TODO: signedness possibly depends on the CODEC hardware - or
|
588 | 99570a40 | balrog | * does I2S specify it? */
|
589 | 99570a40 | balrog | /* All register writes are 16 bits so we we store 16-bit samples
|
590 | 99570a40 | balrog | * in the buffers regardless of AGCFR[B8_16] value. */
|
591 | 99570a40 | balrog | fmt.fmt = AUD_FMT_U16; |
592 | 99570a40 | balrog | |
593 | 99570a40 | balrog | s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, |
594 | 99570a40 | balrog | "eac.codec.in", s, omap_eac_in_cb, &fmt);
|
595 | 99570a40 | balrog | s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, |
596 | 99570a40 | balrog | "eac.codec.out", s, omap_eac_out_cb, &fmt);
|
597 | 99570a40 | balrog | |
598 | 99570a40 | balrog | omap_eac_volume_update(s); |
599 | 99570a40 | balrog | |
600 | 99570a40 | balrog | AUD_set_active_in(s->codec.in_voice, 1);
|
601 | 99570a40 | balrog | AUD_set_active_out(s->codec.out_voice, 1);
|
602 | 99570a40 | balrog | } |
603 | 99570a40 | balrog | |
604 | 99570a40 | balrog | static void omap_eac_reset(struct omap_eac_s *s) |
605 | 99570a40 | balrog | { |
606 | 99570a40 | balrog | s->sysconfig = 0;
|
607 | 99570a40 | balrog | s->config[0] = 0x0c; |
608 | 99570a40 | balrog | s->config[1] = 0x09; |
609 | 99570a40 | balrog | s->config[2] = 0xab; |
610 | 99570a40 | balrog | s->config[3] = 0x03; |
611 | 99570a40 | balrog | s->control = 0x00;
|
612 | 99570a40 | balrog | s->address = 0x00;
|
613 | 99570a40 | balrog | s->data = 0x0000;
|
614 | 99570a40 | balrog | s->vtol = 0x00;
|
615 | 99570a40 | balrog | s->vtsl = 0x00;
|
616 | 99570a40 | balrog | s->mixer = 0x0000;
|
617 | 99570a40 | balrog | s->gain[0] = 0xe7e7; |
618 | 99570a40 | balrog | s->gain[1] = 0x6767; |
619 | 99570a40 | balrog | s->gain[2] = 0x6767; |
620 | 99570a40 | balrog | s->gain[3] = 0x6767; |
621 | 99570a40 | balrog | s->att = 0xce;
|
622 | 99570a40 | balrog | s->max[0] = 0; |
623 | 99570a40 | balrog | s->max[1] = 0; |
624 | 99570a40 | balrog | s->max[2] = 0; |
625 | 99570a40 | balrog | s->max[3] = 0; |
626 | 99570a40 | balrog | s->max[4] = 0; |
627 | 99570a40 | balrog | s->max[5] = 0; |
628 | 99570a40 | balrog | s->max[6] = 0; |
629 | 99570a40 | balrog | |
630 | 99570a40 | balrog | s->modem.control = 0x00;
|
631 | 99570a40 | balrog | s->modem.config = 0x0000;
|
632 | 99570a40 | balrog | s->bt.control = 0x00;
|
633 | 99570a40 | balrog | s->bt.config = 0x0000;
|
634 | 99570a40 | balrog | s->codec.config[0] = 0x0649; |
635 | 99570a40 | balrog | s->codec.config[1] = 0x0000; |
636 | 99570a40 | balrog | s->codec.config[2] = 0x0007; |
637 | 99570a40 | balrog | s->codec.config[3] = 0x1ffc; |
638 | ab17b46d | balrog | s->codec.rxoff = 0;
|
639 | 99570a40 | balrog | s->codec.rxlen = 0;
|
640 | 99570a40 | balrog | s->codec.txlen = 0;
|
641 | 99570a40 | balrog | s->codec.rxavail = 0;
|
642 | 99570a40 | balrog | s->codec.txavail = 0;
|
643 | 99570a40 | balrog | |
644 | 99570a40 | balrog | omap_eac_format_update(s); |
645 | 99570a40 | balrog | omap_eac_interrupt_update(s); |
646 | 99570a40 | balrog | } |
647 | 99570a40 | balrog | |
648 | c227f099 | Anthony Liguori | static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) |
649 | 99570a40 | balrog | { |
650 | 99570a40 | balrog | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
651 | ab17b46d | balrog | uint32_t ret; |
652 | 99570a40 | balrog | |
653 | 8da3ff18 | pbrook | switch (addr) {
|
654 | 99570a40 | balrog | case 0x000: /* CPCFR1 */ |
655 | 99570a40 | balrog | return s->config[0]; |
656 | 99570a40 | balrog | case 0x004: /* CPCFR2 */ |
657 | 99570a40 | balrog | return s->config[1]; |
658 | 99570a40 | balrog | case 0x008: /* CPCFR3 */ |
659 | 99570a40 | balrog | return s->config[2]; |
660 | 99570a40 | balrog | case 0x00c: /* CPCFR4 */ |
661 | 99570a40 | balrog | return s->config[3]; |
662 | 99570a40 | balrog | |
663 | 99570a40 | balrog | case 0x010: /* CPTCTL */ |
664 | 99570a40 | balrog | return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | |
665 | 99570a40 | balrog | ((s->codec.txlen < s->codec.txavail) << 5);
|
666 | 99570a40 | balrog | |
667 | 99570a40 | balrog | case 0x014: /* CPTTADR */ |
668 | 99570a40 | balrog | return s->address;
|
669 | 99570a40 | balrog | case 0x018: /* CPTDATL */ |
670 | 99570a40 | balrog | return s->data & 0xff; |
671 | 99570a40 | balrog | case 0x01c: /* CPTDATH */ |
672 | 99570a40 | balrog | return s->data >> 8; |
673 | 99570a40 | balrog | case 0x020: /* CPTVSLL */ |
674 | 99570a40 | balrog | return s->vtol;
|
675 | 99570a40 | balrog | case 0x024: /* CPTVSLH */ |
676 | 99570a40 | balrog | return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ |
677 | 99570a40 | balrog | case 0x040: /* MPCTR */ |
678 | 99570a40 | balrog | return s->modem.control;
|
679 | 99570a40 | balrog | case 0x044: /* MPMCCFR */ |
680 | 99570a40 | balrog | return s->modem.config;
|
681 | 99570a40 | balrog | case 0x060: /* BPCTR */ |
682 | 99570a40 | balrog | return s->bt.control;
|
683 | 99570a40 | balrog | case 0x064: /* BPMCCFR */ |
684 | 99570a40 | balrog | return s->bt.config;
|
685 | 99570a40 | balrog | case 0x080: /* AMSCFR */ |
686 | 99570a40 | balrog | return s->mixer;
|
687 | 99570a40 | balrog | case 0x084: /* AMVCTR */ |
688 | 99570a40 | balrog | return s->gain[0]; |
689 | 99570a40 | balrog | case 0x088: /* AM1VCTR */ |
690 | 99570a40 | balrog | return s->gain[1]; |
691 | 99570a40 | balrog | case 0x08c: /* AM2VCTR */ |
692 | 99570a40 | balrog | return s->gain[2]; |
693 | 99570a40 | balrog | case 0x090: /* AM3VCTR */ |
694 | 99570a40 | balrog | return s->gain[3]; |
695 | 99570a40 | balrog | case 0x094: /* ASTCTR */ |
696 | 99570a40 | balrog | return s->att;
|
697 | 99570a40 | balrog | case 0x098: /* APD1LCR */ |
698 | 99570a40 | balrog | return s->max[0]; |
699 | 99570a40 | balrog | case 0x09c: /* APD1RCR */ |
700 | 99570a40 | balrog | return s->max[1]; |
701 | 99570a40 | balrog | case 0x0a0: /* APD2LCR */ |
702 | 99570a40 | balrog | return s->max[2]; |
703 | 99570a40 | balrog | case 0x0a4: /* APD2RCR */ |
704 | 99570a40 | balrog | return s->max[3]; |
705 | 99570a40 | balrog | case 0x0a8: /* APD3LCR */ |
706 | 99570a40 | balrog | return s->max[4]; |
707 | 99570a40 | balrog | case 0x0ac: /* APD3RCR */ |
708 | 99570a40 | balrog | return s->max[5]; |
709 | 99570a40 | balrog | case 0x0b0: /* APD4R */ |
710 | 99570a40 | balrog | return s->max[6]; |
711 | 99570a40 | balrog | case 0x0b4: /* ADWR */ |
712 | 99570a40 | balrog | /* This should be write-only? Docs list it as read-only. */
|
713 | 99570a40 | balrog | return 0x0000; |
714 | 99570a40 | balrog | case 0x0b8: /* ADRDR */ |
715 | ab17b46d | balrog | if (likely(s->codec.rxlen > 1)) { |
716 | ab17b46d | balrog | ret = s->codec.rxbuf[s->codec.rxoff ++]; |
717 | ab17b46d | balrog | s->codec.rxlen --; |
718 | ab17b46d | balrog | s->codec.rxoff &= EAC_BUF_LEN - 1;
|
719 | ab17b46d | balrog | return ret;
|
720 | ab17b46d | balrog | } else if (s->codec.rxlen) { |
721 | ab17b46d | balrog | ret = s->codec.rxbuf[s->codec.rxoff ++]; |
722 | ab17b46d | balrog | s->codec.rxlen --; |
723 | ab17b46d | balrog | s->codec.rxoff &= EAC_BUF_LEN - 1;
|
724 | 99570a40 | balrog | if (s->codec.rxavail)
|
725 | 99570a40 | balrog | omap_eac_in_refill(s); |
726 | ab17b46d | balrog | omap_eac_in_dmarequest_update(s); |
727 | ab17b46d | balrog | return ret;
|
728 | 99570a40 | balrog | } |
729 | 99570a40 | balrog | return 0x0000; |
730 | 99570a40 | balrog | case 0x0bc: /* AGCFR */ |
731 | 99570a40 | balrog | return s->codec.config[0]; |
732 | 99570a40 | balrog | case 0x0c0: /* AGCTR */ |
733 | 99570a40 | balrog | return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); |
734 | 99570a40 | balrog | case 0x0c4: /* AGCFR2 */ |
735 | 99570a40 | balrog | return s->codec.config[2]; |
736 | 99570a40 | balrog | case 0x0c8: /* AGCFR3 */ |
737 | 99570a40 | balrog | return s->codec.config[3]; |
738 | 99570a40 | balrog | case 0x0cc: /* MBPDMACTR */ |
739 | 99570a40 | balrog | case 0x0d0: /* MPDDMARR */ |
740 | 99570a40 | balrog | case 0x0d8: /* MPUDMARR */ |
741 | 99570a40 | balrog | case 0x0e4: /* BPDDMARR */ |
742 | 99570a40 | balrog | case 0x0ec: /* BPUDMARR */ |
743 | 99570a40 | balrog | return 0x0000; |
744 | 99570a40 | balrog | |
745 | 99570a40 | balrog | case 0x100: /* VERSION_NUMBER */ |
746 | 99570a40 | balrog | return 0x0010; |
747 | 99570a40 | balrog | |
748 | 99570a40 | balrog | case 0x104: /* SYSCONFIG */ |
749 | 99570a40 | balrog | return s->sysconfig;
|
750 | 99570a40 | balrog | |
751 | 99570a40 | balrog | case 0x108: /* SYSSTATUS */ |
752 | 99570a40 | balrog | return 1 | 0xe; /* RESETDONE | stuff */ |
753 | 99570a40 | balrog | } |
754 | 99570a40 | balrog | |
755 | 99570a40 | balrog | OMAP_BAD_REG(addr); |
756 | 99570a40 | balrog | return 0; |
757 | 99570a40 | balrog | } |
758 | 99570a40 | balrog | |
759 | c227f099 | Anthony Liguori | static void omap_eac_write(void *opaque, target_phys_addr_t addr, |
760 | 99570a40 | balrog | uint32_t value) |
761 | 99570a40 | balrog | { |
762 | 99570a40 | balrog | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
763 | 99570a40 | balrog | |
764 | 8da3ff18 | pbrook | switch (addr) {
|
765 | 99570a40 | balrog | case 0x098: /* APD1LCR */ |
766 | 99570a40 | balrog | case 0x09c: /* APD1RCR */ |
767 | 99570a40 | balrog | case 0x0a0: /* APD2LCR */ |
768 | 99570a40 | balrog | case 0x0a4: /* APD2RCR */ |
769 | 99570a40 | balrog | case 0x0a8: /* APD3LCR */ |
770 | 99570a40 | balrog | case 0x0ac: /* APD3RCR */ |
771 | 99570a40 | balrog | case 0x0b0: /* APD4R */ |
772 | 99570a40 | balrog | case 0x0b8: /* ADRDR */ |
773 | 99570a40 | balrog | case 0x0d0: /* MPDDMARR */ |
774 | 99570a40 | balrog | case 0x0d8: /* MPUDMARR */ |
775 | 99570a40 | balrog | case 0x0e4: /* BPDDMARR */ |
776 | 99570a40 | balrog | case 0x0ec: /* BPUDMARR */ |
777 | 99570a40 | balrog | case 0x100: /* VERSION_NUMBER */ |
778 | 99570a40 | balrog | case 0x108: /* SYSSTATUS */ |
779 | 99570a40 | balrog | OMAP_RO_REG(addr); |
780 | 99570a40 | balrog | return;
|
781 | 99570a40 | balrog | |
782 | 99570a40 | balrog | case 0x000: /* CPCFR1 */ |
783 | 99570a40 | balrog | s->config[0] = value & 0xff; |
784 | 99570a40 | balrog | omap_eac_format_update(s); |
785 | 99570a40 | balrog | break;
|
786 | 99570a40 | balrog | case 0x004: /* CPCFR2 */ |
787 | 99570a40 | balrog | s->config[1] = value & 0xff; |
788 | 99570a40 | balrog | omap_eac_format_update(s); |
789 | 99570a40 | balrog | break;
|
790 | 99570a40 | balrog | case 0x008: /* CPCFR3 */ |
791 | 99570a40 | balrog | s->config[2] = value & 0xff; |
792 | 99570a40 | balrog | omap_eac_format_update(s); |
793 | 99570a40 | balrog | break;
|
794 | 99570a40 | balrog | case 0x00c: /* CPCFR4 */ |
795 | 99570a40 | balrog | s->config[3] = value & 0xff; |
796 | 99570a40 | balrog | omap_eac_format_update(s); |
797 | 99570a40 | balrog | break;
|
798 | 99570a40 | balrog | |
799 | 99570a40 | balrog | case 0x010: /* CPTCTL */ |
800 | 99570a40 | balrog | /* Assuming TXF and TXE bits are read-only... */
|
801 | 99570a40 | balrog | s->control = value & 0x5f;
|
802 | 99570a40 | balrog | omap_eac_interrupt_update(s); |
803 | 99570a40 | balrog | break;
|
804 | 99570a40 | balrog | |
805 | 99570a40 | balrog | case 0x014: /* CPTTADR */ |
806 | 99570a40 | balrog | s->address = value & 0xff;
|
807 | 99570a40 | balrog | break;
|
808 | 99570a40 | balrog | case 0x018: /* CPTDATL */ |
809 | 99570a40 | balrog | s->data &= 0xff00;
|
810 | 99570a40 | balrog | s->data |= value & 0xff;
|
811 | 99570a40 | balrog | break;
|
812 | 99570a40 | balrog | case 0x01c: /* CPTDATH */ |
813 | 99570a40 | balrog | s->data &= 0x00ff;
|
814 | 99570a40 | balrog | s->data |= value << 8;
|
815 | 99570a40 | balrog | break;
|
816 | 99570a40 | balrog | case 0x020: /* CPTVSLL */ |
817 | 99570a40 | balrog | s->vtol = value & 0xf8;
|
818 | 99570a40 | balrog | break;
|
819 | 99570a40 | balrog | case 0x024: /* CPTVSLH */ |
820 | 99570a40 | balrog | s->vtsl = value & 0x9f;
|
821 | 99570a40 | balrog | break;
|
822 | 99570a40 | balrog | case 0x040: /* MPCTR */ |
823 | 99570a40 | balrog | s->modem.control = value & 0x8f;
|
824 | 99570a40 | balrog | break;
|
825 | 99570a40 | balrog | case 0x044: /* MPMCCFR */ |
826 | 99570a40 | balrog | s->modem.config = value & 0x7fff;
|
827 | 99570a40 | balrog | break;
|
828 | 99570a40 | balrog | case 0x060: /* BPCTR */ |
829 | 99570a40 | balrog | s->bt.control = value & 0x8f;
|
830 | 99570a40 | balrog | break;
|
831 | 99570a40 | balrog | case 0x064: /* BPMCCFR */ |
832 | 99570a40 | balrog | s->bt.config = value & 0x7fff;
|
833 | 99570a40 | balrog | break;
|
834 | 99570a40 | balrog | case 0x080: /* AMSCFR */ |
835 | 99570a40 | balrog | s->mixer = value & 0x0fff;
|
836 | 99570a40 | balrog | break;
|
837 | 99570a40 | balrog | case 0x084: /* AMVCTR */ |
838 | 99570a40 | balrog | s->gain[0] = value & 0xffff; |
839 | 99570a40 | balrog | break;
|
840 | 99570a40 | balrog | case 0x088: /* AM1VCTR */ |
841 | 99570a40 | balrog | s->gain[1] = value & 0xff7f; |
842 | 99570a40 | balrog | break;
|
843 | 99570a40 | balrog | case 0x08c: /* AM2VCTR */ |
844 | 99570a40 | balrog | s->gain[2] = value & 0xff7f; |
845 | 99570a40 | balrog | break;
|
846 | 99570a40 | balrog | case 0x090: /* AM3VCTR */ |
847 | 99570a40 | balrog | s->gain[3] = value & 0xff7f; |
848 | 99570a40 | balrog | break;
|
849 | 99570a40 | balrog | case 0x094: /* ASTCTR */ |
850 | 99570a40 | balrog | s->att = value & 0xff;
|
851 | 99570a40 | balrog | break;
|
852 | 99570a40 | balrog | |
853 | 99570a40 | balrog | case 0x0b4: /* ADWR */ |
854 | 99570a40 | balrog | s->codec.txbuf[s->codec.txlen ++] = value; |
855 | 99570a40 | balrog | if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
|
856 | 99570a40 | balrog | s->codec.txlen == s->codec.txavail)) { |
857 | 99570a40 | balrog | if (s->codec.txavail)
|
858 | 99570a40 | balrog | omap_eac_out_empty(s); |
859 | ab17b46d | balrog | /* Discard what couldn't be written */
|
860 | ab17b46d | balrog | s->codec.txlen = 0;
|
861 | 99570a40 | balrog | } |
862 | 99570a40 | balrog | break;
|
863 | 99570a40 | balrog | |
864 | 99570a40 | balrog | case 0x0bc: /* AGCFR */ |
865 | 99570a40 | balrog | s->codec.config[0] = value & 0x07ff; |
866 | 99570a40 | balrog | omap_eac_format_update(s); |
867 | 99570a40 | balrog | break;
|
868 | 99570a40 | balrog | case 0x0c0: /* AGCTR */ |
869 | 99570a40 | balrog | s->codec.config[1] = value & 0x780f; |
870 | 99570a40 | balrog | omap_eac_format_update(s); |
871 | 99570a40 | balrog | break;
|
872 | 99570a40 | balrog | case 0x0c4: /* AGCFR2 */ |
873 | 99570a40 | balrog | s->codec.config[2] = value & 0x003f; |
874 | 99570a40 | balrog | omap_eac_format_update(s); |
875 | 99570a40 | balrog | break;
|
876 | 99570a40 | balrog | case 0x0c8: /* AGCFR3 */ |
877 | 99570a40 | balrog | s->codec.config[3] = value & 0xffff; |
878 | 99570a40 | balrog | omap_eac_format_update(s); |
879 | 99570a40 | balrog | break;
|
880 | 99570a40 | balrog | case 0x0cc: /* MBPDMACTR */ |
881 | 99570a40 | balrog | case 0x0d4: /* MPDDMAWR */ |
882 | 99570a40 | balrog | case 0x0e0: /* MPUDMAWR */ |
883 | 99570a40 | balrog | case 0x0e8: /* BPDDMAWR */ |
884 | 99570a40 | balrog | case 0x0f0: /* BPUDMAWR */ |
885 | 99570a40 | balrog | break;
|
886 | 99570a40 | balrog | |
887 | 99570a40 | balrog | case 0x104: /* SYSCONFIG */ |
888 | 99570a40 | balrog | if (value & (1 << 1)) /* SOFTRESET */ |
889 | 99570a40 | balrog | omap_eac_reset(s); |
890 | 99570a40 | balrog | s->sysconfig = value & 0x31d;
|
891 | 99570a40 | balrog | break;
|
892 | 99570a40 | balrog | |
893 | 99570a40 | balrog | default:
|
894 | 99570a40 | balrog | OMAP_BAD_REG(addr); |
895 | 99570a40 | balrog | return;
|
896 | 99570a40 | balrog | } |
897 | 99570a40 | balrog | } |
898 | 99570a40 | balrog | |
899 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_eac_readfn[] = { |
900 | 99570a40 | balrog | omap_badwidth_read16, |
901 | 99570a40 | balrog | omap_eac_read, |
902 | 99570a40 | balrog | omap_badwidth_read16, |
903 | 99570a40 | balrog | }; |
904 | 99570a40 | balrog | |
905 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_eac_writefn[] = { |
906 | 99570a40 | balrog | omap_badwidth_write16, |
907 | 99570a40 | balrog | omap_eac_write, |
908 | 99570a40 | balrog | omap_badwidth_write16, |
909 | 99570a40 | balrog | }; |
910 | 99570a40 | balrog | |
911 | 99570a40 | balrog | struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, |
912 | 99570a40 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
913 | 99570a40 | balrog | { |
914 | 99570a40 | balrog | int iomemtype;
|
915 | 99570a40 | balrog | struct omap_eac_s *s = (struct omap_eac_s *) |
916 | 99570a40 | balrog | qemu_mallocz(sizeof(struct omap_eac_s)); |
917 | 99570a40 | balrog | |
918 | 99570a40 | balrog | s->irq = irq; |
919 | 99570a40 | balrog | s->codec.rxdrq = *drq ++; |
920 | 22ed1d34 | Blue Swirl | s->codec.txdrq = *drq; |
921 | 99570a40 | balrog | omap_eac_reset(s); |
922 | 99570a40 | balrog | |
923 | 1a7dafce | malc | AUD_register_card("OMAP EAC", &s->codec.card);
|
924 | 99570a40 | balrog | |
925 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_eac_readfn, |
926 | 99570a40 | balrog | omap_eac_writefn, s); |
927 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
928 | 99570a40 | balrog | |
929 | 99570a40 | balrog | return s;
|
930 | 99570a40 | balrog | } |
931 | 99570a40 | balrog | |
932 | 54585ffe | balrog | /* STI/XTI (emulation interface) console - reverse engineered only */
|
933 | 54585ffe | balrog | struct omap_sti_s {
|
934 | 54585ffe | balrog | qemu_irq irq; |
935 | 54585ffe | balrog | CharDriverState *chr; |
936 | 54585ffe | balrog | |
937 | 54585ffe | balrog | uint32_t sysconfig; |
938 | 54585ffe | balrog | uint32_t systest; |
939 | 54585ffe | balrog | uint32_t irqst; |
940 | 54585ffe | balrog | uint32_t irqen; |
941 | 54585ffe | balrog | uint32_t clkcontrol; |
942 | 54585ffe | balrog | uint32_t serial_config; |
943 | 54585ffe | balrog | }; |
944 | 54585ffe | balrog | |
945 | 54585ffe | balrog | #define STI_TRACE_CONSOLE_CHANNEL 239 |
946 | 54585ffe | balrog | #define STI_TRACE_CONTROL_CHANNEL 253 |
947 | 54585ffe | balrog | |
948 | 54585ffe | balrog | static inline void omap_sti_interrupt_update(struct omap_sti_s *s) |
949 | 54585ffe | balrog | { |
950 | 54585ffe | balrog | qemu_set_irq(s->irq, s->irqst & s->irqen); |
951 | 54585ffe | balrog | } |
952 | 54585ffe | balrog | |
953 | 54585ffe | balrog | static void omap_sti_reset(struct omap_sti_s *s) |
954 | 54585ffe | balrog | { |
955 | 54585ffe | balrog | s->sysconfig = 0;
|
956 | 54585ffe | balrog | s->irqst = 0;
|
957 | 54585ffe | balrog | s->irqen = 0;
|
958 | 54585ffe | balrog | s->clkcontrol = 0;
|
959 | 54585ffe | balrog | s->serial_config = 0;
|
960 | 54585ffe | balrog | |
961 | 54585ffe | balrog | omap_sti_interrupt_update(s); |
962 | 54585ffe | balrog | } |
963 | 54585ffe | balrog | |
964 | c227f099 | Anthony Liguori | static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) |
965 | 54585ffe | balrog | { |
966 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
967 | 54585ffe | balrog | |
968 | 8da3ff18 | pbrook | switch (addr) {
|
969 | 54585ffe | balrog | case 0x00: /* STI_REVISION */ |
970 | 54585ffe | balrog | return 0x10; |
971 | 54585ffe | balrog | |
972 | 54585ffe | balrog | case 0x10: /* STI_SYSCONFIG */ |
973 | 54585ffe | balrog | return s->sysconfig;
|
974 | 54585ffe | balrog | |
975 | 54585ffe | balrog | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
976 | 54585ffe | balrog | return 0x00; |
977 | 54585ffe | balrog | |
978 | 54585ffe | balrog | case 0x18: /* STI_IRQSTATUS */ |
979 | 54585ffe | balrog | return s->irqst;
|
980 | 54585ffe | balrog | |
981 | 54585ffe | balrog | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
982 | 54585ffe | balrog | return s->irqen;
|
983 | 54585ffe | balrog | |
984 | 54585ffe | balrog | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
985 | 54585ffe | balrog | case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
986 | e927bb00 | balrog | /* TODO */
|
987 | e927bb00 | balrog | return 0; |
988 | 54585ffe | balrog | |
989 | 54585ffe | balrog | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
990 | 54585ffe | balrog | return s->clkcontrol;
|
991 | 54585ffe | balrog | |
992 | 54585ffe | balrog | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
993 | 54585ffe | balrog | return s->serial_config;
|
994 | 54585ffe | balrog | } |
995 | 54585ffe | balrog | |
996 | 54585ffe | balrog | OMAP_BAD_REG(addr); |
997 | 54585ffe | balrog | return 0; |
998 | 54585ffe | balrog | } |
999 | 54585ffe | balrog | |
1000 | c227f099 | Anthony Liguori | static void omap_sti_write(void *opaque, target_phys_addr_t addr, |
1001 | 54585ffe | balrog | uint32_t value) |
1002 | 54585ffe | balrog | { |
1003 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
1004 | 54585ffe | balrog | |
1005 | 8da3ff18 | pbrook | switch (addr) {
|
1006 | 54585ffe | balrog | case 0x00: /* STI_REVISION */ |
1007 | 54585ffe | balrog | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
1008 | 54585ffe | balrog | OMAP_RO_REG(addr); |
1009 | 54585ffe | balrog | return;
|
1010 | 54585ffe | balrog | |
1011 | 54585ffe | balrog | case 0x10: /* STI_SYSCONFIG */ |
1012 | 54585ffe | balrog | if (value & (1 << 1)) /* SOFTRESET */ |
1013 | 54585ffe | balrog | omap_sti_reset(s); |
1014 | 54585ffe | balrog | s->sysconfig = value & 0xfe;
|
1015 | 54585ffe | balrog | break;
|
1016 | 54585ffe | balrog | |
1017 | 54585ffe | balrog | case 0x18: /* STI_IRQSTATUS */ |
1018 | 54585ffe | balrog | s->irqst &= ~value; |
1019 | 54585ffe | balrog | omap_sti_interrupt_update(s); |
1020 | 54585ffe | balrog | break;
|
1021 | 54585ffe | balrog | |
1022 | 54585ffe | balrog | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
1023 | 54585ffe | balrog | s->irqen = value & 0xffff;
|
1024 | 54585ffe | balrog | omap_sti_interrupt_update(s); |
1025 | 54585ffe | balrog | break;
|
1026 | 54585ffe | balrog | |
1027 | 54585ffe | balrog | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
1028 | 54585ffe | balrog | s->clkcontrol = value & 0xff;
|
1029 | 54585ffe | balrog | break;
|
1030 | 54585ffe | balrog | |
1031 | 54585ffe | balrog | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
1032 | 54585ffe | balrog | s->serial_config = value & 0xff;
|
1033 | 54585ffe | balrog | break;
|
1034 | 54585ffe | balrog | |
1035 | 54585ffe | balrog | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
1036 | 54585ffe | balrog | case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
1037 | e927bb00 | balrog | /* TODO */
|
1038 | e927bb00 | balrog | return;
|
1039 | e927bb00 | balrog | |
1040 | 54585ffe | balrog | default:
|
1041 | 54585ffe | balrog | OMAP_BAD_REG(addr); |
1042 | 54585ffe | balrog | return;
|
1043 | 54585ffe | balrog | } |
1044 | 54585ffe | balrog | } |
1045 | 54585ffe | balrog | |
1046 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_sti_readfn[] = { |
1047 | 54585ffe | balrog | omap_badwidth_read32, |
1048 | 54585ffe | balrog | omap_badwidth_read32, |
1049 | 54585ffe | balrog | omap_sti_read, |
1050 | 54585ffe | balrog | }; |
1051 | 54585ffe | balrog | |
1052 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_sti_writefn[] = { |
1053 | 54585ffe | balrog | omap_badwidth_write32, |
1054 | 54585ffe | balrog | omap_badwidth_write32, |
1055 | 54585ffe | balrog | omap_sti_write, |
1056 | 54585ffe | balrog | }; |
1057 | 54585ffe | balrog | |
1058 | c227f099 | Anthony Liguori | static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) |
1059 | 54585ffe | balrog | { |
1060 | 54585ffe | balrog | OMAP_BAD_REG(addr); |
1061 | 54585ffe | balrog | return 0; |
1062 | 54585ffe | balrog | } |
1063 | 54585ffe | balrog | |
1064 | c227f099 | Anthony Liguori | static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, |
1065 | 54585ffe | balrog | uint32_t value) |
1066 | 54585ffe | balrog | { |
1067 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
1068 | 8da3ff18 | pbrook | int ch = addr >> 6; |
1069 | 54585ffe | balrog | uint8_t byte = value; |
1070 | 54585ffe | balrog | |
1071 | 54585ffe | balrog | if (ch == STI_TRACE_CONTROL_CHANNEL) {
|
1072 | 54585ffe | balrog | /* Flush channel <i>value</i>. */
|
1073 | 75554a3c | balrog | qemu_chr_write(s->chr, (const uint8_t *) "\r", 1); |
1074 | 54585ffe | balrog | } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { |
1075 | 54585ffe | balrog | if (value == 0xc0 || value == 0xc3) { |
1076 | 54585ffe | balrog | /* Open channel <i>ch</i>. */
|
1077 | 54585ffe | balrog | } else if (value == 0x00) |
1078 | 75554a3c | balrog | qemu_chr_write(s->chr, (const uint8_t *) "\n", 1); |
1079 | 54585ffe | balrog | else
|
1080 | 54585ffe | balrog | qemu_chr_write(s->chr, &byte, 1);
|
1081 | 54585ffe | balrog | } |
1082 | 54585ffe | balrog | } |
1083 | 54585ffe | balrog | |
1084 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = { |
1085 | 54585ffe | balrog | omap_sti_fifo_read, |
1086 | 54585ffe | balrog | omap_badwidth_read8, |
1087 | 54585ffe | balrog | omap_badwidth_read8, |
1088 | 54585ffe | balrog | }; |
1089 | 54585ffe | balrog | |
1090 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = { |
1091 | 54585ffe | balrog | omap_sti_fifo_write, |
1092 | 54585ffe | balrog | omap_badwidth_write8, |
1093 | 54585ffe | balrog | omap_badwidth_write8, |
1094 | 54585ffe | balrog | }; |
1095 | 54585ffe | balrog | |
1096 | b1d8e52e | blueswir1 | static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, |
1097 | c227f099 | Anthony Liguori | target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, |
1098 | 54585ffe | balrog | CharDriverState *chr) |
1099 | 54585ffe | balrog | { |
1100 | 54585ffe | balrog | int iomemtype;
|
1101 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) |
1102 | 54585ffe | balrog | qemu_mallocz(sizeof(struct omap_sti_s)); |
1103 | 54585ffe | balrog | |
1104 | 54585ffe | balrog | s->irq = irq; |
1105 | 54585ffe | balrog | omap_sti_reset(s); |
1106 | 54585ffe | balrog | |
1107 | ceecf1d1 | aurel32 | s->chr = chr ?: qemu_chr_open("null", "null", NULL); |
1108 | 54585ffe | balrog | |
1109 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_sti_readfn, |
1110 | 54585ffe | balrog | omap_sti_writefn, s); |
1111 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
1112 | 54585ffe | balrog | |
1113 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn, |
1114 | 54585ffe | balrog | omap_sti_fifo_writefn, s); |
1115 | 8da3ff18 | pbrook | cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
|
1116 | 54585ffe | balrog | |
1117 | 54585ffe | balrog | return s;
|
1118 | 54585ffe | balrog | } |
1119 | 54585ffe | balrog | |
1120 | 827df9f3 | balrog | /* L4 Interconnect */
|
1121 | 827df9f3 | balrog | struct omap_target_agent_s {
|
1122 | 827df9f3 | balrog | struct omap_l4_s *bus;
|
1123 | 827df9f3 | balrog | int regions;
|
1124 | 827df9f3 | balrog | struct omap_l4_region_s *start;
|
1125 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
1126 | 827df9f3 | balrog | uint32_t component; |
1127 | 827df9f3 | balrog | uint32_t control; |
1128 | 827df9f3 | balrog | uint32_t status; |
1129 | 827df9f3 | balrog | }; |
1130 | 827df9f3 | balrog | |
1131 | 827df9f3 | balrog | struct omap_l4_s {
|
1132 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
1133 | 827df9f3 | balrog | int ta_num;
|
1134 | 827df9f3 | balrog | struct omap_target_agent_s ta[0]; |
1135 | 827df9f3 | balrog | }; |
1136 | 827df9f3 | balrog | |
1137 | c66fb5bc | balrog | #ifdef L4_MUX_HACK
|
1138 | c66fb5bc | balrog | static int omap_l4_io_entries; |
1139 | c66fb5bc | balrog | static int omap_cpu_io_entry; |
1140 | c66fb5bc | balrog | static struct omap_l4_entry { |
1141 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const *mem_read;
|
1142 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write;
|
1143 | c66fb5bc | balrog | void *opaque;
|
1144 | c66fb5bc | balrog | } *omap_l4_io_entry; |
1145 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const *omap_l4_io_readb_fn; |
1146 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const *omap_l4_io_readh_fn; |
1147 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const *omap_l4_io_readw_fn; |
1148 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn; |
1149 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn; |
1150 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn; |
1151 | c66fb5bc | balrog | static void **omap_l4_io_opaque; |
1152 | c66fb5bc | balrog | |
1153 | d60efc6b | Blue Swirl | int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
1154 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write, void *opaque) |
1155 | c66fb5bc | balrog | { |
1156 | c66fb5bc | balrog | omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read; |
1157 | c66fb5bc | balrog | omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write; |
1158 | c66fb5bc | balrog | omap_l4_io_entry[omap_l4_io_entries].opaque = opaque; |
1159 | c66fb5bc | balrog | |
1160 | c66fb5bc | balrog | return omap_l4_io_entries ++;
|
1161 | c66fb5bc | balrog | } |
1162 | c66fb5bc | balrog | |
1163 | c227f099 | Anthony Liguori | static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) |
1164 | c66fb5bc | balrog | { |
1165 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1166 | c66fb5bc | balrog | |
1167 | c66fb5bc | balrog | return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
|
1168 | c66fb5bc | balrog | } |
1169 | c66fb5bc | balrog | |
1170 | c227f099 | Anthony Liguori | static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) |
1171 | c66fb5bc | balrog | { |
1172 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1173 | c66fb5bc | balrog | |
1174 | c66fb5bc | balrog | return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
|
1175 | c66fb5bc | balrog | } |
1176 | c66fb5bc | balrog | |
1177 | c227f099 | Anthony Liguori | static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) |
1178 | c66fb5bc | balrog | { |
1179 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1180 | c66fb5bc | balrog | |
1181 | c66fb5bc | balrog | return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
|
1182 | c66fb5bc | balrog | } |
1183 | c66fb5bc | balrog | |
1184 | c227f099 | Anthony Liguori | static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, |
1185 | c66fb5bc | balrog | uint32_t value) |
1186 | c66fb5bc | balrog | { |
1187 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1188 | c66fb5bc | balrog | |
1189 | c66fb5bc | balrog | return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
|
1190 | c66fb5bc | balrog | } |
1191 | c66fb5bc | balrog | |
1192 | c227f099 | Anthony Liguori | static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, |
1193 | c66fb5bc | balrog | uint32_t value) |
1194 | c66fb5bc | balrog | { |
1195 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1196 | c66fb5bc | balrog | |
1197 | c66fb5bc | balrog | return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
|
1198 | c66fb5bc | balrog | } |
1199 | c66fb5bc | balrog | |
1200 | c227f099 | Anthony Liguori | static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, |
1201 | c66fb5bc | balrog | uint32_t value) |
1202 | c66fb5bc | balrog | { |
1203 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1204 | c66fb5bc | balrog | |
1205 | c66fb5bc | balrog | return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
|
1206 | c66fb5bc | balrog | } |
1207 | c66fb5bc | balrog | |
1208 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_l4_io_readfn[] = { |
1209 | c66fb5bc | balrog | omap_l4_io_readb, |
1210 | c66fb5bc | balrog | omap_l4_io_readh, |
1211 | c66fb5bc | balrog | omap_l4_io_readw, |
1212 | c66fb5bc | balrog | }; |
1213 | c66fb5bc | balrog | |
1214 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = { |
1215 | c66fb5bc | balrog | omap_l4_io_writeb, |
1216 | c66fb5bc | balrog | omap_l4_io_writeh, |
1217 | c66fb5bc | balrog | omap_l4_io_writew, |
1218 | c66fb5bc | balrog | }; |
1219 | c66fb5bc | balrog | #endif
|
1220 | c66fb5bc | balrog | |
1221 | c227f099 | Anthony Liguori | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) |
1222 | 827df9f3 | balrog | { |
1223 | 827df9f3 | balrog | struct omap_l4_s *bus = qemu_mallocz(
|
1224 | 827df9f3 | balrog | sizeof(*bus) + ta_num * sizeof(*bus->ta)); |
1225 | 827df9f3 | balrog | |
1226 | 827df9f3 | balrog | bus->ta_num = ta_num; |
1227 | 827df9f3 | balrog | bus->base = base; |
1228 | 827df9f3 | balrog | |
1229 | c66fb5bc | balrog | #ifdef L4_MUX_HACK
|
1230 | c66fb5bc | balrog | omap_l4_io_entries = 1;
|
1231 | c66fb5bc | balrog | omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry)); |
1232 | c66fb5bc | balrog | |
1233 | c66fb5bc | balrog | omap_cpu_io_entry = |
1234 | 1eed09cb | Avi Kivity | cpu_register_io_memory(omap_l4_io_readfn, |
1235 | c66fb5bc | balrog | omap_l4_io_writefn, bus); |
1236 | c66fb5bc | balrog | # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) |
1237 | c66fb5bc | balrog | omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1238 | c66fb5bc | balrog | omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1239 | c66fb5bc | balrog | omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1240 | c66fb5bc | balrog | omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1241 | c66fb5bc | balrog | omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1242 | c66fb5bc | balrog | omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1243 | c66fb5bc | balrog | omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1244 | c66fb5bc | balrog | #endif
|
1245 | c66fb5bc | balrog | |
1246 | 827df9f3 | balrog | return bus;
|
1247 | 827df9f3 | balrog | } |
1248 | 827df9f3 | balrog | |
1249 | c227f099 | Anthony Liguori | static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) |
1250 | 827df9f3 | balrog | { |
1251 | 827df9f3 | balrog | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
1252 | 827df9f3 | balrog | |
1253 | 8da3ff18 | pbrook | switch (addr) {
|
1254 | 827df9f3 | balrog | case 0x00: /* COMPONENT */ |
1255 | 827df9f3 | balrog | return s->component;
|
1256 | 827df9f3 | balrog | |
1257 | 827df9f3 | balrog | case 0x20: /* AGENT_CONTROL */ |
1258 | 827df9f3 | balrog | return s->control;
|
1259 | 827df9f3 | balrog | |
1260 | 827df9f3 | balrog | case 0x28: /* AGENT_STATUS */ |
1261 | 827df9f3 | balrog | return s->status;
|
1262 | 827df9f3 | balrog | } |
1263 | 827df9f3 | balrog | |
1264 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1265 | 827df9f3 | balrog | return 0; |
1266 | 827df9f3 | balrog | } |
1267 | 827df9f3 | balrog | |
1268 | c227f099 | Anthony Liguori | static void omap_l4ta_write(void *opaque, target_phys_addr_t addr, |
1269 | 827df9f3 | balrog | uint32_t value) |
1270 | 827df9f3 | balrog | { |
1271 | 827df9f3 | balrog | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
1272 | 827df9f3 | balrog | |
1273 | 8da3ff18 | pbrook | switch (addr) {
|
1274 | 827df9f3 | balrog | case 0x00: /* COMPONENT */ |
1275 | 827df9f3 | balrog | case 0x28: /* AGENT_STATUS */ |
1276 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1277 | 827df9f3 | balrog | break;
|
1278 | 827df9f3 | balrog | |
1279 | 827df9f3 | balrog | case 0x20: /* AGENT_CONTROL */ |
1280 | 827df9f3 | balrog | s->control = value & 0x01000700;
|
1281 | 827df9f3 | balrog | if (value & 1) /* OCP_RESET */ |
1282 | 827df9f3 | balrog | s->status &= ~1; /* REQ_TIMEOUT */ |
1283 | 827df9f3 | balrog | break;
|
1284 | 827df9f3 | balrog | |
1285 | 827df9f3 | balrog | default:
|
1286 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1287 | 827df9f3 | balrog | } |
1288 | 827df9f3 | balrog | } |
1289 | 827df9f3 | balrog | |
1290 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_l4ta_readfn[] = { |
1291 | 827df9f3 | balrog | omap_badwidth_read16, |
1292 | 827df9f3 | balrog | omap_l4ta_read, |
1293 | 827df9f3 | balrog | omap_badwidth_read16, |
1294 | 827df9f3 | balrog | }; |
1295 | 827df9f3 | balrog | |
1296 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = { |
1297 | 827df9f3 | balrog | omap_badwidth_write32, |
1298 | 827df9f3 | balrog | omap_badwidth_write32, |
1299 | 827df9f3 | balrog | omap_l4ta_write, |
1300 | 827df9f3 | balrog | }; |
1301 | 827df9f3 | balrog | |
1302 | 827df9f3 | balrog | #define L4TA(n) (n)
|
1303 | 827df9f3 | balrog | #define L4TAO(n) ((n) + 39) |
1304 | 827df9f3 | balrog | |
1305 | 827df9f3 | balrog | static struct omap_l4_region_s { |
1306 | c227f099 | Anthony Liguori | target_phys_addr_t offset; |
1307 | 827df9f3 | balrog | size_t size; |
1308 | 827df9f3 | balrog | int access;
|
1309 | 827df9f3 | balrog | } omap_l4_region[125] = {
|
1310 | 827df9f3 | balrog | [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ |
1311 | 827df9f3 | balrog | [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ |
1312 | 827df9f3 | balrog | [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ |
1313 | 827df9f3 | balrog | [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ |
1314 | 827df9f3 | balrog | [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ |
1315 | 827df9f3 | balrog | [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ |
1316 | 827df9f3 | balrog | [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ |
1317 | 827df9f3 | balrog | [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ |
1318 | 827df9f3 | balrog | [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ |
1319 | 827df9f3 | balrog | [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ |
1320 | 827df9f3 | balrog | [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ |
1321 | 827df9f3 | balrog | [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ |
1322 | 827df9f3 | balrog | [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ |
1323 | 827df9f3 | balrog | [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ |
1324 | 827df9f3 | balrog | [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ |
1325 | 827df9f3 | balrog | [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ |
1326 | 827df9f3 | balrog | [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ |
1327 | 827df9f3 | balrog | [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ |
1328 | 827df9f3 | balrog | [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ |
1329 | 827df9f3 | balrog | [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ |
1330 | 827df9f3 | balrog | [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ |
1331 | 827df9f3 | balrog | [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ |
1332 | 827df9f3 | balrog | [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ |
1333 | 827df9f3 | balrog | [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ |
1334 | 827df9f3 | balrog | [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ |
1335 | 827df9f3 | balrog | [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ |
1336 | 827df9f3 | balrog | [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ |
1337 | 827df9f3 | balrog | [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ |
1338 | 827df9f3 | balrog | [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ |
1339 | 827df9f3 | balrog | [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ |
1340 | 827df9f3 | balrog | [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ |
1341 | 827df9f3 | balrog | [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ |
1342 | 827df9f3 | balrog | [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ |
1343 | 827df9f3 | balrog | [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ |
1344 | 827df9f3 | balrog | [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ |
1345 | 827df9f3 | balrog | [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ |
1346 | 827df9f3 | balrog | [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ |
1347 | 827df9f3 | balrog | [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ |
1348 | 827df9f3 | balrog | [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ |
1349 | 827df9f3 | balrog | [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ |
1350 | 827df9f3 | balrog | [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ |
1351 | 827df9f3 | balrog | [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ |
1352 | 827df9f3 | balrog | [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ |
1353 | 827df9f3 | balrog | [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ |
1354 | 827df9f3 | balrog | [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ |
1355 | 827df9f3 | balrog | [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ |
1356 | 827df9f3 | balrog | [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ |
1357 | 827df9f3 | balrog | [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ |
1358 | 827df9f3 | balrog | [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ |
1359 | 827df9f3 | balrog | [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ |
1360 | 827df9f3 | balrog | [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ |
1361 | 827df9f3 | balrog | [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ |
1362 | 827df9f3 | balrog | [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ |
1363 | 827df9f3 | balrog | [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ |
1364 | 827df9f3 | balrog | [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ |
1365 | 827df9f3 | balrog | [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ |
1366 | 827df9f3 | balrog | [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ |
1367 | 827df9f3 | balrog | [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ |
1368 | 827df9f3 | balrog | [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ |
1369 | 827df9f3 | balrog | [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ |
1370 | 827df9f3 | balrog | [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ |
1371 | 827df9f3 | balrog | [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ |
1372 | 827df9f3 | balrog | [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ |
1373 | 827df9f3 | balrog | [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ |
1374 | 827df9f3 | balrog | [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ |
1375 | 827df9f3 | balrog | [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ |
1376 | 827df9f3 | balrog | [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ |
1377 | 827df9f3 | balrog | [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ |
1378 | 827df9f3 | balrog | [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ |
1379 | 827df9f3 | balrog | [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ |
1380 | 827df9f3 | balrog | [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ |
1381 | 827df9f3 | balrog | [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ |
1382 | 827df9f3 | balrog | [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ |
1383 | 827df9f3 | balrog | [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ |
1384 | 827df9f3 | balrog | [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ |
1385 | 827df9f3 | balrog | [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ |
1386 | 827df9f3 | balrog | [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ |
1387 | 827df9f3 | balrog | [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ |
1388 | 827df9f3 | balrog | [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ |
1389 | 827df9f3 | balrog | [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ |
1390 | 827df9f3 | balrog | [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ |
1391 | 827df9f3 | balrog | [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ |
1392 | 827df9f3 | balrog | [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ |
1393 | 827df9f3 | balrog | [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ |
1394 | 827df9f3 | balrog | [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ |
1395 | 827df9f3 | balrog | [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ |
1396 | 827df9f3 | balrog | [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ |
1397 | 827df9f3 | balrog | [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ |
1398 | 827df9f3 | balrog | [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ |
1399 | 827df9f3 | balrog | [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ |
1400 | 827df9f3 | balrog | [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ |
1401 | 827df9f3 | balrog | [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ |
1402 | 827df9f3 | balrog | [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ |
1403 | 827df9f3 | balrog | [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ |
1404 | 827df9f3 | balrog | [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ |
1405 | 827df9f3 | balrog | [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ |
1406 | 827df9f3 | balrog | [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ |
1407 | 827df9f3 | balrog | [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ |
1408 | 827df9f3 | balrog | [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ |
1409 | 827df9f3 | balrog | [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ |
1410 | 827df9f3 | balrog | [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ |
1411 | 827df9f3 | balrog | [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ |
1412 | 827df9f3 | balrog | [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ |
1413 | 827df9f3 | balrog | [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ |
1414 | 827df9f3 | balrog | [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ |
1415 | 827df9f3 | balrog | [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ |
1416 | 827df9f3 | balrog | [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ |
1417 | 827df9f3 | balrog | [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ |
1418 | 827df9f3 | balrog | [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ |
1419 | 827df9f3 | balrog | [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ |
1420 | 827df9f3 | balrog | [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ |
1421 | 827df9f3 | balrog | [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ |
1422 | 827df9f3 | balrog | [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ |
1423 | 827df9f3 | balrog | [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ |
1424 | 827df9f3 | balrog | [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ |
1425 | 827df9f3 | balrog | [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ |
1426 | 827df9f3 | balrog | [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ |
1427 | 827df9f3 | balrog | [117] = { 0xa6000, 0x1000, 32 }, /* AES */ |
1428 | 827df9f3 | balrog | [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ |
1429 | 827df9f3 | balrog | [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ |
1430 | 827df9f3 | balrog | [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ |
1431 | 827df9f3 | balrog | [121] = { 0xb0000, 0x1000, 32 }, /* MG */ |
1432 | 827df9f3 | balrog | [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, |
1433 | 827df9f3 | balrog | [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ |
1434 | 827df9f3 | balrog | [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ |
1435 | 827df9f3 | balrog | }; |
1436 | 827df9f3 | balrog | |
1437 | 827df9f3 | balrog | static struct omap_l4_agent_info_s { |
1438 | 827df9f3 | balrog | int ta;
|
1439 | 827df9f3 | balrog | int region;
|
1440 | 827df9f3 | balrog | int regions;
|
1441 | 827df9f3 | balrog | int ta_region;
|
1442 | 827df9f3 | balrog | } omap_l4_agent_info[54] = {
|
1443 | 827df9f3 | balrog | { 0, 0, 3, 2 }, /* L4IA initiatior agent */ |
1444 | 827df9f3 | balrog | { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ |
1445 | 827df9f3 | balrog | { L4TAO(2), 5, 2, 1 }, /* 32K timer */ |
1446 | 827df9f3 | balrog | { L4TAO(3), 7, 3, 2 }, /* PRCM */ |
1447 | 827df9f3 | balrog | { L4TA(1), 10, 2, 1 }, /* BCM */ |
1448 | 827df9f3 | balrog | { L4TA(2), 12, 2, 1 }, /* Test JTAG */ |
1449 | 827df9f3 | balrog | { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ |
1450 | 827df9f3 | balrog | { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ |
1451 | 827df9f3 | balrog | { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ |
1452 | 827df9f3 | balrog | { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ |
1453 | 827df9f3 | balrog | { L4TA(10), 28, 5, 4 }, /* Display subsystem */ |
1454 | 827df9f3 | balrog | { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ |
1455 | 827df9f3 | balrog | { L4TA(12), 38, 2, 1 }, /* sDMA */ |
1456 | 827df9f3 | balrog | { L4TA(13), 40, 5, 4 }, /* SSI */ |
1457 | 827df9f3 | balrog | { L4TAO(4), 45, 2, 1 }, /* USB */ |
1458 | 827df9f3 | balrog | { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ |
1459 | 827df9f3 | balrog | { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ |
1460 | 827df9f3 | balrog | { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ |
1461 | 827df9f3 | balrog | { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ |
1462 | 827df9f3 | balrog | { L4TA(18), 55, 2, 1 }, /* XTI */ |
1463 | 827df9f3 | balrog | { L4TA(19), 57, 2, 1 }, /* UART1 */ |
1464 | 827df9f3 | balrog | { L4TA(20), 59, 2, 1 }, /* UART2 */ |
1465 | 827df9f3 | balrog | { L4TA(21), 61, 2, 1 }, /* UART3 */ |
1466 | 827df9f3 | balrog | { L4TAO(5), 63, 2, 1 }, /* I2C1 */ |
1467 | 827df9f3 | balrog | { L4TAO(6), 65, 2, 1 }, /* I2C2 */ |
1468 | 827df9f3 | balrog | { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ |
1469 | 827df9f3 | balrog | { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ |
1470 | 827df9f3 | balrog | { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ |
1471 | 827df9f3 | balrog | { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ |
1472 | 827df9f3 | balrog | { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ |
1473 | 827df9f3 | balrog | { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ |
1474 | 827df9f3 | balrog | { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ |
1475 | 827df9f3 | balrog | { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ |
1476 | 827df9f3 | balrog | { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ |
1477 | 827df9f3 | balrog | { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ |
1478 | 827df9f3 | balrog | { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ |
1479 | 827df9f3 | balrog | { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ |
1480 | 827df9f3 | balrog | { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ |
1481 | 827df9f3 | balrog | { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ |
1482 | 827df9f3 | balrog | { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ |
1483 | 827df9f3 | balrog | { L4TA(32), 97, 2, 1 }, /* EAC */ |
1484 | 827df9f3 | balrog | { L4TA(33), 99, 2, 1 }, /* FAC */ |
1485 | 827df9f3 | balrog | { L4TA(34), 101, 2, 1 }, /* IPC */ |
1486 | 827df9f3 | balrog | { L4TA(35), 103, 2, 1 }, /* SPI1 */ |
1487 | 827df9f3 | balrog | { L4TA(36), 105, 2, 1 }, /* SPI2 */ |
1488 | 827df9f3 | balrog | { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ |
1489 | 827df9f3 | balrog | { L4TAO(10), 109, 2, 1 }, |
1490 | 827df9f3 | balrog | { L4TAO(11), 111, 2, 1 }, /* RNG */ |
1491 | 827df9f3 | balrog | { L4TAO(12), 113, 2, 1 }, /* DES3DES */ |
1492 | 827df9f3 | balrog | { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ |
1493 | 827df9f3 | balrog | { L4TA(37), 117, 2, 1 }, /* AES */ |
1494 | 827df9f3 | balrog | { L4TA(38), 119, 2, 1 }, /* PKA */ |
1495 | 827df9f3 | balrog | { -1, 121, 2, 1 }, |
1496 | 827df9f3 | balrog | { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ |
1497 | 827df9f3 | balrog | }; |
1498 | 827df9f3 | balrog | |
1499 | 827df9f3 | balrog | #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
|
1500 | 827df9f3 | balrog | #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
|
1501 | 827df9f3 | balrog | |
1502 | 827df9f3 | balrog | struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs) |
1503 | 827df9f3 | balrog | { |
1504 | 827df9f3 | balrog | int i, iomemtype;
|
1505 | b9d38e95 | Blue Swirl | struct omap_target_agent_s *ta = NULL; |
1506 | b9d38e95 | Blue Swirl | struct omap_l4_agent_info_s *info = NULL; |
1507 | 827df9f3 | balrog | |
1508 | 827df9f3 | balrog | for (i = 0; i < bus->ta_num; i ++) |
1509 | 827df9f3 | balrog | if (omap_l4_agent_info[i].ta == cs) {
|
1510 | 827df9f3 | balrog | ta = &bus->ta[i]; |
1511 | 827df9f3 | balrog | info = &omap_l4_agent_info[i]; |
1512 | 827df9f3 | balrog | break;
|
1513 | 827df9f3 | balrog | } |
1514 | 827df9f3 | balrog | if (!ta) {
|
1515 | 827df9f3 | balrog | fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
|
1516 | 827df9f3 | balrog | exit(-1);
|
1517 | 827df9f3 | balrog | } |
1518 | 827df9f3 | balrog | |
1519 | 827df9f3 | balrog | ta->bus = bus; |
1520 | 827df9f3 | balrog | ta->start = &omap_l4_region[info->region]; |
1521 | 827df9f3 | balrog | ta->regions = info->regions; |
1522 | 827df9f3 | balrog | |
1523 | 827df9f3 | balrog | ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
1524 | 827df9f3 | balrog | ta->status = 0x00000000;
|
1525 | 827df9f3 | balrog | ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ |
1526 | 827df9f3 | balrog | |
1527 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_l4ta_readfn, |
1528 | 827df9f3 | balrog | omap_l4ta_writefn, ta); |
1529 | c66fb5bc | balrog | ta->base = omap_l4_attach(ta, info->ta_region, iomemtype); |
1530 | 827df9f3 | balrog | |
1531 | 827df9f3 | balrog | return ta;
|
1532 | 827df9f3 | balrog | } |
1533 | 827df9f3 | balrog | |
1534 | c227f099 | Anthony Liguori | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
1535 | 827df9f3 | balrog | int iotype)
|
1536 | 827df9f3 | balrog | { |
1537 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
1538 | c66fb5bc | balrog | ssize_t size; |
1539 | c66fb5bc | balrog | #ifdef L4_MUX_HACK
|
1540 | c66fb5bc | balrog | int i;
|
1541 | c66fb5bc | balrog | #endif
|
1542 | 827df9f3 | balrog | |
1543 | 827df9f3 | balrog | if (region < 0 || region >= ta->regions) { |
1544 | 827df9f3 | balrog | fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
|
1545 | 827df9f3 | balrog | exit(-1);
|
1546 | 827df9f3 | balrog | } |
1547 | 827df9f3 | balrog | |
1548 | 827df9f3 | balrog | base = ta->bus->base + ta->start[region].offset; |
1549 | 827df9f3 | balrog | size = ta->start[region].size; |
1550 | c66fb5bc | balrog | if (iotype) {
|
1551 | c66fb5bc | balrog | #ifndef L4_MUX_HACK
|
1552 | 827df9f3 | balrog | cpu_register_physical_memory(base, size, iotype); |
1553 | c66fb5bc | balrog | #else
|
1554 | c66fb5bc | balrog | cpu_register_physical_memory(base, size, omap_cpu_io_entry); |
1555 | c66fb5bc | balrog | i = (base - ta->bus->base) / TARGET_PAGE_SIZE; |
1556 | c66fb5bc | balrog | for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) { |
1557 | c66fb5bc | balrog | omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
|
1558 | c66fb5bc | balrog | omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
|
1559 | c66fb5bc | balrog | omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
|
1560 | c66fb5bc | balrog | omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
|
1561 | c66fb5bc | balrog | omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
|
1562 | c66fb5bc | balrog | omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
|
1563 | c66fb5bc | balrog | omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque; |
1564 | c66fb5bc | balrog | } |
1565 | c66fb5bc | balrog | #endif
|
1566 | c66fb5bc | balrog | } |
1567 | 827df9f3 | balrog | |
1568 | 827df9f3 | balrog | return base;
|
1569 | 827df9f3 | balrog | } |
1570 | 827df9f3 | balrog | |
1571 | 827df9f3 | balrog | /* TEST-Chip-level TAP */
|
1572 | c227f099 | Anthony Liguori | static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) |
1573 | 827df9f3 | balrog | { |
1574 | 827df9f3 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1575 | 827df9f3 | balrog | |
1576 | 8da3ff18 | pbrook | switch (addr) {
|
1577 | 827df9f3 | balrog | case 0x204: /* IDCODE_reg */ |
1578 | 827df9f3 | balrog | switch (s->mpu_model) {
|
1579 | 827df9f3 | balrog | case omap2420:
|
1580 | 827df9f3 | balrog | case omap2422:
|
1581 | 827df9f3 | balrog | case omap2423:
|
1582 | 827df9f3 | balrog | return 0x5b5d902f; /* ES 2.2 */ |
1583 | 827df9f3 | balrog | case omap2430:
|
1584 | 827df9f3 | balrog | return 0x5b68a02f; /* ES 2.2 */ |
1585 | 827df9f3 | balrog | case omap3430:
|
1586 | 827df9f3 | balrog | return 0x1b7ae02f; /* ES 2 */ |
1587 | 827df9f3 | balrog | default:
|
1588 | 2ac71179 | Paul Brook | hw_error("%s: Bad mpu model\n", __FUNCTION__);
|
1589 | 827df9f3 | balrog | } |
1590 | 827df9f3 | balrog | |
1591 | 827df9f3 | balrog | case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ |
1592 | 827df9f3 | balrog | case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ |
1593 | 827df9f3 | balrog | switch (s->mpu_model) {
|
1594 | 827df9f3 | balrog | case omap2420:
|
1595 | 827df9f3 | balrog | return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ |
1596 | 827df9f3 | balrog | case omap2422:
|
1597 | 827df9f3 | balrog | return 0x000400f0; |
1598 | 827df9f3 | balrog | case omap2423:
|
1599 | 827df9f3 | balrog | return 0x000800f0; |
1600 | 827df9f3 | balrog | case omap2430:
|
1601 | 827df9f3 | balrog | return 0x000000f0; |
1602 | 827df9f3 | balrog | case omap3430:
|
1603 | 827df9f3 | balrog | return 0x000000f0; |
1604 | 827df9f3 | balrog | default:
|
1605 | 2ac71179 | Paul Brook | hw_error("%s: Bad mpu model\n", __FUNCTION__);
|
1606 | 827df9f3 | balrog | } |
1607 | 827df9f3 | balrog | |
1608 | 827df9f3 | balrog | case 0x20c: |
1609 | 827df9f3 | balrog | switch (s->mpu_model) {
|
1610 | 827df9f3 | balrog | case omap2420:
|
1611 | 827df9f3 | balrog | case omap2422:
|
1612 | 827df9f3 | balrog | case omap2423:
|
1613 | 827df9f3 | balrog | return 0xcafeb5d9; /* ES 2.2 */ |
1614 | 827df9f3 | balrog | case omap2430:
|
1615 | 827df9f3 | balrog | return 0xcafeb68a; /* ES 2.2 */ |
1616 | 827df9f3 | balrog | case omap3430:
|
1617 | 827df9f3 | balrog | return 0xcafeb7ae; /* ES 2 */ |
1618 | 827df9f3 | balrog | default:
|
1619 | 2ac71179 | Paul Brook | hw_error("%s: Bad mpu model\n", __FUNCTION__);
|
1620 | 827df9f3 | balrog | } |
1621 | 827df9f3 | balrog | |
1622 | 827df9f3 | balrog | case 0x218: /* DIE_ID_reg */ |
1623 | 827df9f3 | balrog | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
1624 | 827df9f3 | balrog | case 0x21c: /* DIE_ID_reg */ |
1625 | 827df9f3 | balrog | return 0x54 << 24; |
1626 | 827df9f3 | balrog | case 0x220: /* DIE_ID_reg */ |
1627 | 827df9f3 | balrog | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
1628 | 827df9f3 | balrog | case 0x224: /* DIE_ID_reg */ |
1629 | 827df9f3 | balrog | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
1630 | 827df9f3 | balrog | } |
1631 | 827df9f3 | balrog | |
1632 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1633 | 827df9f3 | balrog | return 0; |
1634 | 827df9f3 | balrog | } |
1635 | 827df9f3 | balrog | |
1636 | c227f099 | Anthony Liguori | static void omap_tap_write(void *opaque, target_phys_addr_t addr, |
1637 | 827df9f3 | balrog | uint32_t value) |
1638 | 827df9f3 | balrog | { |
1639 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1640 | 827df9f3 | balrog | } |
1641 | 827df9f3 | balrog | |
1642 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_tap_readfn[] = { |
1643 | 827df9f3 | balrog | omap_badwidth_read32, |
1644 | 827df9f3 | balrog | omap_badwidth_read32, |
1645 | 827df9f3 | balrog | omap_tap_read, |
1646 | 827df9f3 | balrog | }; |
1647 | 827df9f3 | balrog | |
1648 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_tap_writefn[] = { |
1649 | 827df9f3 | balrog | omap_badwidth_write32, |
1650 | 827df9f3 | balrog | omap_badwidth_write32, |
1651 | 827df9f3 | balrog | omap_tap_write, |
1652 | 827df9f3 | balrog | }; |
1653 | 827df9f3 | balrog | |
1654 | 827df9f3 | balrog | void omap_tap_init(struct omap_target_agent_s *ta, |
1655 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu)
|
1656 | 827df9f3 | balrog | { |
1657 | 1eed09cb | Avi Kivity | omap_l4_attach(ta, 0, l4_register_io_memory(
|
1658 | 827df9f3 | balrog | omap_tap_readfn, omap_tap_writefn, mpu)); |
1659 | 827df9f3 | balrog | } |
1660 | 827df9f3 | balrog | |
1661 | 827df9f3 | balrog | /* Power, Reset, and Clock Management */
|
1662 | 827df9f3 | balrog | struct omap_prcm_s {
|
1663 | 827df9f3 | balrog | qemu_irq irq[3];
|
1664 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu;
|
1665 | 827df9f3 | balrog | |
1666 | 827df9f3 | balrog | uint32_t irqst[3];
|
1667 | 827df9f3 | balrog | uint32_t irqen[3];
|
1668 | 827df9f3 | balrog | |
1669 | 827df9f3 | balrog | uint32_t sysconfig; |
1670 | 827df9f3 | balrog | uint32_t voltctrl; |
1671 | 827df9f3 | balrog | uint32_t scratch[20];
|
1672 | 827df9f3 | balrog | |
1673 | 827df9f3 | balrog | uint32_t clksrc[1];
|
1674 | 827df9f3 | balrog | uint32_t clkout[1];
|
1675 | 827df9f3 | balrog | uint32_t clkemul[1];
|
1676 | 827df9f3 | balrog | uint32_t clkpol[1];
|
1677 | 827df9f3 | balrog | uint32_t clksel[8];
|
1678 | 827df9f3 | balrog | uint32_t clken[12];
|
1679 | 827df9f3 | balrog | uint32_t clkctrl[4];
|
1680 | 827df9f3 | balrog | uint32_t clkidle[7];
|
1681 | 827df9f3 | balrog | uint32_t setuptime[2];
|
1682 | 827df9f3 | balrog | |
1683 | 827df9f3 | balrog | uint32_t wkup[3];
|
1684 | 827df9f3 | balrog | uint32_t wken[3];
|
1685 | 827df9f3 | balrog | uint32_t wkst[3];
|
1686 | 827df9f3 | balrog | uint32_t rst[4];
|
1687 | 827df9f3 | balrog | uint32_t rstctrl[1];
|
1688 | 827df9f3 | balrog | uint32_t power[4];
|
1689 | 827df9f3 | balrog | uint32_t rsttime_wkup; |
1690 | 827df9f3 | balrog | |
1691 | 827df9f3 | balrog | uint32_t ev; |
1692 | 827df9f3 | balrog | uint32_t evtime[2];
|
1693 | 51fec3cc | balrog | |
1694 | 51fec3cc | balrog | int dpll_lock, apll_lock[2]; |
1695 | 827df9f3 | balrog | }; |
1696 | 827df9f3 | balrog | |
1697 | 827df9f3 | balrog | static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) |
1698 | 827df9f3 | balrog | { |
1699 | 827df9f3 | balrog | qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); |
1700 | 827df9f3 | balrog | /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
|
1701 | 827df9f3 | balrog | } |
1702 | 827df9f3 | balrog | |
1703 | c227f099 | Anthony Liguori | static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr) |
1704 | 827df9f3 | balrog | { |
1705 | 827df9f3 | balrog | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
1706 | 51fec3cc | balrog | uint32_t ret; |
1707 | 827df9f3 | balrog | |
1708 | 8da3ff18 | pbrook | switch (addr) {
|
1709 | 827df9f3 | balrog | case 0x000: /* PRCM_REVISION */ |
1710 | 827df9f3 | balrog | return 0x10; |
1711 | 827df9f3 | balrog | |
1712 | 827df9f3 | balrog | case 0x010: /* PRCM_SYSCONFIG */ |
1713 | 827df9f3 | balrog | return s->sysconfig;
|
1714 | 827df9f3 | balrog | |
1715 | 827df9f3 | balrog | case 0x018: /* PRCM_IRQSTATUS_MPU */ |
1716 | 827df9f3 | balrog | return s->irqst[0]; |
1717 | 827df9f3 | balrog | |
1718 | 827df9f3 | balrog | case 0x01c: /* PRCM_IRQENABLE_MPU */ |
1719 | 827df9f3 | balrog | return s->irqen[0]; |
1720 | 827df9f3 | balrog | |
1721 | 827df9f3 | balrog | case 0x050: /* PRCM_VOLTCTRL */ |
1722 | 827df9f3 | balrog | return s->voltctrl;
|
1723 | 827df9f3 | balrog | case 0x054: /* PRCM_VOLTST */ |
1724 | 827df9f3 | balrog | return s->voltctrl & 3; |
1725 | 827df9f3 | balrog | |
1726 | 827df9f3 | balrog | case 0x060: /* PRCM_CLKSRC_CTRL */ |
1727 | 827df9f3 | balrog | return s->clksrc[0]; |
1728 | 827df9f3 | balrog | case 0x070: /* PRCM_CLKOUT_CTRL */ |
1729 | 827df9f3 | balrog | return s->clkout[0]; |
1730 | 827df9f3 | balrog | case 0x078: /* PRCM_CLKEMUL_CTRL */ |
1731 | 827df9f3 | balrog | return s->clkemul[0]; |
1732 | 827df9f3 | balrog | case 0x080: /* PRCM_CLKCFG_CTRL */ |
1733 | 827df9f3 | balrog | case 0x084: /* PRCM_CLKCFG_STATUS */ |
1734 | 827df9f3 | balrog | return 0; |
1735 | 827df9f3 | balrog | |
1736 | 827df9f3 | balrog | case 0x090: /* PRCM_VOLTSETUP */ |
1737 | 827df9f3 | balrog | return s->setuptime[0]; |
1738 | 827df9f3 | balrog | |
1739 | 827df9f3 | balrog | case 0x094: /* PRCM_CLKSSETUP */ |
1740 | 827df9f3 | balrog | return s->setuptime[1]; |
1741 | 827df9f3 | balrog | |
1742 | 827df9f3 | balrog | case 0x098: /* PRCM_POLCTRL */ |
1743 | 827df9f3 | balrog | return s->clkpol[0]; |
1744 | 827df9f3 | balrog | |
1745 | 827df9f3 | balrog | case 0x0b0: /* GENERAL_PURPOSE1 */ |
1746 | 827df9f3 | balrog | case 0x0b4: /* GENERAL_PURPOSE2 */ |
1747 | 827df9f3 | balrog | case 0x0b8: /* GENERAL_PURPOSE3 */ |
1748 | 827df9f3 | balrog | case 0x0bc: /* GENERAL_PURPOSE4 */ |
1749 | 827df9f3 | balrog | case 0x0c0: /* GENERAL_PURPOSE5 */ |
1750 | 827df9f3 | balrog | case 0x0c4: /* GENERAL_PURPOSE6 */ |
1751 | 827df9f3 | balrog | case 0x0c8: /* GENERAL_PURPOSE7 */ |
1752 | 827df9f3 | balrog | case 0x0cc: /* GENERAL_PURPOSE8 */ |
1753 | 827df9f3 | balrog | case 0x0d0: /* GENERAL_PURPOSE9 */ |
1754 | 827df9f3 | balrog | case 0x0d4: /* GENERAL_PURPOSE10 */ |
1755 | 827df9f3 | balrog | case 0x0d8: /* GENERAL_PURPOSE11 */ |
1756 | 827df9f3 | balrog | case 0x0dc: /* GENERAL_PURPOSE12 */ |
1757 | 827df9f3 | balrog | case 0x0e0: /* GENERAL_PURPOSE13 */ |
1758 | 827df9f3 | balrog | case 0x0e4: /* GENERAL_PURPOSE14 */ |
1759 | 827df9f3 | balrog | case 0x0e8: /* GENERAL_PURPOSE15 */ |
1760 | 827df9f3 | balrog | case 0x0ec: /* GENERAL_PURPOSE16 */ |
1761 | 827df9f3 | balrog | case 0x0f0: /* GENERAL_PURPOSE17 */ |
1762 | 827df9f3 | balrog | case 0x0f4: /* GENERAL_PURPOSE18 */ |
1763 | 827df9f3 | balrog | case 0x0f8: /* GENERAL_PURPOSE19 */ |
1764 | 827df9f3 | balrog | case 0x0fc: /* GENERAL_PURPOSE20 */ |
1765 | 8da3ff18 | pbrook | return s->scratch[(addr - 0xb0) >> 2]; |
1766 | 827df9f3 | balrog | |
1767 | 827df9f3 | balrog | case 0x140: /* CM_CLKSEL_MPU */ |
1768 | 827df9f3 | balrog | return s->clksel[0]; |
1769 | 827df9f3 | balrog | case 0x148: /* CM_CLKSTCTRL_MPU */ |
1770 | 827df9f3 | balrog | return s->clkctrl[0]; |
1771 | 827df9f3 | balrog | |
1772 | 827df9f3 | balrog | case 0x158: /* RM_RSTST_MPU */ |
1773 | 827df9f3 | balrog | return s->rst[0]; |
1774 | 827df9f3 | balrog | case 0x1c8: /* PM_WKDEP_MPU */ |
1775 | 827df9f3 | balrog | return s->wkup[0]; |
1776 | 827df9f3 | balrog | case 0x1d4: /* PM_EVGENCTRL_MPU */ |
1777 | 827df9f3 | balrog | return s->ev;
|
1778 | 827df9f3 | balrog | case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
1779 | 827df9f3 | balrog | return s->evtime[0]; |
1780 | 827df9f3 | balrog | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
1781 | 827df9f3 | balrog | return s->evtime[1]; |
1782 | 827df9f3 | balrog | case 0x1e0: /* PM_PWSTCTRL_MPU */ |
1783 | 827df9f3 | balrog | return s->power[0]; |
1784 | 827df9f3 | balrog | case 0x1e4: /* PM_PWSTST_MPU */ |
1785 | 827df9f3 | balrog | return 0; |
1786 | 827df9f3 | balrog | |
1787 | 827df9f3 | balrog | case 0x200: /* CM_FCLKEN1_CORE */ |
1788 | 827df9f3 | balrog | return s->clken[0]; |
1789 | 827df9f3 | balrog | case 0x204: /* CM_FCLKEN2_CORE */ |
1790 | 827df9f3 | balrog | return s->clken[1]; |
1791 | 827df9f3 | balrog | case 0x210: /* CM_ICLKEN1_CORE */ |
1792 | 827df9f3 | balrog | return s->clken[2]; |
1793 | 827df9f3 | balrog | case 0x214: /* CM_ICLKEN2_CORE */ |
1794 | 827df9f3 | balrog | return s->clken[3]; |
1795 | 827df9f3 | balrog | case 0x21c: /* CM_ICLKEN4_CORE */ |
1796 | 827df9f3 | balrog | return s->clken[4]; |
1797 | 827df9f3 | balrog | |
1798 | 827df9f3 | balrog | case 0x220: /* CM_IDLEST1_CORE */ |
1799 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
1800 | 827df9f3 | balrog | return 0x7ffffff9; |
1801 | 827df9f3 | balrog | case 0x224: /* CM_IDLEST2_CORE */ |
1802 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
1803 | 827df9f3 | balrog | return 0x00000007; |
1804 | 827df9f3 | balrog | case 0x22c: /* CM_IDLEST4_CORE */ |
1805 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
1806 | 827df9f3 | balrog | return 0x0000001f; |
1807 | 827df9f3 | balrog | |
1808 | 827df9f3 | balrog | case 0x230: /* CM_AUTOIDLE1_CORE */ |
1809 | 827df9f3 | balrog | return s->clkidle[0]; |
1810 | 827df9f3 | balrog | case 0x234: /* CM_AUTOIDLE2_CORE */ |
1811 | 827df9f3 | balrog | return s->clkidle[1]; |
1812 | 827df9f3 | balrog | case 0x238: /* CM_AUTOIDLE3_CORE */ |
1813 | 827df9f3 | balrog | return s->clkidle[2]; |
1814 | 827df9f3 | balrog | case 0x23c: /* CM_AUTOIDLE4_CORE */ |
1815 | 827df9f3 | balrog | return s->clkidle[3]; |
1816 | 827df9f3 | balrog | |
1817 | 827df9f3 | balrog | case 0x240: /* CM_CLKSEL1_CORE */ |
1818 | 827df9f3 | balrog | return s->clksel[1]; |
1819 | 827df9f3 | balrog | case 0x244: /* CM_CLKSEL2_CORE */ |
1820 | 827df9f3 | balrog | return s->clksel[2]; |
1821 | 827df9f3 | balrog | |
1822 | 827df9f3 | balrog | case 0x248: /* CM_CLKSTCTRL_CORE */ |
1823 | 827df9f3 | balrog | return s->clkctrl[1]; |
1824 | 827df9f3 | balrog | |
1825 | 827df9f3 | balrog | case 0x2a0: /* PM_WKEN1_CORE */ |
1826 | 827df9f3 | balrog | return s->wken[0]; |
1827 | 827df9f3 | balrog | case 0x2a4: /* PM_WKEN2_CORE */ |
1828 | 827df9f3 | balrog | return s->wken[1]; |
1829 | 827df9f3 | balrog | |
1830 | 827df9f3 | balrog | case 0x2b0: /* PM_WKST1_CORE */ |
1831 | 827df9f3 | balrog | return s->wkst[0]; |
1832 | 827df9f3 | balrog | case 0x2b4: /* PM_WKST2_CORE */ |
1833 | 827df9f3 | balrog | return s->wkst[1]; |
1834 | 827df9f3 | balrog | case 0x2c8: /* PM_WKDEP_CORE */ |
1835 | 827df9f3 | balrog | return 0x1e; |
1836 | 827df9f3 | balrog | |
1837 | 827df9f3 | balrog | case 0x2e0: /* PM_PWSTCTRL_CORE */ |
1838 | 827df9f3 | balrog | return s->power[1]; |
1839 | 827df9f3 | balrog | case 0x2e4: /* PM_PWSTST_CORE */ |
1840 | 827df9f3 | balrog | return 0x000030 | (s->power[1] & 0xfc00); |
1841 | 827df9f3 | balrog | |
1842 | 827df9f3 | balrog | case 0x300: /* CM_FCLKEN_GFX */ |
1843 | 827df9f3 | balrog | return s->clken[5]; |
1844 | 827df9f3 | balrog | case 0x310: /* CM_ICLKEN_GFX */ |
1845 | 827df9f3 | balrog | return s->clken[6]; |
1846 | 827df9f3 | balrog | case 0x320: /* CM_IDLEST_GFX */ |
1847 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
1848 | 827df9f3 | balrog | return 0x00000001; |
1849 | 827df9f3 | balrog | case 0x340: /* CM_CLKSEL_GFX */ |
1850 | 827df9f3 | balrog | return s->clksel[3]; |
1851 | 827df9f3 | balrog | case 0x348: /* CM_CLKSTCTRL_GFX */ |
1852 | 827df9f3 | balrog | return s->clkctrl[2]; |
1853 | 827df9f3 | balrog | case 0x350: /* RM_RSTCTRL_GFX */ |
1854 | 827df9f3 | balrog | return s->rstctrl[0]; |
1855 | 827df9f3 | balrog | case 0x358: /* RM_RSTST_GFX */ |
1856 | 827df9f3 | balrog | return s->rst[1]; |
1857 | 827df9f3 | balrog | case 0x3c8: /* PM_WKDEP_GFX */ |
1858 | 827df9f3 | balrog | return s->wkup[1]; |
1859 | 827df9f3 | balrog | |
1860 | 827df9f3 | balrog | case 0x3e0: /* PM_PWSTCTRL_GFX */ |
1861 | 827df9f3 | balrog | return s->power[2]; |
1862 | 827df9f3 | balrog | case 0x3e4: /* PM_PWSTST_GFX */ |
1863 | 827df9f3 | balrog | return s->power[2] & 3; |
1864 | 827df9f3 | balrog | |
1865 | 827df9f3 | balrog | case 0x400: /* CM_FCLKEN_WKUP */ |
1866 | 827df9f3 | balrog | return s->clken[7]; |
1867 | 827df9f3 | balrog | case 0x410: /* CM_ICLKEN_WKUP */ |
1868 | 827df9f3 | balrog | return s->clken[8]; |
1869 | 827df9f3 | balrog | case 0x420: /* CM_IDLEST_WKUP */ |
1870 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
1871 | 827df9f3 | balrog | return 0x0000003f; |
1872 | 827df9f3 | balrog | case 0x430: /* CM_AUTOIDLE_WKUP */ |
1873 | 827df9f3 | balrog | return s->clkidle[4]; |
1874 | 827df9f3 | balrog | case 0x440: /* CM_CLKSEL_WKUP */ |
1875 | 827df9f3 | balrog | return s->clksel[4]; |
1876 | 827df9f3 | balrog | case 0x450: /* RM_RSTCTRL_WKUP */ |
1877 | 827df9f3 | balrog | return 0; |
1878 | 827df9f3 | balrog | case 0x454: /* RM_RSTTIME_WKUP */ |
1879 | 827df9f3 | balrog | return s->rsttime_wkup;
|
1880 | 827df9f3 | balrog | case 0x458: /* RM_RSTST_WKUP */ |
1881 | 827df9f3 | balrog | return s->rst[2]; |
1882 | 827df9f3 | balrog | case 0x4a0: /* PM_WKEN_WKUP */ |
1883 | 827df9f3 | balrog | return s->wken[2]; |
1884 | 827df9f3 | balrog | case 0x4b0: /* PM_WKST_WKUP */ |
1885 | 827df9f3 | balrog | return s->wkst[2]; |
1886 | 827df9f3 | balrog | |
1887 | 827df9f3 | balrog | case 0x500: /* CM_CLKEN_PLL */ |
1888 | 827df9f3 | balrog | return s->clken[9]; |
1889 | 827df9f3 | balrog | case 0x520: /* CM_IDLEST_CKGEN */ |
1890 | 51fec3cc | balrog | ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); |
1891 | 827df9f3 | balrog | if (!(s->clksel[6] & 3)) |
1892 | 51fec3cc | balrog | /* Core uses 32-kHz clock */
|
1893 | 51fec3cc | balrog | ret |= 3 << 0; |
1894 | 51fec3cc | balrog | else if (!s->dpll_lock) |
1895 | 51fec3cc | balrog | /* DPLL not locked, core uses ref_clk */
|
1896 | 51fec3cc | balrog | ret |= 1 << 0; |
1897 | 51fec3cc | balrog | else
|
1898 | 51fec3cc | balrog | /* Core uses DPLL */
|
1899 | 51fec3cc | balrog | ret |= 2 << 0; |
1900 | 51fec3cc | balrog | return ret;
|
1901 | 827df9f3 | balrog | case 0x530: /* CM_AUTOIDLE_PLL */ |
1902 | 827df9f3 | balrog | return s->clkidle[5]; |
1903 | 827df9f3 | balrog | case 0x540: /* CM_CLKSEL1_PLL */ |
1904 | 827df9f3 | balrog | return s->clksel[5]; |
1905 | 827df9f3 | balrog | case 0x544: /* CM_CLKSEL2_PLL */ |
1906 | 827df9f3 | balrog | return s->clksel[6]; |
1907 | 827df9f3 | balrog | |
1908 | 827df9f3 | balrog | case 0x800: /* CM_FCLKEN_DSP */ |
1909 | 827df9f3 | balrog | return s->clken[10]; |
1910 | 827df9f3 | balrog | case 0x810: /* CM_ICLKEN_DSP */ |
1911 | 827df9f3 | balrog | return s->clken[11]; |
1912 | 827df9f3 | balrog | case 0x820: /* CM_IDLEST_DSP */ |
1913 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
1914 | 827df9f3 | balrog | return 0x00000103; |
1915 | 827df9f3 | balrog | case 0x830: /* CM_AUTOIDLE_DSP */ |
1916 | 827df9f3 | balrog | return s->clkidle[6]; |
1917 | 827df9f3 | balrog | case 0x840: /* CM_CLKSEL_DSP */ |
1918 | 827df9f3 | balrog | return s->clksel[7]; |
1919 | 827df9f3 | balrog | case 0x848: /* CM_CLKSTCTRL_DSP */ |
1920 | 827df9f3 | balrog | return s->clkctrl[3]; |
1921 | 827df9f3 | balrog | case 0x850: /* RM_RSTCTRL_DSP */ |
1922 | 827df9f3 | balrog | return 0; |
1923 | 827df9f3 | balrog | case 0x858: /* RM_RSTST_DSP */ |
1924 | 827df9f3 | balrog | return s->rst[3]; |
1925 | 827df9f3 | balrog | case 0x8c8: /* PM_WKDEP_DSP */ |
1926 | 827df9f3 | balrog | return s->wkup[2]; |
1927 | 827df9f3 | balrog | case 0x8e0: /* PM_PWSTCTRL_DSP */ |
1928 | 827df9f3 | balrog | return s->power[3]; |
1929 | 827df9f3 | balrog | case 0x8e4: /* PM_PWSTST_DSP */ |
1930 | 827df9f3 | balrog | return 0x008030 | (s->power[3] & 0x3003); |
1931 | 827df9f3 | balrog | |
1932 | 827df9f3 | balrog | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
1933 | 827df9f3 | balrog | return s->irqst[1]; |
1934 | 827df9f3 | balrog | case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
1935 | 827df9f3 | balrog | return s->irqen[1]; |
1936 | 827df9f3 | balrog | |
1937 | 827df9f3 | balrog | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
1938 | 827df9f3 | balrog | return s->irqst[2]; |
1939 | 827df9f3 | balrog | case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
1940 | 827df9f3 | balrog | return s->irqen[2]; |
1941 | 827df9f3 | balrog | } |
1942 | 827df9f3 | balrog | |
1943 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1944 | 827df9f3 | balrog | return 0; |
1945 | 827df9f3 | balrog | } |
1946 | 827df9f3 | balrog | |
1947 | 51fec3cc | balrog | static void omap_prcm_apll_update(struct omap_prcm_s *s) |
1948 | 51fec3cc | balrog | { |
1949 | 51fec3cc | balrog | int mode[2]; |
1950 | 51fec3cc | balrog | |
1951 | 51fec3cc | balrog | mode[0] = (s->clken[9] >> 6) & 3; |
1952 | 51fec3cc | balrog | s->apll_lock[0] = (mode[0] == 3); |
1953 | 51fec3cc | balrog | mode[1] = (s->clken[9] >> 2) & 3; |
1954 | 51fec3cc | balrog | s->apll_lock[1] = (mode[1] == 3); |
1955 | 51fec3cc | balrog | /* TODO: update clocks */
|
1956 | 51fec3cc | balrog | |
1957 | 16d55035 | Blue Swirl | if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2) |
1958 | 51fec3cc | balrog | fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
|
1959 | 51fec3cc | balrog | __FUNCTION__); |
1960 | 51fec3cc | balrog | } |
1961 | 51fec3cc | balrog | |
1962 | 51fec3cc | balrog | static void omap_prcm_dpll_update(struct omap_prcm_s *s) |
1963 | 51fec3cc | balrog | { |
1964 | 51fec3cc | balrog | omap_clk dpll = omap_findclk(s->mpu, "dpll");
|
1965 | 51fec3cc | balrog | omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
|
1966 | 51fec3cc | balrog | omap_clk core = omap_findclk(s->mpu, "core_clk");
|
1967 | 51fec3cc | balrog | int mode = (s->clken[9] >> 0) & 3; |
1968 | 51fec3cc | balrog | int mult, div;
|
1969 | 51fec3cc | balrog | |
1970 | 51fec3cc | balrog | mult = (s->clksel[5] >> 12) & 0x3ff; |
1971 | 51fec3cc | balrog | div = (s->clksel[5] >> 8) & 0xf; |
1972 | 51fec3cc | balrog | if (mult == 0 || mult == 1) |
1973 | 51fec3cc | balrog | mode = 1; /* Bypass */ |
1974 | 51fec3cc | balrog | |
1975 | 51fec3cc | balrog | s->dpll_lock = 0;
|
1976 | 51fec3cc | balrog | switch (mode) {
|
1977 | 51fec3cc | balrog | case 0: |
1978 | 51fec3cc | balrog | fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
|
1979 | 51fec3cc | balrog | break;
|
1980 | 51fec3cc | balrog | case 1: /* Low-power bypass mode (Default) */ |
1981 | 51fec3cc | balrog | case 2: /* Fast-relock bypass mode */ |
1982 | 51fec3cc | balrog | omap_clk_setrate(dpll, 1, 1); |
1983 | 51fec3cc | balrog | omap_clk_setrate(dpll_x2, 1, 1); |
1984 | 51fec3cc | balrog | break;
|
1985 | 51fec3cc | balrog | case 3: /* Lock mode */ |
1986 | 51fec3cc | balrog | s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ |
1987 | 51fec3cc | balrog | |
1988 | 51fec3cc | balrog | omap_clk_setrate(dpll, div + 1, mult);
|
1989 | 51fec3cc | balrog | omap_clk_setrate(dpll_x2, div + 1, mult * 2); |
1990 | 51fec3cc | balrog | break;
|
1991 | 51fec3cc | balrog | } |
1992 | 51fec3cc | balrog | |
1993 | 51fec3cc | balrog | switch ((s->clksel[6] >> 0) & 3) { |
1994 | 51fec3cc | balrog | case 0: |
1995 | 51fec3cc | balrog | omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
|
1996 | 51fec3cc | balrog | break;
|
1997 | 51fec3cc | balrog | case 1: |
1998 | 51fec3cc | balrog | omap_clk_reparent(core, dpll); |
1999 | 51fec3cc | balrog | break;
|
2000 | 51fec3cc | balrog | case 2: |
2001 | 51fec3cc | balrog | /* Default */
|
2002 | 51fec3cc | balrog | omap_clk_reparent(core, dpll_x2); |
2003 | 51fec3cc | balrog | break;
|
2004 | 51fec3cc | balrog | case 3: |
2005 | 51fec3cc | balrog | fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
|
2006 | 51fec3cc | balrog | break;
|
2007 | 51fec3cc | balrog | } |
2008 | 51fec3cc | balrog | } |
2009 | 51fec3cc | balrog | |
2010 | c227f099 | Anthony Liguori | static void omap_prcm_write(void *opaque, target_phys_addr_t addr, |
2011 | 827df9f3 | balrog | uint32_t value) |
2012 | 827df9f3 | balrog | { |
2013 | 827df9f3 | balrog | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
2014 | 827df9f3 | balrog | |
2015 | 8da3ff18 | pbrook | switch (addr) {
|
2016 | 827df9f3 | balrog | case 0x000: /* PRCM_REVISION */ |
2017 | 827df9f3 | balrog | case 0x054: /* PRCM_VOLTST */ |
2018 | 827df9f3 | balrog | case 0x084: /* PRCM_CLKCFG_STATUS */ |
2019 | 827df9f3 | balrog | case 0x1e4: /* PM_PWSTST_MPU */ |
2020 | 827df9f3 | balrog | case 0x220: /* CM_IDLEST1_CORE */ |
2021 | 827df9f3 | balrog | case 0x224: /* CM_IDLEST2_CORE */ |
2022 | 827df9f3 | balrog | case 0x22c: /* CM_IDLEST4_CORE */ |
2023 | 827df9f3 | balrog | case 0x2c8: /* PM_WKDEP_CORE */ |
2024 | 827df9f3 | balrog | case 0x2e4: /* PM_PWSTST_CORE */ |
2025 | 827df9f3 | balrog | case 0x320: /* CM_IDLEST_GFX */ |
2026 | 827df9f3 | balrog | case 0x3e4: /* PM_PWSTST_GFX */ |
2027 | 827df9f3 | balrog | case 0x420: /* CM_IDLEST_WKUP */ |
2028 | 827df9f3 | balrog | case 0x520: /* CM_IDLEST_CKGEN */ |
2029 | 827df9f3 | balrog | case 0x820: /* CM_IDLEST_DSP */ |
2030 | 827df9f3 | balrog | case 0x8e4: /* PM_PWSTST_DSP */ |
2031 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
2032 | 827df9f3 | balrog | return;
|
2033 | 827df9f3 | balrog | |
2034 | 827df9f3 | balrog | case 0x010: /* PRCM_SYSCONFIG */ |
2035 | 827df9f3 | balrog | s->sysconfig = value & 1;
|
2036 | 827df9f3 | balrog | break;
|
2037 | 827df9f3 | balrog | |
2038 | 827df9f3 | balrog | case 0x018: /* PRCM_IRQSTATUS_MPU */ |
2039 | 827df9f3 | balrog | s->irqst[0] &= ~value;
|
2040 | 827df9f3 | balrog | omap_prcm_int_update(s, 0);
|
2041 | 827df9f3 | balrog | break;
|
2042 | 827df9f3 | balrog | case 0x01c: /* PRCM_IRQENABLE_MPU */ |
2043 | 827df9f3 | balrog | s->irqen[0] = value & 0x3f; |
2044 | 827df9f3 | balrog | omap_prcm_int_update(s, 0);
|
2045 | 827df9f3 | balrog | break;
|
2046 | 827df9f3 | balrog | |
2047 | 827df9f3 | balrog | case 0x050: /* PRCM_VOLTCTRL */ |
2048 | 827df9f3 | balrog | s->voltctrl = value & 0xf1c3;
|
2049 | 827df9f3 | balrog | break;
|
2050 | 827df9f3 | balrog | |
2051 | 827df9f3 | balrog | case 0x060: /* PRCM_CLKSRC_CTRL */ |
2052 | 827df9f3 | balrog | s->clksrc[0] = value & 0xdb; |
2053 | 827df9f3 | balrog | /* TODO update clocks */
|
2054 | 827df9f3 | balrog | break;
|
2055 | 827df9f3 | balrog | |
2056 | 827df9f3 | balrog | case 0x070: /* PRCM_CLKOUT_CTRL */ |
2057 | 827df9f3 | balrog | s->clkout[0] = value & 0xbbbb; |
2058 | 827df9f3 | balrog | /* TODO update clocks */
|
2059 | 827df9f3 | balrog | break;
|
2060 | 827df9f3 | balrog | |
2061 | 827df9f3 | balrog | case 0x078: /* PRCM_CLKEMUL_CTRL */ |
2062 | 827df9f3 | balrog | s->clkemul[0] = value & 1; |
2063 | 827df9f3 | balrog | /* TODO update clocks */
|
2064 | 827df9f3 | balrog | break;
|
2065 | 827df9f3 | balrog | |
2066 | 827df9f3 | balrog | case 0x080: /* PRCM_CLKCFG_CTRL */ |
2067 | 827df9f3 | balrog | break;
|
2068 | 827df9f3 | balrog | |
2069 | 827df9f3 | balrog | case 0x090: /* PRCM_VOLTSETUP */ |
2070 | 827df9f3 | balrog | s->setuptime[0] = value & 0xffff; |
2071 | 827df9f3 | balrog | break;
|
2072 | 827df9f3 | balrog | case 0x094: /* PRCM_CLKSSETUP */ |
2073 | 827df9f3 | balrog | s->setuptime[1] = value & 0xffff; |
2074 | 827df9f3 | balrog | break;
|
2075 | 827df9f3 | balrog | |
2076 | 827df9f3 | balrog | case 0x098: /* PRCM_POLCTRL */ |
2077 | 827df9f3 | balrog | s->clkpol[0] = value & 0x701; |
2078 | 827df9f3 | balrog | break;
|
2079 | 827df9f3 | balrog | |
2080 | 827df9f3 | balrog | case 0x0b0: /* GENERAL_PURPOSE1 */ |
2081 | 827df9f3 | balrog | case 0x0b4: /* GENERAL_PURPOSE2 */ |
2082 | 827df9f3 | balrog | case 0x0b8: /* GENERAL_PURPOSE3 */ |
2083 | 827df9f3 | balrog | case 0x0bc: /* GENERAL_PURPOSE4 */ |
2084 | 827df9f3 | balrog | case 0x0c0: /* GENERAL_PURPOSE5 */ |
2085 | 827df9f3 | balrog | case 0x0c4: /* GENERAL_PURPOSE6 */ |
2086 | 827df9f3 | balrog | case 0x0c8: /* GENERAL_PURPOSE7 */ |
2087 | 827df9f3 | balrog | case 0x0cc: /* GENERAL_PURPOSE8 */ |
2088 | 827df9f3 | balrog | case 0x0d0: /* GENERAL_PURPOSE9 */ |
2089 | 827df9f3 | balrog | case 0x0d4: /* GENERAL_PURPOSE10 */ |
2090 | 827df9f3 | balrog | case 0x0d8: /* GENERAL_PURPOSE11 */ |
2091 | 827df9f3 | balrog | case 0x0dc: /* GENERAL_PURPOSE12 */ |
2092 | 827df9f3 | balrog | case 0x0e0: /* GENERAL_PURPOSE13 */ |
2093 | 827df9f3 | balrog | case 0x0e4: /* GENERAL_PURPOSE14 */ |
2094 | 827df9f3 | balrog | case 0x0e8: /* GENERAL_PURPOSE15 */ |
2095 | 827df9f3 | balrog | case 0x0ec: /* GENERAL_PURPOSE16 */ |
2096 | 827df9f3 | balrog | case 0x0f0: /* GENERAL_PURPOSE17 */ |
2097 | 827df9f3 | balrog | case 0x0f4: /* GENERAL_PURPOSE18 */ |
2098 | 827df9f3 | balrog | case 0x0f8: /* GENERAL_PURPOSE19 */ |
2099 | 827df9f3 | balrog | case 0x0fc: /* GENERAL_PURPOSE20 */ |
2100 | 8da3ff18 | pbrook | s->scratch[(addr - 0xb0) >> 2] = value; |
2101 | 827df9f3 | balrog | break;
|
2102 | 827df9f3 | balrog | |
2103 | 827df9f3 | balrog | case 0x140: /* CM_CLKSEL_MPU */ |
2104 | 827df9f3 | balrog | s->clksel[0] = value & 0x1f; |
2105 | 827df9f3 | balrog | /* TODO update clocks */
|
2106 | 827df9f3 | balrog | break;
|
2107 | 827df9f3 | balrog | case 0x148: /* CM_CLKSTCTRL_MPU */ |
2108 | 827df9f3 | balrog | s->clkctrl[0] = value & 0x1f; |
2109 | 827df9f3 | balrog | break;
|
2110 | 827df9f3 | balrog | |
2111 | 827df9f3 | balrog | case 0x158: /* RM_RSTST_MPU */ |
2112 | 827df9f3 | balrog | s->rst[0] &= ~value;
|
2113 | 827df9f3 | balrog | break;
|
2114 | 827df9f3 | balrog | case 0x1c8: /* PM_WKDEP_MPU */ |
2115 | 827df9f3 | balrog | s->wkup[0] = value & 0x15; |
2116 | 827df9f3 | balrog | break;
|
2117 | 827df9f3 | balrog | |
2118 | 827df9f3 | balrog | case 0x1d4: /* PM_EVGENCTRL_MPU */ |
2119 | 827df9f3 | balrog | s->ev = value & 0x1f;
|
2120 | 827df9f3 | balrog | break;
|
2121 | 827df9f3 | balrog | case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
2122 | 827df9f3 | balrog | s->evtime[0] = value;
|
2123 | 827df9f3 | balrog | break;
|
2124 | 827df9f3 | balrog | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
2125 | 827df9f3 | balrog | s->evtime[1] = value;
|
2126 | 827df9f3 | balrog | break;
|
2127 | 827df9f3 | balrog | |
2128 | 827df9f3 | balrog | case 0x1e0: /* PM_PWSTCTRL_MPU */ |
2129 | 827df9f3 | balrog | s->power[0] = value & 0xc0f; |
2130 | 827df9f3 | balrog | break;
|
2131 | 827df9f3 | balrog | |
2132 | 827df9f3 | balrog | case 0x200: /* CM_FCLKEN1_CORE */ |
2133 | 827df9f3 | balrog | s->clken[0] = value & 0xbfffffff; |
2134 | 827df9f3 | balrog | /* TODO update clocks */
|
2135 | 99570a40 | balrog | /* The EN_EAC bit only gets/puts func_96m_clk. */
|
2136 | 827df9f3 | balrog | break;
|
2137 | 827df9f3 | balrog | case 0x204: /* CM_FCLKEN2_CORE */ |
2138 | 827df9f3 | balrog | s->clken[1] = value & 0x00000007; |
2139 | 827df9f3 | balrog | /* TODO update clocks */
|
2140 | 827df9f3 | balrog | break;
|
2141 | 827df9f3 | balrog | case 0x210: /* CM_ICLKEN1_CORE */ |
2142 | 827df9f3 | balrog | s->clken[2] = value & 0xfffffff9; |
2143 | 827df9f3 | balrog | /* TODO update clocks */
|
2144 | 99570a40 | balrog | /* The EN_EAC bit only gets/puts core_l4_iclk. */
|
2145 | 827df9f3 | balrog | break;
|
2146 | 827df9f3 | balrog | case 0x214: /* CM_ICLKEN2_CORE */ |
2147 | 827df9f3 | balrog | s->clken[3] = value & 0x00000007; |
2148 | 827df9f3 | balrog | /* TODO update clocks */
|
2149 | 827df9f3 | balrog | break;
|
2150 | 827df9f3 | balrog | case 0x21c: /* CM_ICLKEN4_CORE */ |
2151 | 827df9f3 | balrog | s->clken[4] = value & 0x0000001f; |
2152 | 827df9f3 | balrog | /* TODO update clocks */
|
2153 | 827df9f3 | balrog | break;
|
2154 | 827df9f3 | balrog | |
2155 | 827df9f3 | balrog | case 0x230: /* CM_AUTOIDLE1_CORE */ |
2156 | 827df9f3 | balrog | s->clkidle[0] = value & 0xfffffff9; |
2157 | 827df9f3 | balrog | /* TODO update clocks */
|
2158 | 827df9f3 | balrog | break;
|
2159 | 827df9f3 | balrog | case 0x234: /* CM_AUTOIDLE2_CORE */ |
2160 | 827df9f3 | balrog | s->clkidle[1] = value & 0x00000007; |
2161 | 827df9f3 | balrog | /* TODO update clocks */
|
2162 | 827df9f3 | balrog | break;
|
2163 | 827df9f3 | balrog | case 0x238: /* CM_AUTOIDLE3_CORE */ |
2164 | 827df9f3 | balrog | s->clkidle[2] = value & 0x00000007; |
2165 | 827df9f3 | balrog | /* TODO update clocks */
|
2166 | 827df9f3 | balrog | break;
|
2167 | 827df9f3 | balrog | case 0x23c: /* CM_AUTOIDLE4_CORE */ |
2168 | 827df9f3 | balrog | s->clkidle[3] = value & 0x0000001f; |
2169 | 827df9f3 | balrog | /* TODO update clocks */
|
2170 | 827df9f3 | balrog | break;
|
2171 | 827df9f3 | balrog | |
2172 | 827df9f3 | balrog | case 0x240: /* CM_CLKSEL1_CORE */ |
2173 | 827df9f3 | balrog | s->clksel[1] = value & 0x0fffbf7f; |
2174 | 827df9f3 | balrog | /* TODO update clocks */
|
2175 | 827df9f3 | balrog | break;
|
2176 | 827df9f3 | balrog | |
2177 | 827df9f3 | balrog | case 0x244: /* CM_CLKSEL2_CORE */ |
2178 | 827df9f3 | balrog | s->clksel[2] = value & 0x00fffffc; |
2179 | 827df9f3 | balrog | /* TODO update clocks */
|
2180 | 827df9f3 | balrog | break;
|
2181 | 827df9f3 | balrog | |
2182 | 827df9f3 | balrog | case 0x248: /* CM_CLKSTCTRL_CORE */ |
2183 | 827df9f3 | balrog | s->clkctrl[1] = value & 0x7; |
2184 | 827df9f3 | balrog | break;
|
2185 | 827df9f3 | balrog | |
2186 | 827df9f3 | balrog | case 0x2a0: /* PM_WKEN1_CORE */ |
2187 | 827df9f3 | balrog | s->wken[0] = value & 0x04667ff8; |
2188 | 827df9f3 | balrog | break;
|
2189 | 827df9f3 | balrog | case 0x2a4: /* PM_WKEN2_CORE */ |
2190 | 827df9f3 | balrog | s->wken[1] = value & 0x00000005; |
2191 | 827df9f3 | balrog | break;
|
2192 | 827df9f3 | balrog | |
2193 | 827df9f3 | balrog | case 0x2b0: /* PM_WKST1_CORE */ |
2194 | 827df9f3 | balrog | s->wkst[0] &= ~value;
|
2195 | 827df9f3 | balrog | break;
|
2196 | 827df9f3 | balrog | case 0x2b4: /* PM_WKST2_CORE */ |
2197 | 827df9f3 | balrog | s->wkst[1] &= ~value;
|
2198 | 827df9f3 | balrog | break;
|
2199 | 827df9f3 | balrog | |
2200 | 827df9f3 | balrog | case 0x2e0: /* PM_PWSTCTRL_CORE */ |
2201 | 827df9f3 | balrog | s->power[1] = (value & 0x00fc3f) | (1 << 2); |
2202 | 827df9f3 | balrog | break;
|
2203 | 827df9f3 | balrog | |
2204 | 827df9f3 | balrog | case 0x300: /* CM_FCLKEN_GFX */ |
2205 | 827df9f3 | balrog | s->clken[5] = value & 6; |
2206 | 827df9f3 | balrog | /* TODO update clocks */
|
2207 | 827df9f3 | balrog | break;
|
2208 | 827df9f3 | balrog | case 0x310: /* CM_ICLKEN_GFX */ |
2209 | 827df9f3 | balrog | s->clken[6] = value & 1; |
2210 | 827df9f3 | balrog | /* TODO update clocks */
|
2211 | 827df9f3 | balrog | break;
|
2212 | 827df9f3 | balrog | case 0x340: /* CM_CLKSEL_GFX */ |
2213 | 827df9f3 | balrog | s->clksel[3] = value & 7; |
2214 | 827df9f3 | balrog | /* TODO update clocks */
|
2215 | 827df9f3 | balrog | break;
|
2216 | 827df9f3 | balrog | case 0x348: /* CM_CLKSTCTRL_GFX */ |
2217 | 827df9f3 | balrog | s->clkctrl[2] = value & 1; |
2218 | 827df9f3 | balrog | break;
|
2219 | 827df9f3 | balrog | case 0x350: /* RM_RSTCTRL_GFX */ |
2220 | 827df9f3 | balrog | s->rstctrl[0] = value & 1; |
2221 | 827df9f3 | balrog | /* TODO: reset */
|
2222 | 827df9f3 | balrog | break;
|
2223 | 827df9f3 | balrog | case 0x358: /* RM_RSTST_GFX */ |
2224 | 827df9f3 | balrog | s->rst[1] &= ~value;
|
2225 | 827df9f3 | balrog | break;
|
2226 | 827df9f3 | balrog | case 0x3c8: /* PM_WKDEP_GFX */ |
2227 | 827df9f3 | balrog | s->wkup[1] = value & 0x13; |
2228 | 827df9f3 | balrog | break;
|
2229 | 827df9f3 | balrog | case 0x3e0: /* PM_PWSTCTRL_GFX */ |
2230 | 827df9f3 | balrog | s->power[2] = (value & 0x00c0f) | (3 << 2); |
2231 | 827df9f3 | balrog | break;
|
2232 | 827df9f3 | balrog | |
2233 | 827df9f3 | balrog | case 0x400: /* CM_FCLKEN_WKUP */ |
2234 | 827df9f3 | balrog | s->clken[7] = value & 0xd; |
2235 | 827df9f3 | balrog | /* TODO update clocks */
|
2236 | 827df9f3 | balrog | break;
|
2237 | 827df9f3 | balrog | case 0x410: /* CM_ICLKEN_WKUP */ |
2238 | 827df9f3 | balrog | s->clken[8] = value & 0x3f; |
2239 | 827df9f3 | balrog | /* TODO update clocks */
|
2240 | 827df9f3 | balrog | break;
|
2241 | 827df9f3 | balrog | case 0x430: /* CM_AUTOIDLE_WKUP */ |
2242 | 827df9f3 | balrog | s->clkidle[4] = value & 0x0000003f; |
2243 | 827df9f3 | balrog | /* TODO update clocks */
|
2244 | 827df9f3 | balrog | break;
|
2245 | 827df9f3 | balrog | case 0x440: /* CM_CLKSEL_WKUP */ |
2246 | 827df9f3 | balrog | s->clksel[4] = value & 3; |
2247 | 827df9f3 | balrog | /* TODO update clocks */
|
2248 | 827df9f3 | balrog | break;
|
2249 | 827df9f3 | balrog | case 0x450: /* RM_RSTCTRL_WKUP */ |
2250 | 827df9f3 | balrog | /* TODO: reset */
|
2251 | 827df9f3 | balrog | if (value & 2) |
2252 | 827df9f3 | balrog | qemu_system_reset_request(); |
2253 | 827df9f3 | balrog | break;
|
2254 | 827df9f3 | balrog | case 0x454: /* RM_RSTTIME_WKUP */ |
2255 | 827df9f3 | balrog | s->rsttime_wkup = value & 0x1fff;
|
2256 | 827df9f3 | balrog | break;
|
2257 | 827df9f3 | balrog | case 0x458: /* RM_RSTST_WKUP */ |
2258 | 827df9f3 | balrog | s->rst[2] &= ~value;
|
2259 | 827df9f3 | balrog | break;
|
2260 | 827df9f3 | balrog | case 0x4a0: /* PM_WKEN_WKUP */ |
2261 | 827df9f3 | balrog | s->wken[2] = value & 0x00000005; |
2262 | 827df9f3 | balrog | break;
|
2263 | 827df9f3 | balrog | case 0x4b0: /* PM_WKST_WKUP */ |
2264 | 827df9f3 | balrog | s->wkst[2] &= ~value;
|
2265 | 827df9f3 | balrog | break;
|
2266 | 827df9f3 | balrog | |
2267 | 827df9f3 | balrog | case 0x500: /* CM_CLKEN_PLL */ |
2268 | 51fec3cc | balrog | if (value & 0xffffff30) |
2269 | 51fec3cc | balrog | fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
|
2270 | 51fec3cc | balrog | "future compatiblity\n", __FUNCTION__);
|
2271 | 51fec3cc | balrog | if ((s->clken[9] ^ value) & 0xcc) { |
2272 | 51fec3cc | balrog | s->clken[9] &= ~0xcc; |
2273 | 51fec3cc | balrog | s->clken[9] |= value & 0xcc; |
2274 | 51fec3cc | balrog | omap_prcm_apll_update(s); |
2275 | 51fec3cc | balrog | } |
2276 | 51fec3cc | balrog | if ((s->clken[9] ^ value) & 3) { |
2277 | 51fec3cc | balrog | s->clken[9] &= ~3; |
2278 | 51fec3cc | balrog | s->clken[9] |= value & 3; |
2279 | 51fec3cc | balrog | omap_prcm_dpll_update(s); |
2280 | 51fec3cc | balrog | } |
2281 | 827df9f3 | balrog | break;
|
2282 | 827df9f3 | balrog | case 0x530: /* CM_AUTOIDLE_PLL */ |
2283 | 827df9f3 | balrog | s->clkidle[5] = value & 0x000000cf; |
2284 | 827df9f3 | balrog | /* TODO update clocks */
|
2285 | 827df9f3 | balrog | break;
|
2286 | 827df9f3 | balrog | case 0x540: /* CM_CLKSEL1_PLL */ |
2287 | 51fec3cc | balrog | if (value & 0xfc4000d7) |
2288 | 51fec3cc | balrog | fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
|
2289 | 51fec3cc | balrog | "future compatiblity\n", __FUNCTION__);
|
2290 | 51fec3cc | balrog | if ((s->clksel[5] ^ value) & 0x003fff00) { |
2291 | 51fec3cc | balrog | s->clksel[5] = value & 0x03bfff28; |
2292 | 51fec3cc | balrog | omap_prcm_dpll_update(s); |
2293 | 51fec3cc | balrog | } |
2294 | 51fec3cc | balrog | /* TODO update the other clocks */
|
2295 | 51fec3cc | balrog | |
2296 | 827df9f3 | balrog | s->clksel[5] = value & 0x03bfff28; |
2297 | 827df9f3 | balrog | break;
|
2298 | 827df9f3 | balrog | case 0x544: /* CM_CLKSEL2_PLL */ |
2299 | 51fec3cc | balrog | if (value & ~3) |
2300 | 51fec3cc | balrog | fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
|
2301 | 51fec3cc | balrog | "future compatiblity\n", __FUNCTION__);
|
2302 | 51fec3cc | balrog | if (s->clksel[6] != (value & 3)) { |
2303 | 51fec3cc | balrog | s->clksel[6] = value & 3; |
2304 | 51fec3cc | balrog | omap_prcm_dpll_update(s); |
2305 | 51fec3cc | balrog | } |
2306 | 827df9f3 | balrog | break;
|
2307 | 827df9f3 | balrog | |
2308 | 827df9f3 | balrog | case 0x800: /* CM_FCLKEN_DSP */ |
2309 | 827df9f3 | balrog | s->clken[10] = value & 0x501; |
2310 | 827df9f3 | balrog | /* TODO update clocks */
|
2311 | 827df9f3 | balrog | break;
|
2312 | 827df9f3 | balrog | case 0x810: /* CM_ICLKEN_DSP */ |
2313 | 827df9f3 | balrog | s->clken[11] = value & 0x2; |
2314 | 827df9f3 | balrog | /* TODO update clocks */
|
2315 | 827df9f3 | balrog | break;
|
2316 | 827df9f3 | balrog | case 0x830: /* CM_AUTOIDLE_DSP */ |
2317 | 827df9f3 | balrog | s->clkidle[6] = value & 0x2; |
2318 | 827df9f3 | balrog | /* TODO update clocks */
|
2319 | 827df9f3 | balrog | break;
|
2320 | 827df9f3 | balrog | case 0x840: /* CM_CLKSEL_DSP */ |
2321 | 827df9f3 | balrog | s->clksel[7] = value & 0x3fff; |
2322 | 827df9f3 | balrog | /* TODO update clocks */
|
2323 | 827df9f3 | balrog | break;
|
2324 | 827df9f3 | balrog | case 0x848: /* CM_CLKSTCTRL_DSP */ |
2325 | 827df9f3 | balrog | s->clkctrl[3] = value & 0x101; |
2326 | 827df9f3 | balrog | break;
|
2327 | 827df9f3 | balrog | case 0x850: /* RM_RSTCTRL_DSP */ |
2328 | 827df9f3 | balrog | /* TODO: reset */
|
2329 | 827df9f3 | balrog | break;
|
2330 | 827df9f3 | balrog | case 0x858: /* RM_RSTST_DSP */ |
2331 | 827df9f3 | balrog | s->rst[3] &= ~value;
|
2332 | 827df9f3 | balrog | break;
|
2333 | 827df9f3 | balrog | case 0x8c8: /* PM_WKDEP_DSP */ |
2334 | 827df9f3 | balrog | s->wkup[2] = value & 0x13; |
2335 | 827df9f3 | balrog | break;
|
2336 | 827df9f3 | balrog | case 0x8e0: /* PM_PWSTCTRL_DSP */ |
2337 | 827df9f3 | balrog | s->power[3] = (value & 0x03017) | (3 << 2); |
2338 | 827df9f3 | balrog | break;
|
2339 | 827df9f3 | balrog | |
2340 | 827df9f3 | balrog | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
2341 | 827df9f3 | balrog | s->irqst[1] &= ~value;
|
2342 | 827df9f3 | balrog | omap_prcm_int_update(s, 1);
|
2343 | 827df9f3 | balrog | break;
|
2344 | 827df9f3 | balrog | case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
2345 | 827df9f3 | balrog | s->irqen[1] = value & 0x7; |
2346 | 827df9f3 | balrog | omap_prcm_int_update(s, 1);
|
2347 | 827df9f3 | balrog | break;
|
2348 | 827df9f3 | balrog | |
2349 | 827df9f3 | balrog | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
2350 | 827df9f3 | balrog | s->irqst[2] &= ~value;
|
2351 | 827df9f3 | balrog | omap_prcm_int_update(s, 2);
|
2352 | 827df9f3 | balrog | break;
|
2353 | 827df9f3 | balrog | case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
2354 | 827df9f3 | balrog | s->irqen[2] = value & 0x7; |
2355 | 827df9f3 | balrog | omap_prcm_int_update(s, 2);
|
2356 | 827df9f3 | balrog | break;
|
2357 | 827df9f3 | balrog | |
2358 | 827df9f3 | balrog | default:
|
2359 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2360 | 827df9f3 | balrog | return;
|
2361 | 827df9f3 | balrog | } |
2362 | 827df9f3 | balrog | } |
2363 | 827df9f3 | balrog | |
2364 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_prcm_readfn[] = { |
2365 | 827df9f3 | balrog | omap_badwidth_read32, |
2366 | 827df9f3 | balrog | omap_badwidth_read32, |
2367 | 827df9f3 | balrog | omap_prcm_read, |
2368 | 827df9f3 | balrog | }; |
2369 | 827df9f3 | balrog | |
2370 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_prcm_writefn[] = { |
2371 | 827df9f3 | balrog | omap_badwidth_write32, |
2372 | 827df9f3 | balrog | omap_badwidth_write32, |
2373 | 827df9f3 | balrog | omap_prcm_write, |
2374 | 827df9f3 | balrog | }; |
2375 | 827df9f3 | balrog | |
2376 | 827df9f3 | balrog | static void omap_prcm_reset(struct omap_prcm_s *s) |
2377 | 827df9f3 | balrog | { |
2378 | 827df9f3 | balrog | s->sysconfig = 0;
|
2379 | 827df9f3 | balrog | s->irqst[0] = 0; |
2380 | 827df9f3 | balrog | s->irqst[1] = 0; |
2381 | 827df9f3 | balrog | s->irqst[2] = 0; |
2382 | 827df9f3 | balrog | s->irqen[0] = 0; |
2383 | 827df9f3 | balrog | s->irqen[1] = 0; |
2384 | 827df9f3 | balrog | s->irqen[2] = 0; |
2385 | 827df9f3 | balrog | s->voltctrl = 0x1040;
|
2386 | 827df9f3 | balrog | s->ev = 0x14;
|
2387 | 827df9f3 | balrog | s->evtime[0] = 0; |
2388 | 827df9f3 | balrog | s->evtime[1] = 0; |
2389 | 827df9f3 | balrog | s->clkctrl[0] = 0; |
2390 | 827df9f3 | balrog | s->clkctrl[1] = 0; |
2391 | 827df9f3 | balrog | s->clkctrl[2] = 0; |
2392 | 827df9f3 | balrog | s->clkctrl[3] = 0; |
2393 | 827df9f3 | balrog | s->clken[1] = 7; |
2394 | 827df9f3 | balrog | s->clken[3] = 7; |
2395 | 827df9f3 | balrog | s->clken[4] = 0; |
2396 | 827df9f3 | balrog | s->clken[5] = 0; |
2397 | 827df9f3 | balrog | s->clken[6] = 0; |
2398 | 827df9f3 | balrog | s->clken[7] = 0xc; |
2399 | 827df9f3 | balrog | s->clken[8] = 0x3e; |
2400 | 827df9f3 | balrog | s->clken[9] = 0x0d; |
2401 | 827df9f3 | balrog | s->clken[10] = 0; |
2402 | 827df9f3 | balrog | s->clken[11] = 0; |
2403 | 827df9f3 | balrog | s->clkidle[0] = 0; |
2404 | 827df9f3 | balrog | s->clkidle[2] = 7; |
2405 | 827df9f3 | balrog | s->clkidle[3] = 0; |
2406 | 827df9f3 | balrog | s->clkidle[4] = 0; |
2407 | 827df9f3 | balrog | s->clkidle[5] = 0x0c; |
2408 | 827df9f3 | balrog | s->clkidle[6] = 0; |
2409 | 827df9f3 | balrog | s->clksel[0] = 0x01; |
2410 | 827df9f3 | balrog | s->clksel[1] = 0x02100121; |
2411 | 827df9f3 | balrog | s->clksel[2] = 0x00000000; |
2412 | 827df9f3 | balrog | s->clksel[3] = 0x01; |
2413 | 827df9f3 | balrog | s->clksel[4] = 0; |
2414 | 827df9f3 | balrog | s->clksel[7] = 0x0121; |
2415 | 827df9f3 | balrog | s->wkup[0] = 0x15; |
2416 | 827df9f3 | balrog | s->wkup[1] = 0x13; |
2417 | 827df9f3 | balrog | s->wkup[2] = 0x13; |
2418 | 827df9f3 | balrog | s->wken[0] = 0x04667ff8; |
2419 | 827df9f3 | balrog | s->wken[1] = 0x00000005; |
2420 | 827df9f3 | balrog | s->wken[2] = 5; |
2421 | 827df9f3 | balrog | s->wkst[0] = 0; |
2422 | 827df9f3 | balrog | s->wkst[1] = 0; |
2423 | 827df9f3 | balrog | s->wkst[2] = 0; |
2424 | 827df9f3 | balrog | s->power[0] = 0x00c; |
2425 | 827df9f3 | balrog | s->power[1] = 4; |
2426 | 827df9f3 | balrog | s->power[2] = 0x0000c; |
2427 | 827df9f3 | balrog | s->power[3] = 0x14; |
2428 | 827df9f3 | balrog | s->rstctrl[0] = 1; |
2429 | 827df9f3 | balrog | s->rst[3] = 1; |
2430 | 51fec3cc | balrog | omap_prcm_apll_update(s); |
2431 | 51fec3cc | balrog | omap_prcm_dpll_update(s); |
2432 | 827df9f3 | balrog | } |
2433 | 827df9f3 | balrog | |
2434 | 827df9f3 | balrog | static void omap_prcm_coldreset(struct omap_prcm_s *s) |
2435 | 827df9f3 | balrog | { |
2436 | 827df9f3 | balrog | s->setuptime[0] = 0; |
2437 | 827df9f3 | balrog | s->setuptime[1] = 0; |
2438 | 827df9f3 | balrog | memset(&s->scratch, 0, sizeof(s->scratch)); |
2439 | 827df9f3 | balrog | s->rst[0] = 0x01; |
2440 | 827df9f3 | balrog | s->rst[1] = 0x00; |
2441 | 827df9f3 | balrog | s->rst[2] = 0x01; |
2442 | 827df9f3 | balrog | s->clken[0] = 0; |
2443 | 827df9f3 | balrog | s->clken[2] = 0; |
2444 | 827df9f3 | balrog | s->clkidle[1] = 0; |
2445 | 827df9f3 | balrog | s->clksel[5] = 0; |
2446 | 827df9f3 | balrog | s->clksel[6] = 2; |
2447 | 827df9f3 | balrog | s->clksrc[0] = 0x43; |
2448 | 827df9f3 | balrog | s->clkout[0] = 0x0303; |
2449 | 827df9f3 | balrog | s->clkemul[0] = 0; |
2450 | 827df9f3 | balrog | s->clkpol[0] = 0x100; |
2451 | 827df9f3 | balrog | s->rsttime_wkup = 0x1002;
|
2452 | 827df9f3 | balrog | |
2453 | 827df9f3 | balrog | omap_prcm_reset(s); |
2454 | 827df9f3 | balrog | } |
2455 | 827df9f3 | balrog | |
2456 | 827df9f3 | balrog | struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
2457 | 827df9f3 | balrog | qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
2458 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu)
|
2459 | 827df9f3 | balrog | { |
2460 | 827df9f3 | balrog | int iomemtype;
|
2461 | 827df9f3 | balrog | struct omap_prcm_s *s = (struct omap_prcm_s *) |
2462 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_prcm_s)); |
2463 | 827df9f3 | balrog | |
2464 | 827df9f3 | balrog | s->irq[0] = mpu_int;
|
2465 | 827df9f3 | balrog | s->irq[1] = dsp_int;
|
2466 | 827df9f3 | balrog | s->irq[2] = iva_int;
|
2467 | 827df9f3 | balrog | s->mpu = mpu; |
2468 | 827df9f3 | balrog | omap_prcm_coldreset(s); |
2469 | 827df9f3 | balrog | |
2470 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_prcm_readfn, |
2471 | 827df9f3 | balrog | omap_prcm_writefn, s); |
2472 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
2473 | 827df9f3 | balrog | omap_l4_attach(ta, 1, iomemtype);
|
2474 | 827df9f3 | balrog | |
2475 | 827df9f3 | balrog | return s;
|
2476 | 827df9f3 | balrog | } |
2477 | 827df9f3 | balrog | |
2478 | 827df9f3 | balrog | /* System and Pinout control */
|
2479 | 827df9f3 | balrog | struct omap_sysctl_s {
|
2480 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu;
|
2481 | 827df9f3 | balrog | |
2482 | 827df9f3 | balrog | uint32_t sysconfig; |
2483 | 827df9f3 | balrog | uint32_t devconfig; |
2484 | 827df9f3 | balrog | uint32_t psaconfig; |
2485 | 827df9f3 | balrog | uint32_t padconf[0x45];
|
2486 | 827df9f3 | balrog | uint8_t obs; |
2487 | 827df9f3 | balrog | uint32_t msuspendmux[5];
|
2488 | 827df9f3 | balrog | }; |
2489 | 827df9f3 | balrog | |
2490 | c227f099 | Anthony Liguori | static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr) |
2491 | f451387a | balrog | { |
2492 | f451387a | balrog | |
2493 | f451387a | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
2494 | f451387a | balrog | int pad_offset, byte_offset;
|
2495 | f451387a | balrog | int value;
|
2496 | f451387a | balrog | |
2497 | 8da3ff18 | pbrook | switch (addr) {
|
2498 | f451387a | balrog | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
2499 | 8da3ff18 | pbrook | pad_offset = (addr - 0x30) >> 2; |
2500 | 8da3ff18 | pbrook | byte_offset = (addr - 0x30) & (4 - 1); |
2501 | f451387a | balrog | |
2502 | f451387a | balrog | value = s->padconf[pad_offset]; |
2503 | f451387a | balrog | value = (value >> (byte_offset * 8)) & 0xff; |
2504 | f451387a | balrog | |
2505 | f451387a | balrog | return value;
|
2506 | f451387a | balrog | |
2507 | f451387a | balrog | default:
|
2508 | f451387a | balrog | break;
|
2509 | f451387a | balrog | } |
2510 | f451387a | balrog | |
2511 | f451387a | balrog | OMAP_BAD_REG(addr); |
2512 | f451387a | balrog | return 0; |
2513 | f451387a | balrog | } |
2514 | f451387a | balrog | |
2515 | c227f099 | Anthony Liguori | static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) |
2516 | 827df9f3 | balrog | { |
2517 | 827df9f3 | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
2518 | 827df9f3 | balrog | |
2519 | 8da3ff18 | pbrook | switch (addr) {
|
2520 | 827df9f3 | balrog | case 0x000: /* CONTROL_REVISION */ |
2521 | 827df9f3 | balrog | return 0x20; |
2522 | 827df9f3 | balrog | |
2523 | 827df9f3 | balrog | case 0x010: /* CONTROL_SYSCONFIG */ |
2524 | 827df9f3 | balrog | return s->sysconfig;
|
2525 | 827df9f3 | balrog | |
2526 | 827df9f3 | balrog | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
2527 | 8da3ff18 | pbrook | return s->padconf[(addr - 0x30) >> 2]; |
2528 | 827df9f3 | balrog | |
2529 | 827df9f3 | balrog | case 0x270: /* CONTROL_DEBOBS */ |
2530 | 827df9f3 | balrog | return s->obs;
|
2531 | 827df9f3 | balrog | |
2532 | 827df9f3 | balrog | case 0x274: /* CONTROL_DEVCONF */ |
2533 | 827df9f3 | balrog | return s->devconfig;
|
2534 | 827df9f3 | balrog | |
2535 | 827df9f3 | balrog | case 0x28c: /* CONTROL_EMU_SUPPORT */ |
2536 | 827df9f3 | balrog | return 0; |
2537 | 827df9f3 | balrog | |
2538 | 827df9f3 | balrog | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
2539 | 827df9f3 | balrog | return s->msuspendmux[0]; |
2540 | 827df9f3 | balrog | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
2541 | 827df9f3 | balrog | return s->msuspendmux[1]; |
2542 | 827df9f3 | balrog | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
2543 | 827df9f3 | balrog | return s->msuspendmux[2]; |
2544 | 827df9f3 | balrog | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
2545 | 827df9f3 | balrog | return s->msuspendmux[3]; |
2546 | 827df9f3 | balrog | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
2547 | 827df9f3 | balrog | return s->msuspendmux[4]; |
2548 | 827df9f3 | balrog | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
2549 | 827df9f3 | balrog | return 0; |
2550 | 827df9f3 | balrog | |
2551 | 827df9f3 | balrog | case 0x2b8: /* CONTROL_PSA_CTRL */ |
2552 | 827df9f3 | balrog | return s->psaconfig;
|
2553 | 827df9f3 | balrog | case 0x2bc: /* CONTROL_PSA_CMD */ |
2554 | 827df9f3 | balrog | case 0x2c0: /* CONTROL_PSA_VALUE */ |
2555 | 827df9f3 | balrog | return 0; |
2556 | 827df9f3 | balrog | |
2557 | 827df9f3 | balrog | case 0x2b0: /* CONTROL_SEC_CTRL */ |
2558 | 827df9f3 | balrog | return 0x800000f1; |
2559 | 827df9f3 | balrog | case 0x2d0: /* CONTROL_SEC_EMU */ |
2560 | 827df9f3 | balrog | return 0x80000015; |
2561 | 827df9f3 | balrog | case 0x2d4: /* CONTROL_SEC_TAP */ |
2562 | 827df9f3 | balrog | return 0x8000007f; |
2563 | 827df9f3 | balrog | case 0x2b4: /* CONTROL_SEC_TEST */ |
2564 | 827df9f3 | balrog | case 0x2f0: /* CONTROL_SEC_STATUS */ |
2565 | 827df9f3 | balrog | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
2566 | 827df9f3 | balrog | /* Secure mode is not present on general-pusrpose device. Outside
|
2567 | 827df9f3 | balrog | * secure mode these values cannot be read or written. */
|
2568 | 827df9f3 | balrog | return 0; |
2569 | 827df9f3 | balrog | |
2570 | 827df9f3 | balrog | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
2571 | 827df9f3 | balrog | return 0xff; |
2572 | 827df9f3 | balrog | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
2573 | 827df9f3 | balrog | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
2574 | 827df9f3 | balrog | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
2575 | 827df9f3 | balrog | /* No secure mode so no Extended Secure RAM present. */
|
2576 | 827df9f3 | balrog | return 0; |
2577 | 827df9f3 | balrog | |
2578 | 827df9f3 | balrog | case 0x2f8: /* CONTROL_STATUS */ |
2579 | 827df9f3 | balrog | /* Device Type => General-purpose */
|
2580 | 827df9f3 | balrog | return 0x0300; |
2581 | 827df9f3 | balrog | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
2582 | 827df9f3 | balrog | |
2583 | 827df9f3 | balrog | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
2584 | 827df9f3 | balrog | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
2585 | 827df9f3 | balrog | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
2586 | 827df9f3 | balrog | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
2587 | 827df9f3 | balrog | return 0xdecafbad; |
2588 | 827df9f3 | balrog | |
2589 | 827df9f3 | balrog | case 0x310: /* CONTROL_RAND_KEY_0 */ |
2590 | 827df9f3 | balrog | case 0x314: /* CONTROL_RAND_KEY_1 */ |
2591 | 827df9f3 | balrog | case 0x318: /* CONTROL_RAND_KEY_2 */ |
2592 | 827df9f3 | balrog | case 0x31c: /* CONTROL_RAND_KEY_3 */ |
2593 | 827df9f3 | balrog | case 0x320: /* CONTROL_CUST_KEY_0 */ |
2594 | 827df9f3 | balrog | case 0x324: /* CONTROL_CUST_KEY_1 */ |
2595 | 827df9f3 | balrog | case 0x330: /* CONTROL_TEST_KEY_0 */ |
2596 | 827df9f3 | balrog | case 0x334: /* CONTROL_TEST_KEY_1 */ |
2597 | 827df9f3 | balrog | case 0x338: /* CONTROL_TEST_KEY_2 */ |
2598 | 827df9f3 | balrog | case 0x33c: /* CONTROL_TEST_KEY_3 */ |
2599 | 827df9f3 | balrog | case 0x340: /* CONTROL_TEST_KEY_4 */ |
2600 | 827df9f3 | balrog | case 0x344: /* CONTROL_TEST_KEY_5 */ |
2601 | 827df9f3 | balrog | case 0x348: /* CONTROL_TEST_KEY_6 */ |
2602 | 827df9f3 | balrog | case 0x34c: /* CONTROL_TEST_KEY_7 */ |
2603 | 827df9f3 | balrog | case 0x350: /* CONTROL_TEST_KEY_8 */ |
2604 | 827df9f3 | balrog | case 0x354: /* CONTROL_TEST_KEY_9 */ |
2605 | 827df9f3 | balrog | /* Can only be accessed in secure mode and when C_FieldAccEnable
|
2606 | 827df9f3 | balrog | * bit is set in CONTROL_SEC_CTRL.
|
2607 | 827df9f3 | balrog | * TODO: otherwise an interconnect access error is generated. */
|
2608 | 827df9f3 | balrog | return 0; |
2609 | 827df9f3 | balrog | } |
2610 | 827df9f3 | balrog | |
2611 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2612 | 827df9f3 | balrog | return 0; |
2613 | 827df9f3 | balrog | } |
2614 | 827df9f3 | balrog | |
2615 | c227f099 | Anthony Liguori | static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr, |
2616 | f451387a | balrog | uint32_t value) |
2617 | f451387a | balrog | { |
2618 | f451387a | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
2619 | f451387a | balrog | int pad_offset, byte_offset;
|
2620 | f451387a | balrog | int prev_value;
|
2621 | f451387a | balrog | |
2622 | 8da3ff18 | pbrook | switch (addr) {
|
2623 | f451387a | balrog | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
2624 | 8da3ff18 | pbrook | pad_offset = (addr - 0x30) >> 2; |
2625 | 8da3ff18 | pbrook | byte_offset = (addr - 0x30) & (4 - 1); |
2626 | f451387a | balrog | |
2627 | f451387a | balrog | prev_value = s->padconf[pad_offset]; |
2628 | f451387a | balrog | prev_value &= ~(0xff << (byte_offset * 8)); |
2629 | f451387a | balrog | prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f; |
2630 | f451387a | balrog | s->padconf[pad_offset] = prev_value; |
2631 | f451387a | balrog | break;
|
2632 | f451387a | balrog | |
2633 | f451387a | balrog | default:
|
2634 | f451387a | balrog | OMAP_BAD_REG(addr); |
2635 | f451387a | balrog | break;
|
2636 | f451387a | balrog | } |
2637 | f451387a | balrog | } |
2638 | f451387a | balrog | |
2639 | c227f099 | Anthony Liguori | static void omap_sysctl_write(void *opaque, target_phys_addr_t addr, |
2640 | 827df9f3 | balrog | uint32_t value) |
2641 | 827df9f3 | balrog | { |
2642 | 827df9f3 | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
2643 | 827df9f3 | balrog | |
2644 | 8da3ff18 | pbrook | switch (addr) {
|
2645 | 827df9f3 | balrog | case 0x000: /* CONTROL_REVISION */ |
2646 | 827df9f3 | balrog | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
2647 | 827df9f3 | balrog | case 0x2c0: /* CONTROL_PSA_VALUE */ |
2648 | 827df9f3 | balrog | case 0x2f8: /* CONTROL_STATUS */ |
2649 | 827df9f3 | balrog | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
2650 | 827df9f3 | balrog | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
2651 | 827df9f3 | balrog | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
2652 | 827df9f3 | balrog | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
2653 | 827df9f3 | balrog | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
2654 | 827df9f3 | balrog | case 0x310: /* CONTROL_RAND_KEY_0 */ |
2655 | 827df9f3 | balrog | case 0x314: /* CONTROL_RAND_KEY_1 */ |
2656 | 827df9f3 | balrog | case 0x318: /* CONTROL_RAND_KEY_2 */ |
2657 | 827df9f3 | balrog | case 0x31c: /* CONTROL_RAND_KEY_3 */ |
2658 | 827df9f3 | balrog | case 0x320: /* CONTROL_CUST_KEY_0 */ |
2659 | 827df9f3 | balrog | case 0x324: /* CONTROL_CUST_KEY_1 */ |
2660 | 827df9f3 | balrog | case 0x330: /* CONTROL_TEST_KEY_0 */ |
2661 | 827df9f3 | balrog | case 0x334: /* CONTROL_TEST_KEY_1 */ |
2662 | 827df9f3 | balrog | case 0x338: /* CONTROL_TEST_KEY_2 */ |
2663 | 827df9f3 | balrog | case 0x33c: /* CONTROL_TEST_KEY_3 */ |
2664 | 827df9f3 | balrog | case 0x340: /* CONTROL_TEST_KEY_4 */ |
2665 | 827df9f3 | balrog | case 0x344: /* CONTROL_TEST_KEY_5 */ |
2666 | 827df9f3 | balrog | case 0x348: /* CONTROL_TEST_KEY_6 */ |
2667 | 827df9f3 | balrog | case 0x34c: /* CONTROL_TEST_KEY_7 */ |
2668 | 827df9f3 | balrog | case 0x350: /* CONTROL_TEST_KEY_8 */ |
2669 | 827df9f3 | balrog | case 0x354: /* CONTROL_TEST_KEY_9 */ |
2670 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
2671 | 827df9f3 | balrog | return;
|
2672 | 827df9f3 | balrog | |
2673 | 827df9f3 | balrog | case 0x010: /* CONTROL_SYSCONFIG */ |
2674 | 827df9f3 | balrog | s->sysconfig = value & 0x1e;
|
2675 | 827df9f3 | balrog | break;
|
2676 | 827df9f3 | balrog | |
2677 | 827df9f3 | balrog | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
2678 | 827df9f3 | balrog | /* XXX: should check constant bits */
|
2679 | 8da3ff18 | pbrook | s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f; |
2680 | 827df9f3 | balrog | break;
|
2681 | 827df9f3 | balrog | |
2682 | 827df9f3 | balrog | case 0x270: /* CONTROL_DEBOBS */ |
2683 | 827df9f3 | balrog | s->obs = value & 0xff;
|
2684 | 827df9f3 | balrog | break;
|
2685 | 827df9f3 | balrog | |
2686 | 827df9f3 | balrog | case 0x274: /* CONTROL_DEVCONF */ |
2687 | 827df9f3 | balrog | s->devconfig = value & 0xffffc7ff;
|
2688 | 827df9f3 | balrog | break;
|
2689 | 827df9f3 | balrog | |
2690 | 827df9f3 | balrog | case 0x28c: /* CONTROL_EMU_SUPPORT */ |
2691 | 827df9f3 | balrog | break;
|
2692 | 827df9f3 | balrog | |
2693 | 827df9f3 | balrog | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
2694 | 827df9f3 | balrog | s->msuspendmux[0] = value & 0x3fffffff; |
2695 | 827df9f3 | balrog | break;
|
2696 | 827df9f3 | balrog | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
2697 | 827df9f3 | balrog | s->msuspendmux[1] = value & 0x3fffffff; |
2698 | 827df9f3 | balrog | break;
|
2699 | 827df9f3 | balrog | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
2700 | 827df9f3 | balrog | s->msuspendmux[2] = value & 0x3fffffff; |
2701 | 827df9f3 | balrog | break;
|
2702 | 827df9f3 | balrog | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
2703 | 827df9f3 | balrog | s->msuspendmux[3] = value & 0x3fffffff; |
2704 | 827df9f3 | balrog | break;
|
2705 | 827df9f3 | balrog | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
2706 | 827df9f3 | balrog | s->msuspendmux[4] = value & 0x3fffffff; |
2707 | 827df9f3 | balrog | break;
|
2708 | 827df9f3 | balrog | |
2709 | 827df9f3 | balrog | case 0x2b8: /* CONTROL_PSA_CTRL */ |
2710 | 827df9f3 | balrog | s->psaconfig = value & 0x1c;
|
2711 | 827df9f3 | balrog | s->psaconfig |= (value & 0x20) ? 2 : 1; |
2712 | 827df9f3 | balrog | break;
|
2713 | 827df9f3 | balrog | case 0x2bc: /* CONTROL_PSA_CMD */ |
2714 | 827df9f3 | balrog | break;
|
2715 | 827df9f3 | balrog | |
2716 | 827df9f3 | balrog | case 0x2b0: /* CONTROL_SEC_CTRL */ |
2717 | 827df9f3 | balrog | case 0x2b4: /* CONTROL_SEC_TEST */ |
2718 | 827df9f3 | balrog | case 0x2d0: /* CONTROL_SEC_EMU */ |
2719 | 827df9f3 | balrog | case 0x2d4: /* CONTROL_SEC_TAP */ |
2720 | 827df9f3 | balrog | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
2721 | 827df9f3 | balrog | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
2722 | 827df9f3 | balrog | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
2723 | 827df9f3 | balrog | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
2724 | 827df9f3 | balrog | case 0x2f0: /* CONTROL_SEC_STATUS */ |
2725 | 827df9f3 | balrog | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
2726 | 827df9f3 | balrog | break;
|
2727 | 827df9f3 | balrog | |
2728 | 827df9f3 | balrog | default:
|
2729 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2730 | 827df9f3 | balrog | return;
|
2731 | 827df9f3 | balrog | } |
2732 | 827df9f3 | balrog | } |
2733 | 827df9f3 | balrog | |
2734 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_sysctl_readfn[] = { |
2735 | f451387a | balrog | omap_sysctl_read8, |
2736 | 827df9f3 | balrog | omap_badwidth_read32, /* TODO */
|
2737 | 827df9f3 | balrog | omap_sysctl_read, |
2738 | 827df9f3 | balrog | }; |
2739 | 827df9f3 | balrog | |
2740 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = { |
2741 | f451387a | balrog | omap_sysctl_write8, |
2742 | 827df9f3 | balrog | omap_badwidth_write32, /* TODO */
|
2743 | 827df9f3 | balrog | omap_sysctl_write, |
2744 | 827df9f3 | balrog | }; |
2745 | 827df9f3 | balrog | |
2746 | 827df9f3 | balrog | static void omap_sysctl_reset(struct omap_sysctl_s *s) |
2747 | 827df9f3 | balrog | { |
2748 | 827df9f3 | balrog | /* (power-on reset) */
|
2749 | 827df9f3 | balrog | s->sysconfig = 0;
|
2750 | 827df9f3 | balrog | s->obs = 0;
|
2751 | 827df9f3 | balrog | s->devconfig = 0x0c000000;
|
2752 | 827df9f3 | balrog | s->msuspendmux[0] = 0x00000000; |
2753 | 827df9f3 | balrog | s->msuspendmux[1] = 0x00000000; |
2754 | 827df9f3 | balrog | s->msuspendmux[2] = 0x00000000; |
2755 | 827df9f3 | balrog | s->msuspendmux[3] = 0x00000000; |
2756 | 827df9f3 | balrog | s->msuspendmux[4] = 0x00000000; |
2757 | 827df9f3 | balrog | s->psaconfig = 1;
|
2758 | 827df9f3 | balrog | |
2759 | 827df9f3 | balrog | s->padconf[0x00] = 0x000f0f0f; |
2760 | 827df9f3 | balrog | s->padconf[0x01] = 0x00000000; |
2761 | 827df9f3 | balrog | s->padconf[0x02] = 0x00000000; |
2762 | 827df9f3 | balrog | s->padconf[0x03] = 0x00000000; |
2763 | 827df9f3 | balrog | s->padconf[0x04] = 0x00000000; |
2764 | 827df9f3 | balrog | s->padconf[0x05] = 0x00000000; |
2765 | 827df9f3 | balrog | s->padconf[0x06] = 0x00000000; |
2766 | 827df9f3 | balrog | s->padconf[0x07] = 0x00000000; |
2767 | 827df9f3 | balrog | s->padconf[0x08] = 0x08080800; |
2768 | 827df9f3 | balrog | s->padconf[0x09] = 0x08080808; |
2769 | 827df9f3 | balrog | s->padconf[0x0a] = 0x08080808; |
2770 | 827df9f3 | balrog | s->padconf[0x0b] = 0x08080808; |
2771 | 827df9f3 | balrog | s->padconf[0x0c] = 0x08080808; |
2772 | 827df9f3 | balrog | s->padconf[0x0d] = 0x08080800; |
2773 | 827df9f3 | balrog | s->padconf[0x0e] = 0x08080808; |
2774 | 827df9f3 | balrog | s->padconf[0x0f] = 0x08080808; |
2775 | 827df9f3 | balrog | s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ |
2776 | 827df9f3 | balrog | s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
2777 | 827df9f3 | balrog | s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
2778 | 827df9f3 | balrog | s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
2779 | 827df9f3 | balrog | s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ |
2780 | 827df9f3 | balrog | s->padconf[0x15] = 0x18181818; |
2781 | 827df9f3 | balrog | s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ |
2782 | 827df9f3 | balrog | s->padconf[0x17] = 0x1f001f00; |
2783 | 827df9f3 | balrog | s->padconf[0x18] = 0x1f1f1f1f; |
2784 | 827df9f3 | balrog | s->padconf[0x19] = 0x00000000; |
2785 | 827df9f3 | balrog | s->padconf[0x1a] = 0x1f180000; |
2786 | 827df9f3 | balrog | s->padconf[0x1b] = 0x00001f1f; |
2787 | 827df9f3 | balrog | s->padconf[0x1c] = 0x1f001f00; |
2788 | 827df9f3 | balrog | s->padconf[0x1d] = 0x00000000; |
2789 | 827df9f3 | balrog | s->padconf[0x1e] = 0x00000000; |
2790 | 827df9f3 | balrog | s->padconf[0x1f] = 0x08000000; |
2791 | 827df9f3 | balrog | s->padconf[0x20] = 0x08080808; |
2792 | 827df9f3 | balrog | s->padconf[0x21] = 0x08080808; |
2793 | 827df9f3 | balrog | s->padconf[0x22] = 0x0f080808; |
2794 | 827df9f3 | balrog | s->padconf[0x23] = 0x0f0f0f0f; |
2795 | 827df9f3 | balrog | s->padconf[0x24] = 0x000f0f0f; |
2796 | 827df9f3 | balrog | s->padconf[0x25] = 0x1f1f1f0f; |
2797 | 827df9f3 | balrog | s->padconf[0x26] = 0x080f0f1f; |
2798 | 827df9f3 | balrog | s->padconf[0x27] = 0x070f1808; |
2799 | 827df9f3 | balrog | s->padconf[0x28] = 0x0f070707; |
2800 | 827df9f3 | balrog | s->padconf[0x29] = 0x000f0f1f; |
2801 | 827df9f3 | balrog | s->padconf[0x2a] = 0x0f0f0f1f; |
2802 | 827df9f3 | balrog | s->padconf[0x2b] = 0x08000000; |
2803 | 827df9f3 | balrog | s->padconf[0x2c] = 0x0000001f; |
2804 | 827df9f3 | balrog | s->padconf[0x2d] = 0x0f0f1f00; |
2805 | 827df9f3 | balrog | s->padconf[0x2e] = 0x1f1f0f0f; |
2806 | 827df9f3 | balrog | s->padconf[0x2f] = 0x0f1f1f1f; |
2807 | 827df9f3 | balrog | s->padconf[0x30] = 0x0f0f0f0f; |
2808 | 827df9f3 | balrog | s->padconf[0x31] = 0x0f1f0f1f; |
2809 | 827df9f3 | balrog | s->padconf[0x32] = 0x0f0f0f0f; |
2810 | 827df9f3 | balrog | s->padconf[0x33] = 0x0f1f0f1f; |
2811 | 827df9f3 | balrog | s->padconf[0x34] = 0x1f1f0f0f; |
2812 | 827df9f3 | balrog | s->padconf[0x35] = 0x0f0f1f1f; |
2813 | 827df9f3 | balrog | s->padconf[0x36] = 0x0f0f1f0f; |
2814 | 827df9f3 | balrog | s->padconf[0x37] = 0x0f0f0f0f; |
2815 | 827df9f3 | balrog | s->padconf[0x38] = 0x1f18180f; |
2816 | 827df9f3 | balrog | s->padconf[0x39] = 0x1f1f1f1f; |
2817 | 827df9f3 | balrog | s->padconf[0x3a] = 0x00001f1f; |
2818 | 827df9f3 | balrog | s->padconf[0x3b] = 0x00000000; |
2819 | 827df9f3 | balrog | s->padconf[0x3c] = 0x00000000; |
2820 | 827df9f3 | balrog | s->padconf[0x3d] = 0x0f0f0f0f; |
2821 | 827df9f3 | balrog | s->padconf[0x3e] = 0x18000f0f; |
2822 | 827df9f3 | balrog | s->padconf[0x3f] = 0x00070000; |
2823 | 827df9f3 | balrog | s->padconf[0x40] = 0x00000707; |
2824 | 827df9f3 | balrog | s->padconf[0x41] = 0x0f1f0700; |
2825 | 827df9f3 | balrog | s->padconf[0x42] = 0x1f1f070f; |
2826 | 827df9f3 | balrog | s->padconf[0x43] = 0x0008081f; |
2827 | 827df9f3 | balrog | s->padconf[0x44] = 0x00000800; |
2828 | 827df9f3 | balrog | } |
2829 | 827df9f3 | balrog | |
2830 | 827df9f3 | balrog | struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
2831 | 827df9f3 | balrog | omap_clk iclk, struct omap_mpu_state_s *mpu)
|
2832 | 827df9f3 | balrog | { |
2833 | 827df9f3 | balrog | int iomemtype;
|
2834 | 827df9f3 | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) |
2835 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_sysctl_s)); |
2836 | 827df9f3 | balrog | |
2837 | 827df9f3 | balrog | s->mpu = mpu; |
2838 | 827df9f3 | balrog | omap_sysctl_reset(s); |
2839 | 827df9f3 | balrog | |
2840 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_sysctl_readfn, |
2841 | 827df9f3 | balrog | omap_sysctl_writefn, s); |
2842 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
2843 | 827df9f3 | balrog | |
2844 | 827df9f3 | balrog | return s;
|
2845 | 827df9f3 | balrog | } |
2846 | 827df9f3 | balrog | |
2847 | 827df9f3 | balrog | /* General chip reset */
|
2848 | 827df9f3 | balrog | static void omap2_mpu_reset(void *opaque) |
2849 | 827df9f3 | balrog | { |
2850 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
2851 | 827df9f3 | balrog | |
2852 | 827df9f3 | balrog | omap_inth_reset(mpu->ih[0]);
|
2853 | 827df9f3 | balrog | omap_dma_reset(mpu->dma); |
2854 | 827df9f3 | balrog | omap_prcm_reset(mpu->prcm); |
2855 | 827df9f3 | balrog | omap_sysctl_reset(mpu->sysc); |
2856 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[0]);
|
2857 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[1]);
|
2858 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[2]);
|
2859 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[3]);
|
2860 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[4]);
|
2861 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[5]);
|
2862 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[6]);
|
2863 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[7]);
|
2864 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[8]);
|
2865 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[9]);
|
2866 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[10]);
|
2867 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[11]);
|
2868 | 011d87d0 | cmchao | omap_synctimer_reset(mpu->synctimer); |
2869 | 827df9f3 | balrog | omap_sdrc_reset(mpu->sdrc); |
2870 | 827df9f3 | balrog | omap_gpmc_reset(mpu->gpmc); |
2871 | 827df9f3 | balrog | omap_dss_reset(mpu->dss); |
2872 | 827df9f3 | balrog | omap_uart_reset(mpu->uart[0]);
|
2873 | 827df9f3 | balrog | omap_uart_reset(mpu->uart[1]);
|
2874 | 827df9f3 | balrog | omap_uart_reset(mpu->uart[2]);
|
2875 | 827df9f3 | balrog | omap_mmc_reset(mpu->mmc); |
2876 | 827df9f3 | balrog | omap_gpif_reset(mpu->gpif); |
2877 | 827df9f3 | balrog | omap_mcspi_reset(mpu->mcspi[0]);
|
2878 | 827df9f3 | balrog | omap_mcspi_reset(mpu->mcspi[1]);
|
2879 | 827df9f3 | balrog | omap_i2c_reset(mpu->i2c[0]);
|
2880 | 827df9f3 | balrog | omap_i2c_reset(mpu->i2c[1]);
|
2881 | 827df9f3 | balrog | cpu_reset(mpu->env); |
2882 | 827df9f3 | balrog | } |
2883 | 827df9f3 | balrog | |
2884 | 827df9f3 | balrog | static int omap2_validate_addr(struct omap_mpu_state_s *s, |
2885 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
2886 | 827df9f3 | balrog | { |
2887 | 827df9f3 | balrog | return 1; |
2888 | 827df9f3 | balrog | } |
2889 | 827df9f3 | balrog | |
2890 | 827df9f3 | balrog | static const struct dma_irq_map omap2_dma_irq_map[] = { |
2891 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ0 },
|
2892 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ1 },
|
2893 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ2 },
|
2894 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ3 },
|
2895 | 827df9f3 | balrog | }; |
2896 | 827df9f3 | balrog | |
2897 | 827df9f3 | balrog | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
2898 | 3023f332 | aliguori | const char *core) |
2899 | 827df9f3 | balrog | { |
2900 | 827df9f3 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
2901 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
2902 | c227f099 | Anthony Liguori | ram_addr_t sram_base, q2_base; |
2903 | 827df9f3 | balrog | qemu_irq *cpu_irq; |
2904 | 827df9f3 | balrog | qemu_irq dma_irqs[4];
|
2905 | 827df9f3 | balrog | omap_clk gpio_clks[4];
|
2906 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
2907 | 827df9f3 | balrog | int i;
|
2908 | 827df9f3 | balrog | |
2909 | 827df9f3 | balrog | /* Core */
|
2910 | 827df9f3 | balrog | s->mpu_model = omap2420; |
2911 | 827df9f3 | balrog | s->env = cpu_init(core ?: "arm1136-r2");
|
2912 | 827df9f3 | balrog | if (!s->env) {
|
2913 | 827df9f3 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
2914 | 827df9f3 | balrog | exit(1);
|
2915 | 827df9f3 | balrog | } |
2916 | 827df9f3 | balrog | s->sdram_size = sdram_size; |
2917 | 827df9f3 | balrog | s->sram_size = OMAP242X_SRAM_SIZE; |
2918 | 827df9f3 | balrog | |
2919 | 827df9f3 | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
2920 | 827df9f3 | balrog | |
2921 | 827df9f3 | balrog | /* Clocks */
|
2922 | 827df9f3 | balrog | omap_clk_init(s); |
2923 | 827df9f3 | balrog | |
2924 | 827df9f3 | balrog | /* Memory-mapped stuff */
|
2925 | 827df9f3 | balrog | cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size, |
2926 | 7e7c5e4c | balrog | (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
2927 | 827df9f3 | balrog | cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size, |
2928 | 827df9f3 | balrog | (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
2929 | 827df9f3 | balrog | |
2930 | 827df9f3 | balrog | s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
|
2931 | 827df9f3 | balrog | |
2932 | 827df9f3 | balrog | /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
|
2933 | 827df9f3 | balrog | cpu_irq = arm_pic_init_cpu(s->env); |
2934 | 827df9f3 | balrog | s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0], |
2935 | 827df9f3 | balrog | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
2936 | 827df9f3 | balrog | omap_findclk(s, "mpu_intc_fclk"),
|
2937 | 827df9f3 | balrog | omap_findclk(s, "mpu_intc_iclk"));
|
2938 | 827df9f3 | balrog | |
2939 | 827df9f3 | balrog | s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
|
2940 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s); |
2941 | 827df9f3 | balrog | |
2942 | 827df9f3 | balrog | s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
|
2943 | 827df9f3 | balrog | omap_findclk(s, "omapctrl_iclk"), s);
|
2944 | 827df9f3 | balrog | |
2945 | 827df9f3 | balrog | for (i = 0; i < 4; i ++) |
2946 | 827df9f3 | balrog | dma_irqs[i] = |
2947 | 827df9f3 | balrog | s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr]; |
2948 | 827df9f3 | balrog | s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32, |
2949 | 827df9f3 | balrog | omap_findclk(s, "sdma_iclk"),
|
2950 | 827df9f3 | balrog | omap_findclk(s, "sdma_fclk"));
|
2951 | 827df9f3 | balrog | s->port->addr_valid = omap2_validate_addr; |
2952 | 827df9f3 | balrog | |
2953 | afbb5194 | balrog | /* Register SDRAM and SRAM ports for fast DMA transfers. */
|
2954 | afbb5194 | balrog | soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size); |
2955 | afbb5194 | balrog | soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size); |
2956 | afbb5194 | balrog | |
2957 | 827df9f3 | balrog | s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19), |
2958 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_UART1_IRQ],
|
2959 | 827df9f3 | balrog | omap_findclk(s, "uart1_fclk"),
|
2960 | 827df9f3 | balrog | omap_findclk(s, "uart1_iclk"),
|
2961 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART1_TX], |
2962 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
|
2963 | 827df9f3 | balrog | s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), |
2964 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_UART2_IRQ],
|
2965 | 827df9f3 | balrog | omap_findclk(s, "uart2_fclk"),
|
2966 | 827df9f3 | balrog | omap_findclk(s, "uart2_iclk"),
|
2967 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART2_TX], |
2968 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART2_RX], |
2969 | b9d38e95 | Blue Swirl | serial_hds[0] ? serial_hds[1] : NULL); |
2970 | 827df9f3 | balrog | s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), |
2971 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_UART3_IRQ],
|
2972 | 827df9f3 | balrog | omap_findclk(s, "uart3_fclk"),
|
2973 | 827df9f3 | balrog | omap_findclk(s, "uart3_iclk"),
|
2974 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART3_TX], |
2975 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART3_RX], |
2976 | b9d38e95 | Blue Swirl | serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
2977 | 827df9f3 | balrog | |
2978 | 827df9f3 | balrog | s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), |
2979 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER1],
|
2980 | 827df9f3 | balrog | omap_findclk(s, "wu_gpt1_clk"),
|
2981 | 827df9f3 | balrog | omap_findclk(s, "wu_l4_iclk"));
|
2982 | 827df9f3 | balrog | s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), |
2983 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER2],
|
2984 | 827df9f3 | balrog | omap_findclk(s, "core_gpt2_clk"),
|
2985 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
2986 | 827df9f3 | balrog | s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), |
2987 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER3],
|
2988 | 827df9f3 | balrog | omap_findclk(s, "core_gpt3_clk"),
|
2989 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
2990 | 827df9f3 | balrog | s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), |
2991 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER4],
|
2992 | 827df9f3 | balrog | omap_findclk(s, "core_gpt4_clk"),
|
2993 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
2994 | 827df9f3 | balrog | s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), |
2995 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER5],
|
2996 | 827df9f3 | balrog | omap_findclk(s, "core_gpt5_clk"),
|
2997 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
2998 | 827df9f3 | balrog | s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), |
2999 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER6],
|
3000 | 827df9f3 | balrog | omap_findclk(s, "core_gpt6_clk"),
|
3001 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3002 | 827df9f3 | balrog | s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), |
3003 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER7],
|
3004 | 827df9f3 | balrog | omap_findclk(s, "core_gpt7_clk"),
|
3005 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3006 | 827df9f3 | balrog | s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), |
3007 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER8],
|
3008 | 827df9f3 | balrog | omap_findclk(s, "core_gpt8_clk"),
|
3009 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3010 | 827df9f3 | balrog | s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), |
3011 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER9],
|
3012 | 827df9f3 | balrog | omap_findclk(s, "core_gpt9_clk"),
|
3013 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3014 | 827df9f3 | balrog | s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), |
3015 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER10],
|
3016 | 827df9f3 | balrog | omap_findclk(s, "core_gpt10_clk"),
|
3017 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3018 | 827df9f3 | balrog | s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), |
3019 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER11],
|
3020 | 827df9f3 | balrog | omap_findclk(s, "core_gpt11_clk"),
|
3021 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3022 | 827df9f3 | balrog | s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), |
3023 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER12],
|
3024 | 827df9f3 | balrog | omap_findclk(s, "core_gpt12_clk"),
|
3025 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3026 | 827df9f3 | balrog | |
3027 | 827df9f3 | balrog | omap_tap_init(omap_l4ta(s->l4, 2), s);
|
3028 | 827df9f3 | balrog | |
3029 | 011d87d0 | cmchao | s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
|
3030 | 827df9f3 | balrog | omap_findclk(s, "clk32-kHz"),
|
3031 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3032 | 827df9f3 | balrog | |
3033 | 827df9f3 | balrog | s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5), |
3034 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
|
3035 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_I2C1_TX], |
3036 | 827df9f3 | balrog | omap_findclk(s, "i2c1.fclk"),
|
3037 | 827df9f3 | balrog | omap_findclk(s, "i2c1.iclk"));
|
3038 | 827df9f3 | balrog | s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6), |
3039 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
|
3040 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_I2C2_TX], |
3041 | 827df9f3 | balrog | omap_findclk(s, "i2c2.fclk"),
|
3042 | 827df9f3 | balrog | omap_findclk(s, "i2c2.iclk"));
|
3043 | 827df9f3 | balrog | |
3044 | 827df9f3 | balrog | gpio_clks[0] = omap_findclk(s, "gpio1_dbclk"); |
3045 | 827df9f3 | balrog | gpio_clks[1] = omap_findclk(s, "gpio2_dbclk"); |
3046 | 827df9f3 | balrog | gpio_clks[2] = omap_findclk(s, "gpio3_dbclk"); |
3047 | 827df9f3 | balrog | gpio_clks[3] = omap_findclk(s, "gpio4_dbclk"); |
3048 | 827df9f3 | balrog | s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
|
3049 | 827df9f3 | balrog | &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
|
3050 | 827df9f3 | balrog | gpio_clks, omap_findclk(s, "gpio_iclk"), 4); |
3051 | 827df9f3 | balrog | |
3052 | 827df9f3 | balrog | s->sdrc = omap_sdrc_init(0x68009000);
|
3053 | 827df9f3 | balrog | s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]); |
3054 | 827df9f3 | balrog | |
3055 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_SD, 0, 0); |
3056 | 751c6a17 | Gerd Hoffmann | if (!dinfo) {
|
3057 | 827df9f3 | balrog | fprintf(stderr, "qemu: missing SecureDigital device\n");
|
3058 | 827df9f3 | balrog | exit(1);
|
3059 | 827df9f3 | balrog | } |
3060 | 751c6a17 | Gerd Hoffmann | s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
|
3061 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_MMC_IRQ],
|
3062 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_MMC1_TX], |
3063 | 827df9f3 | balrog | omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); |
3064 | 827df9f3 | balrog | |
3065 | 827df9f3 | balrog | s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, |
3066 | 99570a40 | balrog | s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
|
3067 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_SPI1_TX0], |
3068 | 827df9f3 | balrog | omap_findclk(s, "spi1_fclk"),
|
3069 | 827df9f3 | balrog | omap_findclk(s, "spi1_iclk"));
|
3070 | 827df9f3 | balrog | s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, |
3071 | 99570a40 | balrog | s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
|
3072 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_SPI2_TX0], |
3073 | 827df9f3 | balrog | omap_findclk(s, "spi2_fclk"),
|
3074 | 827df9f3 | balrog | omap_findclk(s, "spi2_iclk"));
|
3075 | 827df9f3 | balrog | |
3076 | 3023f332 | aliguori | s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, |
3077 | 827df9f3 | balrog | /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
|
3078 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
|
3079 | 827df9f3 | balrog | omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), |
3080 | 827df9f3 | balrog | omap_findclk(s, "dss_54m_clk"),
|
3081 | 827df9f3 | balrog | omap_findclk(s, "dss_l3_iclk"),
|
3082 | 827df9f3 | balrog | omap_findclk(s, "dss_l4_iclk"));
|
3083 | 827df9f3 | balrog | |
3084 | 54585ffe | balrog | omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000, |
3085 | 54585ffe | balrog | s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"), |
3086 | 54585ffe | balrog | serial_hds[0] && serial_hds[1] && serial_hds[2] ? |
3087 | b9d38e95 | Blue Swirl | serial_hds[3] : NULL); |
3088 | 54585ffe | balrog | |
3089 | 99570a40 | balrog | s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
|
3090 | 99570a40 | balrog | s->irq[0][OMAP_INT_24XX_EAC_IRQ],
|
3091 | 99570a40 | balrog | /* Ten consecutive lines */
|
3092 | 99570a40 | balrog | &s->drq[OMAP24XX_DMA_EAC_AC_RD], |
3093 | 99570a40 | balrog | omap_findclk(s, "func_96m_clk"),
|
3094 | 99570a40 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3095 | 99570a40 | balrog | |
3096 | 827df9f3 | balrog | /* All register mappings (includin those not currenlty implemented):
|
3097 | 827df9f3 | balrog | * SystemControlMod 48000000 - 48000fff
|
3098 | 827df9f3 | balrog | * SystemControlL4 48001000 - 48001fff
|
3099 | 827df9f3 | balrog | * 32kHz Timer Mod 48004000 - 48004fff
|
3100 | 827df9f3 | balrog | * 32kHz Timer L4 48005000 - 48005fff
|
3101 | 827df9f3 | balrog | * PRCM ModA 48008000 - 480087ff
|
3102 | 827df9f3 | balrog | * PRCM ModB 48008800 - 48008fff
|
3103 | 827df9f3 | balrog | * PRCM L4 48009000 - 48009fff
|
3104 | 827df9f3 | balrog | * TEST-BCM Mod 48012000 - 48012fff
|
3105 | 827df9f3 | balrog | * TEST-BCM L4 48013000 - 48013fff
|
3106 | 827df9f3 | balrog | * TEST-TAP Mod 48014000 - 48014fff
|
3107 | 827df9f3 | balrog | * TEST-TAP L4 48015000 - 48015fff
|
3108 | 827df9f3 | balrog | * GPIO1 Mod 48018000 - 48018fff
|
3109 | 827df9f3 | balrog | * GPIO Top 48019000 - 48019fff
|
3110 | 827df9f3 | balrog | * GPIO2 Mod 4801a000 - 4801afff
|
3111 | 827df9f3 | balrog | * GPIO L4 4801b000 - 4801bfff
|
3112 | 827df9f3 | balrog | * GPIO3 Mod 4801c000 - 4801cfff
|
3113 | 827df9f3 | balrog | * GPIO4 Mod 4801e000 - 4801efff
|
3114 | 827df9f3 | balrog | * WDTIMER1 Mod 48020000 - 48010fff
|
3115 | 827df9f3 | balrog | * WDTIMER Top 48021000 - 48011fff
|
3116 | 827df9f3 | balrog | * WDTIMER2 Mod 48022000 - 48012fff
|
3117 | 827df9f3 | balrog | * WDTIMER L4 48023000 - 48013fff
|
3118 | 827df9f3 | balrog | * WDTIMER3 Mod 48024000 - 48014fff
|
3119 | 827df9f3 | balrog | * WDTIMER3 L4 48025000 - 48015fff
|
3120 | 827df9f3 | balrog | * WDTIMER4 Mod 48026000 - 48016fff
|
3121 | 827df9f3 | balrog | * WDTIMER4 L4 48027000 - 48017fff
|
3122 | 827df9f3 | balrog | * GPTIMER1 Mod 48028000 - 48018fff
|
3123 | 827df9f3 | balrog | * GPTIMER1 L4 48029000 - 48019fff
|
3124 | 827df9f3 | balrog | * GPTIMER2 Mod 4802a000 - 4801afff
|
3125 | 827df9f3 | balrog | * GPTIMER2 L4 4802b000 - 4801bfff
|
3126 | 827df9f3 | balrog | * L4-Config AP 48040000 - 480407ff
|
3127 | 827df9f3 | balrog | * L4-Config IP 48040800 - 48040fff
|
3128 | 827df9f3 | balrog | * L4-Config LA 48041000 - 48041fff
|
3129 | 827df9f3 | balrog | * ARM11ETB Mod 48048000 - 48049fff
|
3130 | 827df9f3 | balrog | * ARM11ETB L4 4804a000 - 4804afff
|
3131 | 827df9f3 | balrog | * DISPLAY Top 48050000 - 480503ff
|
3132 | 827df9f3 | balrog | * DISPLAY DISPC 48050400 - 480507ff
|
3133 | 827df9f3 | balrog | * DISPLAY RFBI 48050800 - 48050bff
|
3134 | 827df9f3 | balrog | * DISPLAY VENC 48050c00 - 48050fff
|
3135 | 827df9f3 | balrog | * DISPLAY L4 48051000 - 48051fff
|
3136 | 827df9f3 | balrog | * CAMERA Top 48052000 - 480523ff
|
3137 | 827df9f3 | balrog | * CAMERA core 48052400 - 480527ff
|
3138 | 827df9f3 | balrog | * CAMERA DMA 48052800 - 48052bff
|
3139 | 827df9f3 | balrog | * CAMERA MMU 48052c00 - 48052fff
|
3140 | 827df9f3 | balrog | * CAMERA L4 48053000 - 48053fff
|
3141 | 827df9f3 | balrog | * SDMA Mod 48056000 - 48056fff
|
3142 | 827df9f3 | balrog | * SDMA L4 48057000 - 48057fff
|
3143 | 827df9f3 | balrog | * SSI Top 48058000 - 48058fff
|
3144 | 827df9f3 | balrog | * SSI GDD 48059000 - 48059fff
|
3145 | 827df9f3 | balrog | * SSI Port1 4805a000 - 4805afff
|
3146 | 827df9f3 | balrog | * SSI Port2 4805b000 - 4805bfff
|
3147 | 827df9f3 | balrog | * SSI L4 4805c000 - 4805cfff
|
3148 | 827df9f3 | balrog | * USB Mod 4805e000 - 480fefff
|
3149 | 827df9f3 | balrog | * USB L4 4805f000 - 480fffff
|
3150 | 827df9f3 | balrog | * WIN_TRACER1 Mod 48060000 - 48060fff
|
3151 | 827df9f3 | balrog | * WIN_TRACER1 L4 48061000 - 48061fff
|
3152 | 827df9f3 | balrog | * WIN_TRACER2 Mod 48062000 - 48062fff
|
3153 | 827df9f3 | balrog | * WIN_TRACER2 L4 48063000 - 48063fff
|
3154 | 827df9f3 | balrog | * WIN_TRACER3 Mod 48064000 - 48064fff
|
3155 | 827df9f3 | balrog | * WIN_TRACER3 L4 48065000 - 48065fff
|
3156 | 827df9f3 | balrog | * WIN_TRACER4 Top 48066000 - 480660ff
|
3157 | 827df9f3 | balrog | * WIN_TRACER4 ETT 48066100 - 480661ff
|
3158 | 827df9f3 | balrog | * WIN_TRACER4 WT 48066200 - 480662ff
|
3159 | 827df9f3 | balrog | * WIN_TRACER4 L4 48067000 - 48067fff
|
3160 | 827df9f3 | balrog | * XTI Mod 48068000 - 48068fff
|
3161 | 827df9f3 | balrog | * XTI L4 48069000 - 48069fff
|
3162 | 827df9f3 | balrog | * UART1 Mod 4806a000 - 4806afff
|
3163 | 827df9f3 | balrog | * UART1 L4 4806b000 - 4806bfff
|
3164 | 827df9f3 | balrog | * UART2 Mod 4806c000 - 4806cfff
|
3165 | 827df9f3 | balrog | * UART2 L4 4806d000 - 4806dfff
|
3166 | 827df9f3 | balrog | * UART3 Mod 4806e000 - 4806efff
|
3167 | 827df9f3 | balrog | * UART3 L4 4806f000 - 4806ffff
|
3168 | 827df9f3 | balrog | * I2C1 Mod 48070000 - 48070fff
|
3169 | 827df9f3 | balrog | * I2C1 L4 48071000 - 48071fff
|
3170 | 827df9f3 | balrog | * I2C2 Mod 48072000 - 48072fff
|
3171 | 827df9f3 | balrog | * I2C2 L4 48073000 - 48073fff
|
3172 | 827df9f3 | balrog | * McBSP1 Mod 48074000 - 48074fff
|
3173 | 827df9f3 | balrog | * McBSP1 L4 48075000 - 48075fff
|
3174 | 827df9f3 | balrog | * McBSP2 Mod 48076000 - 48076fff
|
3175 | 827df9f3 | balrog | * McBSP2 L4 48077000 - 48077fff
|
3176 | 827df9f3 | balrog | * GPTIMER3 Mod 48078000 - 48078fff
|
3177 | 827df9f3 | balrog | * GPTIMER3 L4 48079000 - 48079fff
|
3178 | 827df9f3 | balrog | * GPTIMER4 Mod 4807a000 - 4807afff
|
3179 | 827df9f3 | balrog | * GPTIMER4 L4 4807b000 - 4807bfff
|
3180 | 827df9f3 | balrog | * GPTIMER5 Mod 4807c000 - 4807cfff
|
3181 | 827df9f3 | balrog | * GPTIMER5 L4 4807d000 - 4807dfff
|
3182 | 827df9f3 | balrog | * GPTIMER6 Mod 4807e000 - 4807efff
|
3183 | 827df9f3 | balrog | * GPTIMER6 L4 4807f000 - 4807ffff
|
3184 | 827df9f3 | balrog | * GPTIMER7 Mod 48080000 - 48080fff
|
3185 | 827df9f3 | balrog | * GPTIMER7 L4 48081000 - 48081fff
|
3186 | 827df9f3 | balrog | * GPTIMER8 Mod 48082000 - 48082fff
|
3187 | 827df9f3 | balrog | * GPTIMER8 L4 48083000 - 48083fff
|
3188 | 827df9f3 | balrog | * GPTIMER9 Mod 48084000 - 48084fff
|
3189 | 827df9f3 | balrog | * GPTIMER9 L4 48085000 - 48085fff
|
3190 | 827df9f3 | balrog | * GPTIMER10 Mod 48086000 - 48086fff
|
3191 | 827df9f3 | balrog | * GPTIMER10 L4 48087000 - 48087fff
|
3192 | 827df9f3 | balrog | * GPTIMER11 Mod 48088000 - 48088fff
|
3193 | 827df9f3 | balrog | * GPTIMER11 L4 48089000 - 48089fff
|
3194 | 827df9f3 | balrog | * GPTIMER12 Mod 4808a000 - 4808afff
|
3195 | 827df9f3 | balrog | * GPTIMER12 L4 4808b000 - 4808bfff
|
3196 | 827df9f3 | balrog | * EAC Mod 48090000 - 48090fff
|
3197 | 827df9f3 | balrog | * EAC L4 48091000 - 48091fff
|
3198 | 827df9f3 | balrog | * FAC Mod 48092000 - 48092fff
|
3199 | 827df9f3 | balrog | * FAC L4 48093000 - 48093fff
|
3200 | 827df9f3 | balrog | * MAILBOX Mod 48094000 - 48094fff
|
3201 | 827df9f3 | balrog | * MAILBOX L4 48095000 - 48095fff
|
3202 | 827df9f3 | balrog | * SPI1 Mod 48098000 - 48098fff
|
3203 | 827df9f3 | balrog | * SPI1 L4 48099000 - 48099fff
|
3204 | 827df9f3 | balrog | * SPI2 Mod 4809a000 - 4809afff
|
3205 | 827df9f3 | balrog | * SPI2 L4 4809b000 - 4809bfff
|
3206 | 827df9f3 | balrog | * MMC/SDIO Mod 4809c000 - 4809cfff
|
3207 | 827df9f3 | balrog | * MMC/SDIO L4 4809d000 - 4809dfff
|
3208 | 827df9f3 | balrog | * MS_PRO Mod 4809e000 - 4809efff
|
3209 | 827df9f3 | balrog | * MS_PRO L4 4809f000 - 4809ffff
|
3210 | 827df9f3 | balrog | * RNG Mod 480a0000 - 480a0fff
|
3211 | 827df9f3 | balrog | * RNG L4 480a1000 - 480a1fff
|
3212 | 827df9f3 | balrog | * DES3DES Mod 480a2000 - 480a2fff
|
3213 | 827df9f3 | balrog | * DES3DES L4 480a3000 - 480a3fff
|
3214 | 827df9f3 | balrog | * SHA1MD5 Mod 480a4000 - 480a4fff
|
3215 | 827df9f3 | balrog | * SHA1MD5 L4 480a5000 - 480a5fff
|
3216 | 827df9f3 | balrog | * AES Mod 480a6000 - 480a6fff
|
3217 | 827df9f3 | balrog | * AES L4 480a7000 - 480a7fff
|
3218 | 827df9f3 | balrog | * PKA Mod 480a8000 - 480a9fff
|
3219 | 827df9f3 | balrog | * PKA L4 480aa000 - 480aafff
|
3220 | 827df9f3 | balrog | * MG Mod 480b0000 - 480b0fff
|
3221 | 827df9f3 | balrog | * MG L4 480b1000 - 480b1fff
|
3222 | 827df9f3 | balrog | * HDQ/1-wire Mod 480b2000 - 480b2fff
|
3223 | 827df9f3 | balrog | * HDQ/1-wire L4 480b3000 - 480b3fff
|
3224 | 827df9f3 | balrog | * MPU interrupt 480fe000 - 480fefff
|
3225 | 54585ffe | balrog | * STI channel base 54000000 - 5400ffff
|
3226 | 827df9f3 | balrog | * IVA RAM 5c000000 - 5c01ffff
|
3227 | 827df9f3 | balrog | * IVA ROM 5c020000 - 5c027fff
|
3228 | 827df9f3 | balrog | * IMG_BUF_A 5c040000 - 5c040fff
|
3229 | 827df9f3 | balrog | * IMG_BUF_B 5c042000 - 5c042fff
|
3230 | 827df9f3 | balrog | * VLCDS 5c048000 - 5c0487ff
|
3231 | 827df9f3 | balrog | * IMX_COEF 5c049000 - 5c04afff
|
3232 | 827df9f3 | balrog | * IMX_CMD 5c051000 - 5c051fff
|
3233 | 827df9f3 | balrog | * VLCDQ 5c053000 - 5c0533ff
|
3234 | 827df9f3 | balrog | * VLCDH 5c054000 - 5c054fff
|
3235 | 827df9f3 | balrog | * SEQ_CMD 5c055000 - 5c055fff
|
3236 | 827df9f3 | balrog | * IMX_REG 5c056000 - 5c0560ff
|
3237 | 827df9f3 | balrog | * VLCD_REG 5c056100 - 5c0561ff
|
3238 | 827df9f3 | balrog | * SEQ_REG 5c056200 - 5c0562ff
|
3239 | 827df9f3 | balrog | * IMG_BUF_REG 5c056300 - 5c0563ff
|
3240 | 827df9f3 | balrog | * SEQIRQ_REG 5c056400 - 5c0564ff
|
3241 | 827df9f3 | balrog | * OCP_REG 5c060000 - 5c060fff
|
3242 | 827df9f3 | balrog | * SYSC_REG 5c070000 - 5c070fff
|
3243 | 827df9f3 | balrog | * MMU_REG 5d000000 - 5d000fff
|
3244 | 827df9f3 | balrog | * sDMA R 68000400 - 680005ff
|
3245 | 827df9f3 | balrog | * sDMA W 68000600 - 680007ff
|
3246 | 827df9f3 | balrog | * Display Control 68000800 - 680009ff
|
3247 | 827df9f3 | balrog | * DSP subsystem 68000a00 - 68000bff
|
3248 | 827df9f3 | balrog | * MPU subsystem 68000c00 - 68000dff
|
3249 | 827df9f3 | balrog | * IVA subsystem 68001000 - 680011ff
|
3250 | 827df9f3 | balrog | * USB 68001200 - 680013ff
|
3251 | 827df9f3 | balrog | * Camera 68001400 - 680015ff
|
3252 | 827df9f3 | balrog | * VLYNQ (firewall) 68001800 - 68001bff
|
3253 | 827df9f3 | balrog | * VLYNQ 68001e00 - 68001fff
|
3254 | 827df9f3 | balrog | * SSI 68002000 - 680021ff
|
3255 | 827df9f3 | balrog | * L4 68002400 - 680025ff
|
3256 | 827df9f3 | balrog | * DSP (firewall) 68002800 - 68002bff
|
3257 | 827df9f3 | balrog | * DSP subsystem 68002e00 - 68002fff
|
3258 | 827df9f3 | balrog | * IVA (firewall) 68003000 - 680033ff
|
3259 | 827df9f3 | balrog | * IVA 68003600 - 680037ff
|
3260 | 827df9f3 | balrog | * GFX 68003a00 - 68003bff
|
3261 | 827df9f3 | balrog | * CMDWR emulation 68003c00 - 68003dff
|
3262 | 827df9f3 | balrog | * SMS 68004000 - 680041ff
|
3263 | 827df9f3 | balrog | * OCM 68004200 - 680043ff
|
3264 | 827df9f3 | balrog | * GPMC 68004400 - 680045ff
|
3265 | 827df9f3 | balrog | * RAM (firewall) 68005000 - 680053ff
|
3266 | 827df9f3 | balrog | * RAM (err login) 68005400 - 680057ff
|
3267 | 827df9f3 | balrog | * ROM (firewall) 68005800 - 68005bff
|
3268 | 827df9f3 | balrog | * ROM (err login) 68005c00 - 68005fff
|
3269 | 827df9f3 | balrog | * GPMC (firewall) 68006000 - 680063ff
|
3270 | 827df9f3 | balrog | * GPMC (err login) 68006400 - 680067ff
|
3271 | 827df9f3 | balrog | * SMS (err login) 68006c00 - 68006fff
|
3272 | 827df9f3 | balrog | * SMS registers 68008000 - 68008fff
|
3273 | 827df9f3 | balrog | * SDRC registers 68009000 - 68009fff
|
3274 | 827df9f3 | balrog | * GPMC registers 6800a000 6800afff
|
3275 | 827df9f3 | balrog | */
|
3276 | 827df9f3 | balrog | |
3277 | a08d4367 | Jan Kiszka | qemu_register_reset(omap2_mpu_reset, s); |
3278 | 827df9f3 | balrog | |
3279 | 827df9f3 | balrog | return s;
|
3280 | 827df9f3 | balrog | } |