Revision 0bf43016 hw/omap2.c
| b/hw/omap2.c | ||
|---|---|---|
| 2844 | 2844 |
return s; |
| 2845 | 2845 |
} |
| 2846 | 2846 |
|
| 2847 |
/* SDRAM Controller Subsystem */ |
|
| 2848 |
struct omap_sdrc_s {
|
|
| 2849 |
uint8_t config; |
|
| 2850 |
}; |
|
| 2851 |
|
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| 2852 |
static void omap_sdrc_reset(struct omap_sdrc_s *s) |
|
| 2853 |
{
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| 2854 |
s->config = 0x10; |
|
| 2855 |
} |
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| 2856 |
|
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| 2857 |
static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) |
|
| 2858 |
{
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| 2859 |
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
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| 2860 |
|
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| 2861 |
switch (addr) {
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| 2862 |
case 0x00: /* SDRC_REVISION */ |
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| 2863 |
return 0x20; |
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| 2864 |
|
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| 2865 |
case 0x10: /* SDRC_SYSCONFIG */ |
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| 2866 |
return s->config; |
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| 2867 |
|
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| 2868 |
case 0x14: /* SDRC_SYSSTATUS */ |
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| 2869 |
return 1; /* RESETDONE */ |
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| 2870 |
|
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| 2871 |
case 0x40: /* SDRC_CS_CFG */ |
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| 2872 |
case 0x44: /* SDRC_SHARING */ |
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| 2873 |
case 0x48: /* SDRC_ERR_ADDR */ |
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| 2874 |
case 0x4c: /* SDRC_ERR_TYPE */ |
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| 2875 |
case 0x60: /* SDRC_DLLA_SCTRL */ |
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| 2876 |
case 0x64: /* SDRC_DLLA_STATUS */ |
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| 2877 |
case 0x68: /* SDRC_DLLB_CTRL */ |
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| 2878 |
case 0x6c: /* SDRC_DLLB_STATUS */ |
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| 2879 |
case 0x70: /* SDRC_POWER */ |
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| 2880 |
case 0x80: /* SDRC_MCFG_0 */ |
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| 2881 |
case 0x84: /* SDRC_MR_0 */ |
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| 2882 |
case 0x88: /* SDRC_EMR1_0 */ |
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| 2883 |
case 0x8c: /* SDRC_EMR2_0 */ |
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| 2884 |
case 0x90: /* SDRC_EMR3_0 */ |
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| 2885 |
case 0x94: /* SDRC_DCDL1_CTRL */ |
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| 2886 |
case 0x98: /* SDRC_DCDL2_CTRL */ |
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| 2887 |
case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
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| 2888 |
case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
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| 2889 |
case 0xa4: /* SDRC_RFR_CTRL_0 */ |
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| 2890 |
case 0xa8: /* SDRC_MANUAL_0 */ |
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| 2891 |
case 0xb0: /* SDRC_MCFG_1 */ |
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| 2892 |
case 0xb4: /* SDRC_MR_1 */ |
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| 2893 |
case 0xb8: /* SDRC_EMR1_1 */ |
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| 2894 |
case 0xbc: /* SDRC_EMR2_1 */ |
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| 2895 |
case 0xc0: /* SDRC_EMR3_1 */ |
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| 2896 |
case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
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| 2897 |
case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
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| 2898 |
case 0xd4: /* SDRC_RFR_CTRL_1 */ |
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| 2899 |
case 0xd8: /* SDRC_MANUAL_1 */ |
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| 2900 |
return 0x00; |
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| 2901 |
} |
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| 2902 |
|
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| 2903 |
OMAP_BAD_REG(addr); |
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| 2904 |
return 0; |
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| 2905 |
} |
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| 2906 |
|
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| 2907 |
static void omap_sdrc_write(void *opaque, target_phys_addr_t addr, |
|
| 2908 |
uint32_t value) |
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| 2909 |
{
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| 2910 |
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
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| 2911 |
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| 2912 |
switch (addr) {
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| 2913 |
case 0x00: /* SDRC_REVISION */ |
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| 2914 |
case 0x14: /* SDRC_SYSSTATUS */ |
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| 2915 |
case 0x48: /* SDRC_ERR_ADDR */ |
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| 2916 |
case 0x64: /* SDRC_DLLA_STATUS */ |
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| 2917 |
case 0x6c: /* SDRC_DLLB_STATUS */ |
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| 2918 |
OMAP_RO_REG(addr); |
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| 2919 |
return; |
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| 2920 |
|
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| 2921 |
case 0x10: /* SDRC_SYSCONFIG */ |
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| 2922 |
if ((value >> 3) != 0x2) |
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| 2923 |
fprintf(stderr, "%s: bad SDRAM idle mode %i\n", |
|
| 2924 |
__FUNCTION__, value >> 3); |
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| 2925 |
if (value & 2) |
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| 2926 |
omap_sdrc_reset(s); |
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| 2927 |
s->config = value & 0x18; |
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| 2928 |
break; |
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| 2929 |
|
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| 2930 |
case 0x40: /* SDRC_CS_CFG */ |
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| 2931 |
case 0x44: /* SDRC_SHARING */ |
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| 2932 |
case 0x4c: /* SDRC_ERR_TYPE */ |
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| 2933 |
case 0x60: /* SDRC_DLLA_SCTRL */ |
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| 2934 |
case 0x68: /* SDRC_DLLB_CTRL */ |
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| 2935 |
case 0x70: /* SDRC_POWER */ |
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| 2936 |
case 0x80: /* SDRC_MCFG_0 */ |
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| 2937 |
case 0x84: /* SDRC_MR_0 */ |
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| 2938 |
case 0x88: /* SDRC_EMR1_0 */ |
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| 2939 |
case 0x8c: /* SDRC_EMR2_0 */ |
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| 2940 |
case 0x90: /* SDRC_EMR3_0 */ |
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| 2941 |
case 0x94: /* SDRC_DCDL1_CTRL */ |
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| 2942 |
case 0x98: /* SDRC_DCDL2_CTRL */ |
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| 2943 |
case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
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| 2944 |
case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
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| 2945 |
case 0xa4: /* SDRC_RFR_CTRL_0 */ |
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| 2946 |
case 0xa8: /* SDRC_MANUAL_0 */ |
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| 2947 |
case 0xb0: /* SDRC_MCFG_1 */ |
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| 2948 |
case 0xb4: /* SDRC_MR_1 */ |
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| 2949 |
case 0xb8: /* SDRC_EMR1_1 */ |
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| 2950 |
case 0xbc: /* SDRC_EMR2_1 */ |
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| 2951 |
case 0xc0: /* SDRC_EMR3_1 */ |
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| 2952 |
case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
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| 2953 |
case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
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| 2954 |
case 0xd4: /* SDRC_RFR_CTRL_1 */ |
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| 2955 |
case 0xd8: /* SDRC_MANUAL_1 */ |
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| 2956 |
break; |
|
| 2957 |
|
|
| 2958 |
default: |
|
| 2959 |
OMAP_BAD_REG(addr); |
|
| 2960 |
return; |
|
| 2961 |
} |
|
| 2962 |
} |
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| 2963 |
|
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| 2964 |
static CPUReadMemoryFunc * const omap_sdrc_readfn[] = {
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|
| 2965 |
omap_badwidth_read32, |
|
| 2966 |
omap_badwidth_read32, |
|
| 2967 |
omap_sdrc_read, |
|
| 2968 |
}; |
|
| 2969 |
|
|
| 2970 |
static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
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| 2971 |
omap_badwidth_write32, |
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| 2972 |
omap_badwidth_write32, |
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| 2973 |
omap_sdrc_write, |
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| 2974 |
}; |
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| 2975 |
|
|
| 2976 |
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base) |
|
| 2977 |
{
|
|
| 2978 |
int iomemtype; |
|
| 2979 |
struct omap_sdrc_s *s = (struct omap_sdrc_s *) |
|
| 2980 |
qemu_mallocz(sizeof(struct omap_sdrc_s)); |
|
| 2981 |
|
|
| 2982 |
omap_sdrc_reset(s); |
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| 2983 |
|
|
| 2984 |
iomemtype = cpu_register_io_memory(omap_sdrc_readfn, |
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| 2985 |
omap_sdrc_writefn, s); |
|
| 2986 |
cpu_register_physical_memory(base, 0x1000, iomemtype); |
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| 2987 |
|
|
| 2988 |
return s; |
|
| 2989 |
} |
|
| 2990 |
|
|
| 2991 | 2847 |
/* General chip reset */ |
| 2992 | 2848 |
static void omap2_mpu_reset(void *opaque) |
| 2993 | 2849 |
{
|
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