Revision 0c45d3d4

b/gdbstub.c
1462 1462

  
1463 1463
    return r;
1464 1464
}
1465
#elif defined (TARGET_LM32)
1466

  
1467
#include "hw/lm32_pic.h"
1468
#define NUM_CORE_REGS (32 + 7)
1469

  
1470
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1471
{
1472
    if (n < 32) {
1473
        GET_REG32(env->regs[n]);
1474
    } else {
1475
        switch (n) {
1476
        case 32:
1477
            GET_REG32(env->pc);
1478
            break;
1479
        /* FIXME: put in right exception ID */
1480
        case 33:
1481
            GET_REG32(0);
1482
            break;
1483
        case 34:
1484
            GET_REG32(env->eba);
1485
            break;
1486
        case 35:
1487
            GET_REG32(env->deba);
1488
            break;
1489
        case 36:
1490
            GET_REG32(env->ie);
1491
            break;
1492
        case 37:
1493
            GET_REG32(lm32_pic_get_im(env->pic_state));
1494
            break;
1495
        case 38:
1496
            GET_REG32(lm32_pic_get_ip(env->pic_state));
1497
            break;
1498
        }
1499
    }
1500
    return 0;
1501
}
1502

  
1503
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1504
{
1505
    uint32_t tmp;
1506

  
1507
    if (n > NUM_CORE_REGS) {
1508
        return 0;
1509
    }
1510

  
1511
    tmp = ldl_p(mem_buf);
1512

  
1513
    if (n < 32) {
1514
        env->regs[n] = tmp;
1515
    } else {
1516
        switch (n) {
1517
        case 32:
1518
            env->pc = tmp;
1519
            break;
1520
        case 34:
1521
            env->eba = tmp;
1522
            break;
1523
        case 35:
1524
            env->deba = tmp;
1525
            break;
1526
        case 36:
1527
            env->ie = tmp;
1528
            break;
1529
        case 37:
1530
            lm32_pic_set_im(env->pic_state, tmp);
1531
            break;
1532
        case 38:
1533
            lm32_pic_set_ip(env->pic_state, tmp);
1534
            break;
1535
        }
1536
    }
1537
    return 4;
1538
}
1465 1539
#else
1466 1540

  
1467 1541
#define NUM_CORE_REGS 0
......
1737 1811
#elif defined (TARGET_S390X)
1738 1812
    cpu_synchronize_state(s->c_cpu);
1739 1813
    s->c_cpu->psw.addr = pc;
1814
#elif defined (TARGET_LM32)
1815
    s->c_cpu->pc = pc;
1740 1816
#endif
1741 1817
}
1742 1818

  

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