root / hw / arm / versatilepb.c @ 0d09e41a
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/*
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* ARM Versatile Platform/Application Baseboard System emulation.
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*
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* Copyright (c) 2005-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/sysbus.h" |
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#include "hw/arm.h" |
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#include "hw/arm/devices.h" |
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#include "net/net.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/pci/pci.h" |
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#include "hw/i2c/i2c.h" |
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#include "hw/boards.h" |
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#include "sysemu/blockdev.h" |
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#include "exec/address-spaces.h" |
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#include "hw/block/flash.h" |
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#define VERSATILE_FLASH_ADDR 0x34000000 |
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#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) |
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#define VERSATILE_FLASH_SECT_SIZE (256 * 1024) |
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/* Primary interrupt controller. */
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typedef struct vpb_sic_state |
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{ |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t level; |
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uint32_t mask; |
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uint32_t pic_enable; |
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qemu_irq parent[32];
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int irq;
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} vpb_sic_state; |
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static const VMStateDescription vmstate_vpb_sic = { |
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.name = "versatilepb_sic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32(level, vpb_sic_state), |
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VMSTATE_UINT32(mask, vpb_sic_state), |
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VMSTATE_UINT32(pic_enable, vpb_sic_state), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void vpb_sic_update(vpb_sic_state *s) |
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{ |
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uint32_t flags; |
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flags = s->level & s->mask; |
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qemu_set_irq(s->parent[s->irq], flags != 0);
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} |
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static void vpb_sic_update_pic(vpb_sic_state *s) |
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{ |
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int i;
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uint32_t mask; |
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for (i = 21; i <= 30; i++) { |
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mask = 1u << i;
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if (!(s->pic_enable & mask))
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continue;
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qemu_set_irq(s->parent[i], (s->level & mask) != 0);
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} |
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} |
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static void vpb_sic_set_irq(void *opaque, int irq, int level) |
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{ |
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vpb_sic_state *s = (vpb_sic_state *)opaque; |
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if (level)
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s->level |= 1u << irq;
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else
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s->level &= ~(1u << irq);
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if (s->pic_enable & (1u << irq)) |
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qemu_set_irq(s->parent[irq], level); |
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vpb_sic_update(s); |
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} |
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static uint64_t vpb_sic_read(void *opaque, hwaddr offset, |
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unsigned size)
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{ |
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vpb_sic_state *s = (vpb_sic_state *)opaque; |
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switch (offset >> 2) { |
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case 0: /* STATUS */ |
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return s->level & s->mask;
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case 1: /* RAWSTAT */ |
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return s->level;
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case 2: /* ENABLE */ |
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return s->mask;
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case 4: /* SOFTINT */ |
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return s->level & 1; |
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case 8: /* PICENABLE */ |
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return s->pic_enable;
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default:
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printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
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static void vpb_sic_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size)
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{ |
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vpb_sic_state *s = (vpb_sic_state *)opaque; |
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switch (offset >> 2) { |
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case 2: /* ENSET */ |
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s->mask |= value; |
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break;
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case 3: /* ENCLR */ |
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s->mask &= ~value; |
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break;
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case 4: /* SOFTINTSET */ |
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if (value)
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s->mask |= 1;
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break;
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case 5: /* SOFTINTCLR */ |
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if (value)
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s->mask &= ~1u;
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break;
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case 8: /* PICENSET */ |
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s->pic_enable |= (value & 0x7fe00000);
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vpb_sic_update_pic(s); |
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break;
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case 9: /* PICENCLR */ |
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s->pic_enable &= ~value; |
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vpb_sic_update_pic(s); |
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break;
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default:
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printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
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return;
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} |
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vpb_sic_update(s); |
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} |
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static const MemoryRegionOps vpb_sic_ops = { |
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.read = vpb_sic_read, |
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.write = vpb_sic_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static int vpb_sic_init(SysBusDevice *dev) |
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{ |
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vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev); |
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int i;
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qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
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for (i = 0; i < 32; i++) { |
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sysbus_init_irq(dev, &s->parent[i]); |
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} |
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s->irq = 31;
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memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000); |
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sysbus_init_mmio(dev, &s->iomem); |
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return 0; |
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} |
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/* Board init. */
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/* The AB and PB boards both use the same core, just with different
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peripherals and expansion busses. For now we emulate a subset of the
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PB peripherals and just change the board ID. */
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static struct arm_boot_info versatile_binfo; |
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static void versatile_init(QEMUMachineInitArgs *args, int board_id) |
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{ |
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ARMCPU *cpu; |
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MemoryRegion *sysmem = get_system_memory(); |
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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qemu_irq *cpu_pic; |
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qemu_irq pic[32];
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qemu_irq sic[32];
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DeviceState *dev, *sysctl; |
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SysBusDevice *busdev; |
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DeviceState *pl041; |
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PCIBus *pci_bus; |
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NICInfo *nd; |
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i2c_bus *i2c; |
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int n;
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int done_smc = 0; |
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DriveInfo *dinfo; |
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if (!args->cpu_model) {
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args->cpu_model = "arm926";
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} |
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cpu = cpu_arm_init(args->cpu_model); |
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if (!cpu) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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} |
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memory_region_init_ram(ram, "versatile.ram", args->ram_size);
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vmstate_register_ram_global(ram); |
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/* ??? RAM should repeat to fill physical memory space. */
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/* SDRAM at address zero. */
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memory_region_add_subregion(sysmem, 0, ram);
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sysctl = qdev_create(NULL, "realview_sysctl"); |
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qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); |
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qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); |
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qdev_init_nofail(sysctl); |
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sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); |
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cpu_pic = arm_pic_init_cpu(cpu); |
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dev = sysbus_create_varargs("pl190", 0x10140000, |
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cpu_pic[ARM_PIC_CPU_IRQ], |
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cpu_pic[ARM_PIC_CPU_FIQ], NULL);
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for (n = 0; n < 32; n++) { |
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pic[n] = qdev_get_gpio_in(dev, n); |
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} |
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dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); |
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for (n = 0; n < 32; n++) { |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); |
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sic[n] = qdev_get_gpio_in(dev, n); |
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} |
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sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); |
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sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); |
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dev = qdev_create(NULL, "versatile_pci"); |
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busdev = SYS_BUS_DEVICE(dev); |
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qdev_init_nofail(dev); |
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sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */ |
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sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */ |
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sysbus_connect_irq(busdev, 0, sic[27]); |
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sysbus_connect_irq(busdev, 1, sic[28]); |
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sysbus_connect_irq(busdev, 2, sic[29]); |
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sysbus_connect_irq(busdev, 3, sic[30]); |
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pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
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/* The Versatile PCI bridge does not provide access to PCI IO space,
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so many of the qemu PCI devices are not useable. */
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for(n = 0; n < nb_nics; n++) { |
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nd = &nd_table[n]; |
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if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { |
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smc91c111_init(nd, 0x10010000, sic[25]); |
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done_smc = 1;
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} else {
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pci_nic_init_nofail(nd, "rtl8139", NULL); |
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} |
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} |
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if (usb_enabled(false)) { |
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pci_create_simple(pci_bus, -1, "pci-ohci"); |
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} |
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n = drive_get_max_bus(IF_SCSI); |
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while (n >= 0) { |
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pci_create_simple(pci_bus, -1, "lsi53c895a"); |
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n--; |
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} |
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sysbus_create_simple("pl011", 0x101f1000, pic[12]); |
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sysbus_create_simple("pl011", 0x101f2000, pic[13]); |
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sysbus_create_simple("pl011", 0x101f3000, pic[14]); |
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sysbus_create_simple("pl011", 0x10009000, sic[6]); |
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sysbus_create_simple("pl080", 0x10130000, pic[17]); |
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sysbus_create_simple("sp804", 0x101e2000, pic[4]); |
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sysbus_create_simple("sp804", 0x101e3000, pic[5]); |
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sysbus_create_simple("pl061", 0x101e4000, pic[6]); |
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sysbus_create_simple("pl061", 0x101e5000, pic[7]); |
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sysbus_create_simple("pl061", 0x101e6000, pic[8]); |
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sysbus_create_simple("pl061", 0x101e7000, pic[9]); |
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/* The versatile/PB actually has a modified Color LCD controller
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that includes hardware cursor support from the PL111. */
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dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); |
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/* Wire up the mux control signals from the SYS_CLCD register */
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qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); |
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sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); |
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sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); |
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/* Add PL031 Real Time Clock. */
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sysbus_create_simple("pl031", 0x101e8000, pic[10]); |
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dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); |
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i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
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i2c_create_slave(i2c, "ds1338", 0x68); |
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/* Add PL041 AACI Interface to the LM4549 codec */
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pl041 = qdev_create(NULL, "pl041"); |
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qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); |
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qdev_init_nofail(pl041); |
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sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); |
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sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); |
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/* Memory map for Versatile/PB: */
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/* 0x10000000 System registers. */
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/* 0x10001000 PCI controller config registers. */
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/* 0x10002000 Serial bus interface. */
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/* 0x10003000 Secondary interrupt controller. */
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/* 0x10004000 AACI (audio). */
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/* 0x10005000 MMCI0. */
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/* 0x10006000 KMI0 (keyboard). */
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/* 0x10007000 KMI1 (mouse). */
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/* 0x10008000 Character LCD Interface. */
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/* 0x10009000 UART3. */
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/* 0x1000a000 Smart card 1. */
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/* 0x1000b000 MMCI1. */
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/* 0x10010000 Ethernet. */
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/* 0x10020000 USB. */
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/* 0x10100000 SSMC. */
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/* 0x10110000 MPMC. */
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/* 0x10120000 CLCD Controller. */
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/* 0x10130000 DMA Controller. */
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/* 0x10140000 Vectored interrupt controller. */
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/* 0x101d0000 AHB Monitor Interface. */
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/* 0x101e0000 System Controller. */
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/* 0x101e1000 Watchdog Interface. */
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/* 0x101e2000 Timer 0/1. */
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/* 0x101e3000 Timer 2/3. */
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/* 0x101e4000 GPIO port 0. */
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/* 0x101e5000 GPIO port 1. */
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/* 0x101e6000 GPIO port 2. */
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/* 0x101e7000 GPIO port 3. */
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/* 0x101e8000 RTC. */
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/* 0x101f0000 Smart card 0. */
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/* 0x101f1000 UART0. */
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/* 0x101f2000 UART1. */
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/* 0x101f3000 UART2. */
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/* 0x101f4000 SSPI. */
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/* 0x34000000 NOR Flash */
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dinfo = drive_get(IF_PFLASH, 0, 0); |
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if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash", |
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VERSATILE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
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VERSATILE_FLASH_SECT_SIZE, |
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VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE, |
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4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { |
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fprintf(stderr, "qemu: Error registering flash memory.\n");
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} |
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versatile_binfo.ram_size = args->ram_size; |
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versatile_binfo.kernel_filename = args->kernel_filename; |
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versatile_binfo.kernel_cmdline = args->kernel_cmdline; |
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versatile_binfo.initrd_filename = args->initrd_filename; |
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versatile_binfo.board_id = board_id; |
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arm_load_kernel(cpu, &versatile_binfo); |
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} |
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static void vpb_init(QEMUMachineInitArgs *args) |
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{ |
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versatile_init(args, 0x183);
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} |
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static void vab_init(QEMUMachineInitArgs *args) |
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{ |
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versatile_init(args, 0x25e);
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} |
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static QEMUMachine versatilepb_machine = {
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.name = "versatilepb",
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.desc = "ARM Versatile/PB (ARM926EJ-S)",
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.init = vpb_init, |
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.block_default_type = IF_SCSI, |
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DEFAULT_MACHINE_OPTIONS, |
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}; |
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static QEMUMachine versatileab_machine = {
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.name = "versatileab",
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.desc = "ARM Versatile/AB (ARM926EJ-S)",
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.init = vab_init, |
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.block_default_type = IF_SCSI, |
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DEFAULT_MACHINE_OPTIONS, |
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}; |
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static void versatile_machine_init(void) |
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{ |
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qemu_register_machine(&versatilepb_machine); |
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qemu_register_machine(&versatileab_machine); |
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} |
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machine_init(versatile_machine_init); |
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static void vpb_sic_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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k->init = vpb_sic_init; |
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dc->no_user = 1;
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dc->vmsd = &vmstate_vpb_sic; |
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} |
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static const TypeInfo vpb_sic_info = { |
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.name = "versatilepb_sic",
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(vpb_sic_state),
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.class_init = vpb_sic_class_init, |
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}; |
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|
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static void versatilepb_register_types(void) |
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{ |
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type_register_static(&vpb_sic_info); |
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} |
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|
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type_init(versatilepb_register_types) |