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1
/*
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 * Epson S1D13744/S1D13745 (Blizzard/Hailstorm/Tornado) LCD/TV controller.
3
 *
4
 * Copyright (C) 2008 Nokia Corporation
5
 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6
 *
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 * This program is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
20

    
21
#include "qemu-common.h"
22
#include "ui/console.h"
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#include "hw/arm/devices.h"
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#include "hw/vga_int.h"
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#include "ui/pixel_ops.h"
26

    
27
typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);
28

    
29
typedef struct {
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    uint8_t reg;
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    uint32_t addr;
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    int swallow;
33

    
34
    int pll;
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    int pll_range;
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    int pll_ctrl;
37
    uint8_t pll_mode;
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    uint8_t clksel;
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    int memenable;
40
    int memrefresh;
41
    uint8_t timing[3];
42
    int priority;
43

    
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    uint8_t lcd_config;
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    int x;
46
    int y;
47
    int skipx;
48
    int skipy;
49
    uint8_t hndp;
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    uint8_t vndp;
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    uint8_t hsync;
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    uint8_t vsync;
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    uint8_t pclk;
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    uint8_t u;
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    uint8_t v;
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    uint8_t yrc[2];
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    int ix[2];
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    int iy[2];
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    int ox[2];
60
    int oy[2];
61

    
62
    int enable;
63
    int blank;
64
    int bpp;
65
    int invalidate;
66
    int mx[2];
67
    int my[2];
68
    uint8_t mode;
69
    uint8_t effect;
70
    uint8_t iformat;
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    uint8_t source;
72
    QemuConsole *con;
73
    blizzard_fn_t *line_fn_tab[2];
74
    void *fb;
75

    
76
    uint8_t hssi_config[3];
77
    uint8_t tv_config;
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    uint8_t tv_timing[4];
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    uint8_t vbi;
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    uint8_t tv_x;
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    uint8_t tv_y;
82
    uint8_t tv_test;
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    uint8_t tv_filter_config;
84
    uint8_t tv_filter_idx;
85
    uint8_t tv_filter_coeff[0x20];
86
    uint8_t border_r;
87
    uint8_t border_g;
88
    uint8_t border_b;
89
    uint8_t gamma_config;
90
    uint8_t gamma_idx;
91
    uint8_t gamma_lut[0x100];
92
    uint8_t matrix_ena;
93
    uint8_t matrix_coeff[0x12];
94
    uint8_t matrix_r;
95
    uint8_t matrix_g;
96
    uint8_t matrix_b;
97
    uint8_t pm;
98
    uint8_t status;
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    uint8_t rgbgpio_dir;
100
    uint8_t rgbgpio;
101
    uint8_t gpio_dir;
102
    uint8_t gpio;
103
    uint8_t gpio_edge[2];
104
    uint8_t gpio_irq;
105
    uint8_t gpio_pdown;
106

    
107
    struct {
108
        int x;
109
        int y;
110
        int dx;
111
        int dy;
112
        int len;
113
        int buflen;
114
        void *buf;
115
        void *data;
116
        uint16_t *ptr;
117
        int angle;
118
        int pitch;
119
        blizzard_fn_t line_fn;
120
    } data;
121
} BlizzardState;
122

    
123
/* Bytes(!) per pixel */
124
static const int blizzard_iformat_bpp[0x10] = {
125
    0,
126
    2,        /* RGB 5:6:5*/
127
    3,        /* RGB 6:6:6 mode 1 */
128
    3,        /* RGB 8:8:8 mode 1 */
129
    0, 0,
130
    4,        /* RGB 6:6:6 mode 2 */
131
    4,        /* RGB 8:8:8 mode 2 */
132
    0,        /* YUV 4:2:2 */
133
    0,        /* YUV 4:2:0 */
134
    0, 0, 0, 0, 0, 0,
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};
136

    
137
static inline void blizzard_rgb2yuv(int r, int g, int b,
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                int *y, int *u, int *v)
139
{
140
    *y = 0x10 + ((0x838 * r + 0x1022 * g + 0x322 * b) >> 13);
141
    *u = 0x80 + ((0xe0e * b - 0x04c1 * r - 0x94e * g) >> 13);
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    *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);
143
}
144

    
145
static void blizzard_window(BlizzardState *s)
146
{
147
    DisplaySurface *surface = qemu_console_surface(s->con);
148
    uint8_t *src, *dst;
149
    int bypp[2];
150
    int bypl[3];
151
    int y;
152
    blizzard_fn_t fn = s->data.line_fn;
153

    
154
    if (!fn)
155
        return;
156
    if (s->mx[0] > s->data.x)
157
        s->mx[0] = s->data.x;
158
    if (s->my[0] > s->data.y)
159
        s->my[0] = s->data.y;
160
    if (s->mx[1] < s->data.x + s->data.dx)
161
        s->mx[1] = s->data.x + s->data.dx;
162
    if (s->my[1] < s->data.y + s->data.dy)
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        s->my[1] = s->data.y + s->data.dy;
164

    
165
    bypp[0] = s->bpp;
166
    bypp[1] = surface_bytes_per_pixel(surface);
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    bypl[0] = bypp[0] * s->data.pitch;
168
    bypl[1] = bypp[1] * s->x;
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    bypl[2] = bypp[0] * s->data.dx;
170

    
171
    src = s->data.data;
172
    dst = s->fb + bypl[1] * s->data.y + bypp[1] * s->data.x;
173
    for (y = s->data.dy; y > 0; y --, src += bypl[0], dst += bypl[1])
174
        fn(dst, src, bypl[2]);
175
}
176

    
177
static int blizzard_transfer_setup(BlizzardState *s)
178
{
179
    if (s->source > 3 || !s->bpp ||
180
                    s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0])
181
        return 0;
182

    
183
    s->data.angle = s->effect & 3;
184
    s->data.line_fn = s->line_fn_tab[!!s->data.angle][s->iformat];
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    s->data.x = s->ix[0];
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    s->data.y = s->iy[0];
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    s->data.dx = s->ix[1] - s->ix[0] + 1;
188
    s->data.dy = s->iy[1] - s->iy[0] + 1;
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    s->data.len = s->bpp * s->data.dx * s->data.dy;
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    s->data.pitch = s->data.dx;
191
    if (s->data.len > s->data.buflen) {
192
        s->data.buf = g_realloc(s->data.buf, s->data.len);
193
        s->data.buflen = s->data.len;
194
    }
195
    s->data.ptr = s->data.buf;
196
    s->data.data = s->data.buf;
197
    s->data.len /= 2;
198
    return 1;
199
}
200

    
201
static void blizzard_reset(BlizzardState *s)
202
{
203
    s->reg = 0;
204
    s->swallow = 0;
205

    
206
    s->pll = 9;
207
    s->pll_range = 1;
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    s->pll_ctrl = 0x14;
209
    s->pll_mode = 0x32;
210
    s->clksel = 0x00;
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    s->memenable = 0;
212
    s->memrefresh = 0x25c;
213
    s->timing[0] = 0x3f;
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    s->timing[1] = 0x13;
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    s->timing[2] = 0x21;
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    s->priority = 0;
217

    
218
    s->lcd_config = 0x74;
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    s->x = 8;
220
    s->y = 1;
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    s->skipx = 0;
222
    s->skipy = 0;
223
    s->hndp = 3;
224
    s->vndp = 2;
225
    s->hsync = 1;
226
    s->vsync = 1;
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    s->pclk = 0x80;
228

    
229
    s->ix[0] = 0;
230
    s->ix[1] = 0;
231
    s->iy[0] = 0;
232
    s->iy[1] = 0;
233
    s->ox[0] = 0;
234
    s->ox[1] = 0;
235
    s->oy[0] = 0;
236
    s->oy[1] = 0;
237

    
238
    s->yrc[0] = 0x00;
239
    s->yrc[1] = 0x30;
240
    s->u = 0;
241
    s->v = 0;
242

    
243
    s->iformat = 3;
244
    s->source = 0;
245
    s->bpp = blizzard_iformat_bpp[s->iformat];
246

    
247
    s->hssi_config[0] = 0x00;
248
    s->hssi_config[1] = 0x00;
249
    s->hssi_config[2] = 0x01;
250
    s->tv_config = 0x00;
251
    s->tv_timing[0] = 0x00;
252
    s->tv_timing[1] = 0x00;
253
    s->tv_timing[2] = 0x00;
254
    s->tv_timing[3] = 0x00;
255
    s->vbi = 0x10;
256
    s->tv_x = 0x14;
257
    s->tv_y = 0x03;
258
    s->tv_test = 0x00;
259
    s->tv_filter_config = 0x80;
260
    s->tv_filter_idx = 0x00;
261
    s->border_r = 0x10;
262
    s->border_g = 0x80;
263
    s->border_b = 0x80;
264
    s->gamma_config = 0x00;
265
    s->gamma_idx = 0x00;
266
    s->matrix_ena = 0x00;
267
    memset(&s->matrix_coeff, 0, sizeof(s->matrix_coeff));
268
    s->matrix_r = 0x00;
269
    s->matrix_g = 0x00;
270
    s->matrix_b = 0x00;
271
    s->pm = 0x02;
272
    s->status = 0x00;
273
    s->rgbgpio_dir = 0x00;
274
    s->gpio_dir = 0x00;
275
    s->gpio_edge[0] = 0x00;
276
    s->gpio_edge[1] = 0x00;
277
    s->gpio_irq = 0x00;
278
    s->gpio_pdown = 0xff;
279
}
280

    
281
static inline void blizzard_invalidate_display(void *opaque) {
282
    BlizzardState *s = (BlizzardState *) opaque;
283

    
284
    s->invalidate = 1;
285
}
286

    
287
static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
288
{
289
    BlizzardState *s = (BlizzardState *) opaque;
290

    
291
    switch (reg) {
292
    case 0x00:        /* Revision Code */
293
        return 0xa5;
294

    
295
    case 0x02:        /* Configuration Readback */
296
        return 0x83;        /* Macrovision OK, CNF[2:0] = 3 */
297

    
298
    case 0x04:        /* PLL M-Divider */
299
        return (s->pll - 1) | (1 << 7);
300
    case 0x06:        /* PLL Lock Range Control */
301
        return s->pll_range;
302
    case 0x08:        /* PLL Lock Synthesis Control 0 */
303
        return s->pll_ctrl & 0xff;
304
    case 0x0a:        /* PLL Lock Synthesis Control 1 */
305
        return s->pll_ctrl >> 8;
306
    case 0x0c:        /* PLL Mode Control 0 */
307
        return s->pll_mode;
308

    
309
    case 0x0e:        /* Clock-Source Select */
310
        return s->clksel;
311

    
312
    case 0x10:        /* Memory Controller Activate */
313
    case 0x14:        /* Memory Controller Bank 0 Status Flag */
314
        return s->memenable;
315

    
316
    case 0x18:        /* Auto-Refresh Interval Setting 0 */
317
        return s->memrefresh & 0xff;
318
    case 0x1a:        /* Auto-Refresh Interval Setting 1 */
319
        return s->memrefresh >> 8;
320

    
321
    case 0x1c:        /* Power-On Sequence Timing Control */
322
        return s->timing[0];
323
    case 0x1e:        /* Timing Control 0 */
324
        return s->timing[1];
325
    case 0x20:        /* Timing Control 1 */
326
        return s->timing[2];
327

    
328
    case 0x24:        /* Arbitration Priority Control */
329
        return s->priority;
330

    
331
    case 0x28:        /* LCD Panel Configuration */
332
        return s->lcd_config;
333

    
334
    case 0x2a:        /* LCD Horizontal Display Width */
335
        return s->x >> 3;
336
    case 0x2c:        /* LCD Horizontal Non-display Period */
337
        return s->hndp;
338
    case 0x2e:        /* LCD Vertical Display Height 0 */
339
        return s->y & 0xff;
340
    case 0x30:        /* LCD Vertical Display Height 1 */
341
        return s->y >> 8;
342
    case 0x32:        /* LCD Vertical Non-display Period */
343
        return s->vndp;
344
    case 0x34:        /* LCD HS Pulse-width */
345
        return s->hsync;
346
    case 0x36:        /* LCd HS Pulse Start Position */
347
        return s->skipx >> 3;
348
    case 0x38:        /* LCD VS Pulse-width */
349
        return s->vsync;
350
    case 0x3a:        /* LCD VS Pulse Start Position */
351
        return s->skipy;
352

    
353
    case 0x3c:        /* PCLK Polarity */
354
        return s->pclk;
355

    
356
    case 0x3e:        /* High-speed Serial Interface Tx Configuration Port 0 */
357
        return s->hssi_config[0];
358
    case 0x40:        /* High-speed Serial Interface Tx Configuration Port 1 */
359
        return s->hssi_config[1];
360
    case 0x42:        /* High-speed Serial Interface Tx Mode */
361
        return s->hssi_config[2];
362
    case 0x44:        /* TV Display Configuration */
363
        return s->tv_config;
364
    case 0x46 ... 0x4c:        /* TV Vertical Blanking Interval Data bits */
365
        return s->tv_timing[(reg - 0x46) >> 1];
366
    case 0x4e:        /* VBI: Closed Caption / XDS Control / Status */
367
        return s->vbi;
368
    case 0x50:        /* TV Horizontal Start Position */
369
        return s->tv_x;
370
    case 0x52:        /* TV Vertical Start Position */
371
        return s->tv_y;
372
    case 0x54:        /* TV Test Pattern Setting */
373
        return s->tv_test;
374
    case 0x56:        /* TV Filter Setting */
375
        return s->tv_filter_config;
376
    case 0x58:        /* TV Filter Coefficient Index */
377
        return s->tv_filter_idx;
378
    case 0x5a:        /* TV Filter Coefficient Data */
379
        if (s->tv_filter_idx < 0x20)
380
            return s->tv_filter_coeff[s->tv_filter_idx ++];
381
        return 0;
382

    
383
    case 0x60:        /* Input YUV/RGB Translate Mode 0 */
384
        return s->yrc[0];
385
    case 0x62:        /* Input YUV/RGB Translate Mode 1 */
386
        return s->yrc[1];
387
    case 0x64:        /* U Data Fix */
388
        return s->u;
389
    case 0x66:        /* V Data Fix */
390
        return s->v;
391

    
392
    case 0x68:        /* Display Mode */
393
        return s->mode;
394

    
395
    case 0x6a:        /* Special Effects */
396
        return s->effect;
397

    
398
    case 0x6c:        /* Input Window X Start Position 0 */
399
        return s->ix[0] & 0xff;
400
    case 0x6e:        /* Input Window X Start Position 1 */
401
        return s->ix[0] >> 3;
402
    case 0x70:        /* Input Window Y Start Position 0 */
403
        return s->ix[0] & 0xff;
404
    case 0x72:        /* Input Window Y Start Position 1 */
405
        return s->ix[0] >> 3;
406
    case 0x74:        /* Input Window X End Position 0 */
407
        return s->ix[1] & 0xff;
408
    case 0x76:        /* Input Window X End Position 1 */
409
        return s->ix[1] >> 3;
410
    case 0x78:        /* Input Window Y End Position 0 */
411
        return s->ix[1] & 0xff;
412
    case 0x7a:        /* Input Window Y End Position 1 */
413
        return s->ix[1] >> 3;
414
    case 0x7c:        /* Output Window X Start Position 0 */
415
        return s->ox[0] & 0xff;
416
    case 0x7e:        /* Output Window X Start Position 1 */
417
        return s->ox[0] >> 3;
418
    case 0x80:        /* Output Window Y Start Position 0 */
419
        return s->oy[0] & 0xff;
420
    case 0x82:        /* Output Window Y Start Position 1 */
421
        return s->oy[0] >> 3;
422
    case 0x84:        /* Output Window X End Position 0 */
423
        return s->ox[1] & 0xff;
424
    case 0x86:        /* Output Window X End Position 1 */
425
        return s->ox[1] >> 3;
426
    case 0x88:        /* Output Window Y End Position 0 */
427
        return s->oy[1] & 0xff;
428
    case 0x8a:        /* Output Window Y End Position 1 */
429
        return s->oy[1] >> 3;
430

    
431
    case 0x8c:        /* Input Data Format */
432
        return s->iformat;
433
    case 0x8e:        /* Data Source Select */
434
        return s->source;
435
    case 0x90:        /* Display Memory Data Port */
436
        return 0;
437

    
438
    case 0xa8:        /* Border Color 0 */
439
        return s->border_r;
440
    case 0xaa:        /* Border Color 1 */
441
        return s->border_g;
442
    case 0xac:        /* Border Color 2 */
443
        return s->border_b;
444

    
445
    case 0xb4:        /* Gamma Correction Enable */
446
        return s->gamma_config;
447
    case 0xb6:        /* Gamma Correction Table Index */
448
        return s->gamma_idx;
449
    case 0xb8:        /* Gamma Correction Table Data */
450
        return s->gamma_lut[s->gamma_idx ++];
451

    
452
    case 0xba:        /* 3x3 Matrix Enable */
453
        return s->matrix_ena;
454
    case 0xbc ... 0xde:        /* Coefficient Registers */
455
        return s->matrix_coeff[(reg - 0xbc) >> 1];
456
    case 0xe0:        /* 3x3 Matrix Red Offset */
457
        return s->matrix_r;
458
    case 0xe2:        /* 3x3 Matrix Green Offset */
459
        return s->matrix_g;
460
    case 0xe4:        /* 3x3 Matrix Blue Offset */
461
        return s->matrix_b;
462

    
463
    case 0xe6:        /* Power-save */
464
        return s->pm;
465
    case 0xe8:        /* Non-display Period Control / Status */
466
        return s->status | (1 << 5);
467
    case 0xea:        /* RGB Interface Control */
468
        return s->rgbgpio_dir;
469
    case 0xec:        /* RGB Interface Status */
470
        return s->rgbgpio;
471
    case 0xee:        /* General-purpose IO Pins Configuration */
472
        return s->gpio_dir;
473
    case 0xf0:        /* General-purpose IO Pins Status / Control */
474
        return s->gpio;
475
    case 0xf2:        /* GPIO Positive Edge Interrupt Trigger */
476
        return s->gpio_edge[0];
477
    case 0xf4:        /* GPIO Negative Edge Interrupt Trigger */
478
        return s->gpio_edge[1];
479
    case 0xf6:        /* GPIO Interrupt Status */
480
        return s->gpio_irq;
481
    case 0xf8:        /* GPIO Pull-down Control */
482
        return s->gpio_pdown;
483

    
484
    default:
485
        fprintf(stderr, "%s: unknown register %02x\n", __FUNCTION__, reg);
486
        return 0;
487
    }
488
}
489

    
490
static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
491
{
492
    BlizzardState *s = (BlizzardState *) opaque;
493

    
494
    switch (reg) {
495
    case 0x04:        /* PLL M-Divider */
496
        s->pll = (value & 0x3f) + 1;
497
        break;
498
    case 0x06:        /* PLL Lock Range Control */
499
        s->pll_range = value & 3;
500
        break;
501
    case 0x08:        /* PLL Lock Synthesis Control 0 */
502
        s->pll_ctrl &= 0xf00;
503
        s->pll_ctrl |= (value << 0) & 0x0ff;
504
        break;
505
    case 0x0a:        /* PLL Lock Synthesis Control 1 */
506
        s->pll_ctrl &= 0x0ff;
507
        s->pll_ctrl |= (value << 8) & 0xf00;
508
        break;
509
    case 0x0c:        /* PLL Mode Control 0 */
510
        s->pll_mode = value & 0x77;
511
        if ((value & 3) == 0 || (value & 3) == 3)
512
            fprintf(stderr, "%s: wrong PLL Control bits (%i)\n",
513
                    __FUNCTION__, value & 3);
514
        break;
515

    
516
    case 0x0e:        /* Clock-Source Select */
517
        s->clksel = value & 0xff;
518
        break;
519

    
520
    case 0x10:        /* Memory Controller Activate */
521
        s->memenable = value & 1;
522
        break;
523
    case 0x14:        /* Memory Controller Bank 0 Status Flag */
524
        break;
525

    
526
    case 0x18:        /* Auto-Refresh Interval Setting 0 */
527
        s->memrefresh &= 0xf00;
528
        s->memrefresh |= (value << 0) & 0x0ff;
529
        break;
530
    case 0x1a:        /* Auto-Refresh Interval Setting 1 */
531
        s->memrefresh &= 0x0ff;
532
        s->memrefresh |= (value << 8) & 0xf00;
533
        break;
534

    
535
    case 0x1c:        /* Power-On Sequence Timing Control */
536
        s->timing[0] = value & 0x7f;
537
        break;
538
    case 0x1e:        /* Timing Control 0 */
539
        s->timing[1] = value & 0x17;
540
        break;
541
    case 0x20:        /* Timing Control 1 */
542
        s->timing[2] = value & 0x35;
543
        break;
544

    
545
    case 0x24:        /* Arbitration Priority Control */
546
        s->priority = value & 1;
547
        break;
548

    
549
    case 0x28:        /* LCD Panel Configuration */
550
        s->lcd_config = value & 0xff;
551
        if (value & (1 << 7))
552
            fprintf(stderr, "%s: data swap not supported!\n", __FUNCTION__);
553
        break;
554

    
555
    case 0x2a:        /* LCD Horizontal Display Width */
556
        s->x = value << 3;
557
        break;
558
    case 0x2c:        /* LCD Horizontal Non-display Period */
559
        s->hndp = value & 0xff;
560
        break;
561
    case 0x2e:        /* LCD Vertical Display Height 0 */
562
        s->y &= 0x300;
563
        s->y |= (value << 0) & 0x0ff;
564
        break;
565
    case 0x30:        /* LCD Vertical Display Height 1 */
566
        s->y &= 0x0ff;
567
        s->y |= (value << 8) & 0x300;
568
        break;
569
    case 0x32:        /* LCD Vertical Non-display Period */
570
        s->vndp = value & 0xff;
571
        break;
572
    case 0x34:        /* LCD HS Pulse-width */
573
        s->hsync = value & 0xff;
574
        break;
575
    case 0x36:        /* LCD HS Pulse Start Position */
576
        s->skipx = value & 0xff;
577
        break;
578
    case 0x38:        /* LCD VS Pulse-width */
579
        s->vsync = value & 0xbf;
580
        break;
581
    case 0x3a:        /* LCD VS Pulse Start Position */
582
        s->skipy = value & 0xff;
583
        break;
584

    
585
    case 0x3c:        /* PCLK Polarity */
586
        s->pclk = value & 0x82;
587
        /* Affects calculation of s->hndp, s->hsync and s->skipx.  */
588
        break;
589

    
590
    case 0x3e:        /* High-speed Serial Interface Tx Configuration Port 0 */
591
        s->hssi_config[0] = value;
592
        break;
593
    case 0x40:        /* High-speed Serial Interface Tx Configuration Port 1 */
594
        s->hssi_config[1] = value;
595
        if (((value >> 4) & 3) == 3)
596
            fprintf(stderr, "%s: Illegal active-data-links value\n",
597
                            __FUNCTION__);
598
        break;
599
    case 0x42:        /* High-speed Serial Interface Tx Mode */
600
        s->hssi_config[2] = value & 0xbd;
601
        break;
602

    
603
    case 0x44:        /* TV Display Configuration */
604
        s->tv_config = value & 0xfe;
605
        break;
606
    case 0x46 ... 0x4c:        /* TV Vertical Blanking Interval Data bits 0 */
607
        s->tv_timing[(reg - 0x46) >> 1] = value;
608
        break;
609
    case 0x4e:        /* VBI: Closed Caption / XDS Control / Status */
610
        s->vbi = value;
611
        break;
612
    case 0x50:        /* TV Horizontal Start Position */
613
        s->tv_x = value;
614
        break;
615
    case 0x52:        /* TV Vertical Start Position */
616
        s->tv_y = value & 0x7f;
617
        break;
618
    case 0x54:        /* TV Test Pattern Setting */
619
        s->tv_test = value;
620
        break;
621
    case 0x56:        /* TV Filter Setting */
622
        s->tv_filter_config = value & 0xbf;
623
        break;
624
    case 0x58:        /* TV Filter Coefficient Index */
625
        s->tv_filter_idx = value & 0x1f;
626
        break;
627
    case 0x5a:        /* TV Filter Coefficient Data */
628
        if (s->tv_filter_idx < 0x20)
629
            s->tv_filter_coeff[s->tv_filter_idx ++] = value;
630
        break;
631

    
632
    case 0x60:        /* Input YUV/RGB Translate Mode 0 */
633
        s->yrc[0] = value & 0xb0;
634
        break;
635
    case 0x62:        /* Input YUV/RGB Translate Mode 1 */
636
        s->yrc[1] = value & 0x30;
637
        break;
638
    case 0x64:        /* U Data Fix */
639
        s->u = value & 0xff;
640
        break;
641
    case 0x66:        /* V Data Fix */
642
        s->v = value & 0xff;
643
        break;
644

    
645
    case 0x68:        /* Display Mode */
646
        if ((s->mode ^ value) & 3)
647
            s->invalidate = 1;
648
        s->mode = value & 0xb7;
649
        s->enable = value & 1;
650
        s->blank = (value >> 1) & 1;
651
        if (value & (1 << 4))
652
            fprintf(stderr, "%s: Macrovision enable attempt!\n", __FUNCTION__);
653
        break;
654

    
655
    case 0x6a:        /* Special Effects */
656
        s->effect = value & 0xfb;
657
        break;
658

    
659
    case 0x6c:        /* Input Window X Start Position 0 */
660
        s->ix[0] &= 0x300;
661
        s->ix[0] |= (value << 0) & 0x0ff;
662
        break;
663
    case 0x6e:        /* Input Window X Start Position 1 */
664
        s->ix[0] &= 0x0ff;
665
        s->ix[0] |= (value << 8) & 0x300;
666
        break;
667
    case 0x70:        /* Input Window Y Start Position 0 */
668
        s->iy[0] &= 0x300;
669
        s->iy[0] |= (value << 0) & 0x0ff;
670
        break;
671
    case 0x72:        /* Input Window Y Start Position 1 */
672
        s->iy[0] &= 0x0ff;
673
        s->iy[0] |= (value << 8) & 0x300;
674
        break;
675
    case 0x74:        /* Input Window X End Position 0 */
676
        s->ix[1] &= 0x300;
677
        s->ix[1] |= (value << 0) & 0x0ff;
678
        break;
679
    case 0x76:        /* Input Window X End Position 1 */
680
        s->ix[1] &= 0x0ff;
681
        s->ix[1] |= (value << 8) & 0x300;
682
        break;
683
    case 0x78:        /* Input Window Y End Position 0 */
684
        s->iy[1] &= 0x300;
685
        s->iy[1] |= (value << 0) & 0x0ff;
686
        break;
687
    case 0x7a:        /* Input Window Y End Position 1 */
688
        s->iy[1] &= 0x0ff;
689
        s->iy[1] |= (value << 8) & 0x300;
690
        break;
691
    case 0x7c:        /* Output Window X Start Position 0 */
692
        s->ox[0] &= 0x300;
693
        s->ox[0] |= (value << 0) & 0x0ff;
694
        break;
695
    case 0x7e:        /* Output Window X Start Position 1 */
696
        s->ox[0] &= 0x0ff;
697
        s->ox[0] |= (value << 8) & 0x300;
698
        break;
699
    case 0x80:        /* Output Window Y Start Position 0 */
700
        s->oy[0] &= 0x300;
701
        s->oy[0] |= (value << 0) & 0x0ff;
702
        break;
703
    case 0x82:        /* Output Window Y Start Position 1 */
704
        s->oy[0] &= 0x0ff;
705
        s->oy[0] |= (value << 8) & 0x300;
706
        break;
707
    case 0x84:        /* Output Window X End Position 0 */
708
        s->ox[1] &= 0x300;
709
        s->ox[1] |= (value << 0) & 0x0ff;
710
        break;
711
    case 0x86:        /* Output Window X End Position 1 */
712
        s->ox[1] &= 0x0ff;
713
        s->ox[1] |= (value << 8) & 0x300;
714
        break;
715
    case 0x88:        /* Output Window Y End Position 0 */
716
        s->oy[1] &= 0x300;
717
        s->oy[1] |= (value << 0) & 0x0ff;
718
        break;
719
    case 0x8a:        /* Output Window Y End Position 1 */
720
        s->oy[1] &= 0x0ff;
721
        s->oy[1] |= (value << 8) & 0x300;
722
        break;
723

    
724
    case 0x8c:        /* Input Data Format */
725
        s->iformat = value & 0xf;
726
        s->bpp = blizzard_iformat_bpp[s->iformat];
727
        if (!s->bpp)
728
            fprintf(stderr, "%s: Illegal or unsupported input format %x\n",
729
                            __FUNCTION__, s->iformat);
730
        break;
731
    case 0x8e:        /* Data Source Select */
732
        s->source = value & 7;
733
        /* Currently all windows will be "destructive overlays".  */
734
        if ((!(s->effect & (1 << 3)) && (s->ix[0] != s->ox[0] ||
735
                                        s->iy[0] != s->oy[0] ||
736
                                        s->ix[1] != s->ox[1] ||
737
                                        s->iy[1] != s->oy[1])) ||
738
                        !((s->ix[1] - s->ix[0]) & (s->iy[1] - s->iy[0]) &
739
                          (s->ox[1] - s->ox[0]) & (s->oy[1] - s->oy[0]) & 1))
740
            fprintf(stderr, "%s: Illegal input/output window positions\n",
741
                            __FUNCTION__);
742

    
743
        blizzard_transfer_setup(s);
744
        break;
745

    
746
    case 0x90:        /* Display Memory Data Port */
747
        if (!s->data.len && !blizzard_transfer_setup(s))
748
            break;
749

    
750
        *s->data.ptr ++ = value;
751
        if (-- s->data.len == 0)
752
            blizzard_window(s);
753
        break;
754

    
755
    case 0xa8:        /* Border Color 0 */
756
        s->border_r = value;
757
        break;
758
    case 0xaa:        /* Border Color 1 */
759
        s->border_g = value;
760
        break;
761
    case 0xac:        /* Border Color 2 */
762
        s->border_b = value;
763
        break;
764

    
765
    case 0xb4:        /* Gamma Correction Enable */
766
        s->gamma_config = value & 0x87;
767
        break;
768
    case 0xb6:        /* Gamma Correction Table Index */
769
        s->gamma_idx = value;
770
        break;
771
    case 0xb8:        /* Gamma Correction Table Data */
772
        s->gamma_lut[s->gamma_idx ++] = value;
773
        break;
774

    
775
    case 0xba:        /* 3x3 Matrix Enable */
776
        s->matrix_ena = value & 1;
777
        break;
778
    case 0xbc ... 0xde:        /* Coefficient Registers */
779
        s->matrix_coeff[(reg - 0xbc) >> 1] = value & ((reg & 2) ? 0x80 : 0xff);
780
        break;
781
    case 0xe0:        /* 3x3 Matrix Red Offset */
782
        s->matrix_r = value;
783
        break;
784
    case 0xe2:        /* 3x3 Matrix Green Offset */
785
        s->matrix_g = value;
786
        break;
787
    case 0xe4:        /* 3x3 Matrix Blue Offset */
788
        s->matrix_b = value;
789
        break;
790

    
791
    case 0xe6:        /* Power-save */
792
        s->pm = value & 0x83;
793
        if (value & s->mode & 1)
794
            fprintf(stderr, "%s: The display must be disabled before entering "
795
                            "Standby Mode\n", __FUNCTION__);
796
        break;
797
    case 0xe8:        /* Non-display Period Control / Status */
798
        s->status = value & 0x1b;
799
        break;
800
    case 0xea:        /* RGB Interface Control */
801
        s->rgbgpio_dir = value & 0x8f;
802
        break;
803
    case 0xec:        /* RGB Interface Status */
804
        s->rgbgpio = value & 0xcf;
805
        break;
806
    case 0xee:        /* General-purpose IO Pins Configuration */
807
        s->gpio_dir = value;
808
        break;
809
    case 0xf0:        /* General-purpose IO Pins Status / Control */
810
        s->gpio = value;
811
        break;
812
    case 0xf2:        /* GPIO Positive Edge Interrupt Trigger */
813
        s->gpio_edge[0] = value;
814
        break;
815
    case 0xf4:        /* GPIO Negative Edge Interrupt Trigger */
816
        s->gpio_edge[1] = value;
817
        break;
818
    case 0xf6:        /* GPIO Interrupt Status */
819
        s->gpio_irq &= value;
820
        break;
821
    case 0xf8:        /* GPIO Pull-down Control */
822
        s->gpio_pdown = value;
823
        break;
824

    
825
    default:
826
        fprintf(stderr, "%s: unknown register %02x\n", __FUNCTION__, reg);
827
        break;
828
    }
829
}
830

    
831
uint16_t s1d13745_read(void *opaque, int dc)
832
{
833
    BlizzardState *s = (BlizzardState *) opaque;
834
    uint16_t value = blizzard_reg_read(s, s->reg);
835

    
836
    if (s->swallow -- > 0)
837
        return 0;
838
    if (dc)
839
        s->reg ++;
840

    
841
    return value;
842
}
843

    
844
void s1d13745_write(void *opaque, int dc, uint16_t value)
845
{
846
    BlizzardState *s = (BlizzardState *) opaque;
847

    
848
    if (s->swallow -- > 0)
849
        return;
850
    if (dc) {
851
        blizzard_reg_write(s, s->reg, value);
852

    
853
        if (s->reg != 0x90 && s->reg != 0x5a && s->reg != 0xb8)
854
            s->reg += 2;
855
    } else
856
        s->reg = value & 0xff;
857
}
858

    
859
void s1d13745_write_block(void *opaque, int dc,
860
                void *buf, size_t len, int pitch)
861
{
862
    BlizzardState *s = (BlizzardState *) opaque;
863

    
864
    while (len > 0) {
865
        if (s->reg == 0x90 && dc &&
866
                        (s->data.len || blizzard_transfer_setup(s)) &&
867
                        len >= (s->data.len << 1)) {
868
            len -= s->data.len << 1;
869
            s->data.len = 0;
870
            s->data.data = buf;
871
            if (pitch)
872
                s->data.pitch = pitch;
873
            blizzard_window(s);
874
            s->data.data = s->data.buf;
875
            continue;
876
        }
877

    
878
        s1d13745_write(opaque, dc, *(uint16_t *) buf);
879
        len -= 2;
880
        buf += 2;
881
    }
882
}
883

    
884
static void blizzard_update_display(void *opaque)
885
{
886
    BlizzardState *s = (BlizzardState *) opaque;
887
    DisplaySurface *surface = qemu_console_surface(s->con);
888
    int y, bypp, bypl, bwidth;
889
    uint8_t *src, *dst;
890

    
891
    if (!s->enable)
892
        return;
893

    
894
    if (s->x != surface_width(surface) || s->y != surface_height(surface)) {
895
        s->invalidate = 1;
896
        qemu_console_resize(s->con, s->x, s->y);
897
        surface = qemu_console_surface(s->con);
898
    }
899

    
900
    if (s->invalidate) {
901
        s->invalidate = 0;
902

    
903
        if (s->blank) {
904
            bypp = surface_bytes_per_pixel(surface);
905
            memset(surface_data(surface), 0, bypp * s->x * s->y);
906
            return;
907
        }
908

    
909
        s->mx[0] = 0;
910
        s->mx[1] = s->x;
911
        s->my[0] = 0;
912
        s->my[1] = s->y;
913
    }
914

    
915
    if (s->mx[1] <= s->mx[0])
916
        return;
917

    
918
    bypp = surface_bytes_per_pixel(surface);
919
    bypl = bypp * s->x;
920
    bwidth = bypp * (s->mx[1] - s->mx[0]);
921
    y = s->my[0];
922
    src = s->fb + bypl * y + bypp * s->mx[0];
923
    dst = surface_data(surface) + bypl * y + bypp * s->mx[0];
924
    for (; y < s->my[1]; y ++, src += bypl, dst += bypl)
925
        memcpy(dst, src, bwidth);
926

    
927
    dpy_gfx_update(s->con, s->mx[0], s->my[0],
928
                   s->mx[1] - s->mx[0], y - s->my[0]);
929

    
930
    s->mx[0] = s->x;
931
    s->mx[1] = 0;
932
    s->my[0] = s->y;
933
    s->my[1] = 0;
934
}
935

    
936
static void blizzard_screen_dump(void *opaque, const char *filename,
937
                                 bool cswitch, Error **errp)
938
{
939
    BlizzardState *s = (BlizzardState *) opaque;
940
    DisplaySurface *surface = qemu_console_surface(s->con);
941

    
942
    blizzard_update_display(opaque);
943
    if (s && surface_data(surface)) {
944
        ppm_save(filename, surface, errp);
945
    }
946
}
947

    
948
#define DEPTH 8
949
#include "hw/blizzard_template.h"
950
#define DEPTH 15
951
#include "hw/blizzard_template.h"
952
#define DEPTH 16
953
#include "hw/blizzard_template.h"
954
#define DEPTH 24
955
#include "hw/blizzard_template.h"
956
#define DEPTH 32
957
#include "hw/blizzard_template.h"
958

    
959
void *s1d13745_init(qemu_irq gpio_int)
960
{
961
    BlizzardState *s = (BlizzardState *) g_malloc0(sizeof(*s));
962
    DisplaySurface *surface;
963

    
964
    s->fb = g_malloc(0x180000);
965

    
966
    s->con = graphic_console_init(blizzard_update_display,
967
                                  blizzard_invalidate_display,
968
                                  blizzard_screen_dump, NULL, s);
969
    surface = qemu_console_surface(s->con);
970

    
971
    switch (surface_bits_per_pixel(surface)) {
972
    case 0:
973
        s->line_fn_tab[0] = s->line_fn_tab[1] =
974
                g_malloc0(sizeof(blizzard_fn_t) * 0x10);
975
        break;
976
    case 8:
977
        s->line_fn_tab[0] = blizzard_draw_fn_8;
978
        s->line_fn_tab[1] = blizzard_draw_fn_r_8;
979
        break;
980
    case 15:
981
        s->line_fn_tab[0] = blizzard_draw_fn_15;
982
        s->line_fn_tab[1] = blizzard_draw_fn_r_15;
983
        break;
984
    case 16:
985
        s->line_fn_tab[0] = blizzard_draw_fn_16;
986
        s->line_fn_tab[1] = blizzard_draw_fn_r_16;
987
        break;
988
    case 24:
989
        s->line_fn_tab[0] = blizzard_draw_fn_24;
990
        s->line_fn_tab[1] = blizzard_draw_fn_r_24;
991
        break;
992
    case 32:
993
        s->line_fn_tab[0] = blizzard_draw_fn_32;
994
        s->line_fn_tab[1] = blizzard_draw_fn_r_32;
995
        break;
996
    default:
997
        fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
998
        exit(1);
999
    }
1000

    
1001
    blizzard_reset(s);
1002

    
1003
    return s;
1004
}