root / hw / exynos4210_rtc.c @ 0d09e41a
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/*
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* Samsung exynos4210 Real Time Clock
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* Ogurtsov Oleg <o.ogurtsov@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/* Description:
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* Register RTCCON:
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* CLKSEL Bit[1] not used
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* CLKOUTEN Bit[9] not used
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*/
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#include "hw/sysbus.h" |
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#include "qemu/timer.h" |
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#include "qemu-common.h" |
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#include "hw/ptimer.h" |
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#include "hw/hw.h" |
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#include "qemu/timer.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/arm/exynos4210.h" |
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#define DEBUG_RTC 0 |
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|
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#if DEBUG_RTC
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#define DPRINTF(fmt, ...) \
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do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \ |
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## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) do {} while (0) |
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#endif
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#define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100 |
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|
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#define INTP 0x0030 |
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#define RTCCON 0x0040 |
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#define TICCNT 0x0044 |
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#define RTCALM 0x0050 |
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#define ALMSEC 0x0054 |
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#define ALMMIN 0x0058 |
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#define ALMHOUR 0x005C |
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#define ALMDAY 0x0060 |
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#define ALMMON 0x0064 |
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#define ALMYEAR 0x0068 |
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#define BCDSEC 0x0070 |
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#define BCDMIN 0x0074 |
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#define BCDHOUR 0x0078 |
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#define BCDDAY 0x007C |
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#define BCDDAYWEEK 0x0080 |
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#define BCDMON 0x0084 |
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#define BCDYEAR 0x0088 |
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#define CURTICNT 0x0090 |
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|
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#define TICK_TIMER_ENABLE 0x0100 |
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#define TICNT_THRESHHOLD 2 |
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|
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|
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#define RTC_ENABLE 0x0001 |
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|
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#define INTP_TICK_ENABLE 0x0001 |
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#define INTP_ALM_ENABLE 0x0002 |
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|
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#define ALARM_INT_ENABLE 0x0040 |
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|
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#define RTC_BASE_FREQ 32768 |
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|
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typedef struct Exynos4210RTCState { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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|
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/* registers */
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uint32_t reg_intp; |
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uint32_t reg_rtccon; |
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uint32_t reg_ticcnt; |
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uint32_t reg_rtcalm; |
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uint32_t reg_almsec; |
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uint32_t reg_almmin; |
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uint32_t reg_almhour; |
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uint32_t reg_almday; |
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uint32_t reg_almmon; |
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uint32_t reg_almyear; |
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uint32_t reg_curticcnt; |
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|
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ptimer_state *ptimer; /* tick timer */
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ptimer_state *ptimer_1Hz; /* clock timer */
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uint32_t freq; |
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|
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qemu_irq tick_irq; /* Time Tick Generator irq */
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qemu_irq alm_irq; /* alarm irq */
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|
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struct tm current_tm; /* current time */ |
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} Exynos4210RTCState; |
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|
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#define TICCKSEL(value) ((value & (0x0F << 4)) >> 4) |
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|
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/*** VMState ***/
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static const VMStateDescription vmstate_exynos4210_rtc_state = { |
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.name = "exynos4210.rtc",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(reg_intp, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_almsec, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_almmin, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_almhour, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_almday, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_almmon, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_almyear, Exynos4210RTCState), |
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VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState), |
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VMSTATE_PTIMER(ptimer, Exynos4210RTCState), |
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VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState), |
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VMSTATE_UINT32(freq, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState), |
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VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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#define BCD3DIGITS(x) \
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((uint32_t)to_bcd((uint8_t)(x % 100)) + \
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((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8)) |
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|
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static void check_alarm_raise(Exynos4210RTCState *s) |
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{
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unsigned int alarm_raise = 0; |
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struct tm stm = s->current_tm;
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if ((s->reg_rtcalm & 0x01) && |
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(to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
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alarm_raise = 1;
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} |
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if ((s->reg_rtcalm & 0x02) && |
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(to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
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alarm_raise = 1;
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} |
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if ((s->reg_rtcalm & 0x04) && |
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(to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
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alarm_raise = 1;
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} |
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if ((s->reg_rtcalm & 0x08) && |
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(to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
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alarm_raise = 1;
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} |
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if ((s->reg_rtcalm & 0x10) && |
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(to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
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alarm_raise = 1;
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} |
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if ((s->reg_rtcalm & 0x20) && |
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(BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
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alarm_raise = 1;
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} |
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if (alarm_raise) {
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DPRINTF("ALARM IRQ\n");
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/* set irq status */
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s->reg_intp |= INTP_ALM_ENABLE; |
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qemu_irq_raise(s->alm_irq); |
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} |
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} |
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|
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/*
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* RTC update frequency
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* Parameters:
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* reg_value - current RTCCON register or his new value
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*/
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static void exynos4210_rtc_update_freq(Exynos4210RTCState *s, |
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uint32_t reg_value) |
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{
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uint32_t freq; |
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freq = s->freq; |
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/* set frequncy for time generator */
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s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
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if (freq != s->freq) {
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ptimer_set_freq(s->ptimer, s->freq); |
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DPRINTF("freq=%dHz\n", s->freq);
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} |
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} |
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year) |
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{
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static const int days_tab[12] = { |
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
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}; |
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int d;
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if ((unsigned)month >= 12) { |
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return 31; |
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} |
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d = days_tab[month]; |
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if (month == 1) { |
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if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) { |
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d++; |
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} |
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} |
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return d;
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} |
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|
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/* update 'tm' to the next second */
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static void rtc_next_second(struct tm *tm) |
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{
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int days_in_month;
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|
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tm->tm_sec++; |
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if ((unsigned)tm->tm_sec >= 60) { |
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tm->tm_sec = 0;
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tm->tm_min++; |
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if ((unsigned)tm->tm_min >= 60) { |
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tm->tm_min = 0;
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tm->tm_hour++; |
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if ((unsigned)tm->tm_hour >= 24) { |
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tm->tm_hour = 0;
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/* next day */
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tm->tm_wday++; |
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if ((unsigned)tm->tm_wday >= 7) { |
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tm->tm_wday = 0;
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} |
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days_in_month = get_days_in_month(tm->tm_mon, |
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tm->tm_year + 1900);
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tm->tm_mday++; |
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if (tm->tm_mday < 1) { |
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tm->tm_mday = 1;
|
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} else if (tm->tm_mday > days_in_month) { |
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tm->tm_mday = 1;
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tm->tm_mon++; |
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if (tm->tm_mon >= 12) { |
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tm->tm_mon = 0;
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tm->tm_year++; |
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} |
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} |
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} |
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} |
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} |
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} |
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|
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/*
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* tick handler
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*/
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static void exynos4210_rtc_tick(void *opaque) |
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{
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Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
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|
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DPRINTF("TICK IRQ\n");
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/* set irq status */
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s->reg_intp |= INTP_TICK_ENABLE; |
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/* raise IRQ */
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qemu_irq_raise(s->tick_irq); |
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|
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/* restart timer */
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ptimer_set_count(s->ptimer, s->reg_ticcnt); |
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ptimer_run(s->ptimer, 1);
|
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} |
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|
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/*
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* 1Hz clock handler
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*/
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static void exynos4210_rtc_1Hz_tick(void *opaque) |
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{
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Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
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|
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rtc_next_second(&s->current_tm); |
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/* DPRINTF("1Hz tick\n"); */
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|
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/* raise IRQ */
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if (s->reg_rtcalm & ALARM_INT_ENABLE) {
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check_alarm_raise(s); |
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} |
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|
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ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ); |
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ptimer_run(s->ptimer_1Hz, 1);
|
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} |
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|
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/*
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* RTC Read
|
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*/
|
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static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset, |
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unsigned size)
|
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{
|
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uint32_t value = 0;
|
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Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
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|
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switch (offset) {
|
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case INTP:
|
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value = s->reg_intp; |
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break;
|
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case RTCCON:
|
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value = s->reg_rtccon; |
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break;
|
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case TICCNT:
|
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value = s->reg_ticcnt; |
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break;
|
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case RTCALM:
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value = s->reg_rtcalm; |
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break;
|
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case ALMSEC:
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value = s->reg_almsec; |
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break;
|
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case ALMMIN:
|
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value = s->reg_almmin; |
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break;
|
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case ALMHOUR:
|
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value = s->reg_almhour; |
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break;
|
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case ALMDAY:
|
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value = s->reg_almday; |
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break;
|
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case ALMMON:
|
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value = s->reg_almmon; |
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break;
|
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case ALMYEAR:
|
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value = s->reg_almyear; |
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break;
|
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|
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case BCDSEC:
|
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value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec); |
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break;
|
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case BCDMIN:
|
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value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min); |
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break;
|
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case BCDHOUR:
|
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value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour); |
| 348 |
break;
|
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case BCDDAYWEEK:
|
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value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday); |
| 351 |
break;
|
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case BCDDAY:
|
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value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday); |
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break;
|
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case BCDMON:
|
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value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
|
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break;
|
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case BCDYEAR:
|
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value = BCD3DIGITS(s->current_tm.tm_year); |
| 360 |
break;
|
| 361 |
|
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case CURTICNT:
|
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s->reg_curticcnt = ptimer_get_count(s->ptimer); |
| 364 |
value = s->reg_curticcnt; |
| 365 |
break;
|
| 366 |
|
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default:
|
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fprintf(stderr, |
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"[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n", |
| 370 |
offset); |
| 371 |
break;
|
| 372 |
} |
| 373 |
return value;
|
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} |
| 375 |
|
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/*
|
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* RTC Write
|
| 378 |
*/
|
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static void exynos4210_rtc_write(void *opaque, hwaddr offset, |
| 380 |
uint64_t value, unsigned size)
|
| 381 |
{
|
| 382 |
Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
| 383 |
|
| 384 |
switch (offset) {
|
| 385 |
case INTP:
|
| 386 |
if (value & INTP_ALM_ENABLE) {
|
| 387 |
qemu_irq_lower(s->alm_irq); |
| 388 |
s->reg_intp &= (~INTP_ALM_ENABLE); |
| 389 |
} |
| 390 |
if (value & INTP_TICK_ENABLE) {
|
| 391 |
qemu_irq_lower(s->tick_irq); |
| 392 |
s->reg_intp &= (~INTP_TICK_ENABLE); |
| 393 |
} |
| 394 |
break;
|
| 395 |
case RTCCON:
|
| 396 |
if (value & RTC_ENABLE) {
|
| 397 |
exynos4210_rtc_update_freq(s, value); |
| 398 |
} |
| 399 |
if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
|
| 400 |
/* clock timer */
|
| 401 |
ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ); |
| 402 |
ptimer_run(s->ptimer_1Hz, 1);
|
| 403 |
DPRINTF("run clock timer\n");
|
| 404 |
} |
| 405 |
if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
|
| 406 |
/* tick timer */
|
| 407 |
ptimer_stop(s->ptimer); |
| 408 |
/* clock timer */
|
| 409 |
ptimer_stop(s->ptimer_1Hz); |
| 410 |
DPRINTF("stop all timers\n");
|
| 411 |
} |
| 412 |
if (value & RTC_ENABLE) {
|
| 413 |
if ((value & TICK_TIMER_ENABLE) >
|
| 414 |
(s->reg_rtccon & TICK_TIMER_ENABLE) && |
| 415 |
(s->reg_ticcnt)) {
|
| 416 |
ptimer_set_count(s->ptimer, s->reg_ticcnt); |
| 417 |
ptimer_run(s->ptimer, 1);
|
| 418 |
DPRINTF("run tick timer\n");
|
| 419 |
} |
| 420 |
if ((value & TICK_TIMER_ENABLE) <
|
| 421 |
(s->reg_rtccon & TICK_TIMER_ENABLE)) {
|
| 422 |
ptimer_stop(s->ptimer); |
| 423 |
} |
| 424 |
} |
| 425 |
s->reg_rtccon = value; |
| 426 |
break;
|
| 427 |
case TICCNT:
|
| 428 |
if (value > TICNT_THRESHHOLD) {
|
| 429 |
s->reg_ticcnt = value; |
| 430 |
} else {
|
| 431 |
fprintf(stderr, |
| 432 |
"[exynos4210.rtc: bad TICNT value %u ]\n",
|
| 433 |
(uint32_t)value); |
| 434 |
} |
| 435 |
break;
|
| 436 |
|
| 437 |
case RTCALM:
|
| 438 |
s->reg_rtcalm = value; |
| 439 |
break;
|
| 440 |
case ALMSEC:
|
| 441 |
s->reg_almsec = (value & 0x7f);
|
| 442 |
break;
|
| 443 |
case ALMMIN:
|
| 444 |
s->reg_almmin = (value & 0x7f);
|
| 445 |
break;
|
| 446 |
case ALMHOUR:
|
| 447 |
s->reg_almhour = (value & 0x3f);
|
| 448 |
break;
|
| 449 |
case ALMDAY:
|
| 450 |
s->reg_almday = (value & 0x3f);
|
| 451 |
break;
|
| 452 |
case ALMMON:
|
| 453 |
s->reg_almmon = (value & 0x1f);
|
| 454 |
break;
|
| 455 |
case ALMYEAR:
|
| 456 |
s->reg_almyear = (value & 0x0fff);
|
| 457 |
break;
|
| 458 |
|
| 459 |
case BCDSEC:
|
| 460 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 461 |
s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
|
| 462 |
} |
| 463 |
break;
|
| 464 |
case BCDMIN:
|
| 465 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 466 |
s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
|
| 467 |
} |
| 468 |
break;
|
| 469 |
case BCDHOUR:
|
| 470 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 471 |
s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
|
| 472 |
} |
| 473 |
break;
|
| 474 |
case BCDDAYWEEK:
|
| 475 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 476 |
s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
|
| 477 |
} |
| 478 |
break;
|
| 479 |
case BCDDAY:
|
| 480 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 481 |
s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
|
| 482 |
} |
| 483 |
break;
|
| 484 |
case BCDMON:
|
| 485 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 486 |
s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1; |
| 487 |
} |
| 488 |
break;
|
| 489 |
case BCDYEAR:
|
| 490 |
if (s->reg_rtccon & RTC_ENABLE) {
|
| 491 |
/* 3 digits */
|
| 492 |
s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
|
| 493 |
(int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100; |
| 494 |
} |
| 495 |
break;
|
| 496 |
|
| 497 |
default:
|
| 498 |
fprintf(stderr, |
| 499 |
"[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n", |
| 500 |
offset); |
| 501 |
break;
|
| 502 |
|
| 503 |
} |
| 504 |
} |
| 505 |
|
| 506 |
/*
|
| 507 |
* Set default values to timer fields and registers
|
| 508 |
*/
|
| 509 |
static void exynos4210_rtc_reset(DeviceState *d) |
| 510 |
{
|
| 511 |
Exynos4210RTCState *s = (Exynos4210RTCState *)d; |
| 512 |
|
| 513 |
qemu_get_timedate(&s->current_tm, 0);
|
| 514 |
|
| 515 |
DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
|
| 516 |
s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday, |
| 517 |
s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec); |
| 518 |
|
| 519 |
s->reg_intp = 0;
|
| 520 |
s->reg_rtccon = 0;
|
| 521 |
s->reg_ticcnt = 0;
|
| 522 |
s->reg_rtcalm = 0;
|
| 523 |
s->reg_almsec = 0;
|
| 524 |
s->reg_almmin = 0;
|
| 525 |
s->reg_almhour = 0;
|
| 526 |
s->reg_almday = 0;
|
| 527 |
s->reg_almmon = 0;
|
| 528 |
s->reg_almyear = 0;
|
| 529 |
|
| 530 |
s->reg_curticcnt = 0;
|
| 531 |
|
| 532 |
exynos4210_rtc_update_freq(s, s->reg_rtccon); |
| 533 |
ptimer_stop(s->ptimer); |
| 534 |
ptimer_stop(s->ptimer_1Hz); |
| 535 |
} |
| 536 |
|
| 537 |
static const MemoryRegionOps exynos4210_rtc_ops = { |
| 538 |
.read = exynos4210_rtc_read, |
| 539 |
.write = exynos4210_rtc_write, |
| 540 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 541 |
}; |
| 542 |
|
| 543 |
/*
|
| 544 |
* RTC timer initialization
|
| 545 |
*/
|
| 546 |
static int exynos4210_rtc_init(SysBusDevice *dev) |
| 547 |
{
|
| 548 |
Exynos4210RTCState *s = FROM_SYSBUS(Exynos4210RTCState, dev); |
| 549 |
QEMUBH *bh; |
| 550 |
|
| 551 |
bh = qemu_bh_new(exynos4210_rtc_tick, s); |
| 552 |
s->ptimer = ptimer_init(bh); |
| 553 |
ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); |
| 554 |
exynos4210_rtc_update_freq(s, 0);
|
| 555 |
|
| 556 |
bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); |
| 557 |
s->ptimer_1Hz = ptimer_init(bh); |
| 558 |
ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); |
| 559 |
|
| 560 |
sysbus_init_irq(dev, &s->alm_irq); |
| 561 |
sysbus_init_irq(dev, &s->tick_irq); |
| 562 |
|
| 563 |
memory_region_init_io(&s->iomem, &exynos4210_rtc_ops, s, "exynos4210-rtc",
|
| 564 |
EXYNOS4210_RTC_REG_MEM_SIZE); |
| 565 |
sysbus_init_mmio(dev, &s->iomem); |
| 566 |
|
| 567 |
return 0; |
| 568 |
} |
| 569 |
|
| 570 |
static void exynos4210_rtc_class_init(ObjectClass *klass, void *data) |
| 571 |
{
|
| 572 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 573 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 574 |
|
| 575 |
k->init = exynos4210_rtc_init; |
| 576 |
dc->reset = exynos4210_rtc_reset; |
| 577 |
dc->vmsd = &vmstate_exynos4210_rtc_state; |
| 578 |
} |
| 579 |
|
| 580 |
static const TypeInfo exynos4210_rtc_info = { |
| 581 |
.name = "exynos4210.rtc",
|
| 582 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 583 |
.instance_size = sizeof(Exynos4210RTCState),
|
| 584 |
.class_init = exynos4210_rtc_class_init, |
| 585 |
}; |
| 586 |
|
| 587 |
static void exynos4210_rtc_register_types(void) |
| 588 |
{
|
| 589 |
type_register_static(&exynos4210_rtc_info); |
| 590 |
} |
| 591 |
|
| 592 |
type_init(exynos4210_rtc_register_types) |