root / hw / exynos4210_uart.c @ 0d09e41a
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/*
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* Exynos4210 UART Emulation
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*
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* Copyright (C) 2011 Samsung Electronics Co Ltd.
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* Maksim Kozlov, <m.kozlov@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "hw/sysbus.h" |
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#include "sysemu/sysemu.h" |
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#include "char/char.h" |
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#include "hw/arm/exynos4210.h" |
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#undef DEBUG_UART
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#undef DEBUG_UART_EXTEND
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#undef DEBUG_IRQ
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#undef DEBUG_Rx_DATA
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#undef DEBUG_Tx_DATA
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#define DEBUG_UART 0 |
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#define DEBUG_UART_EXTEND 0 |
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#define DEBUG_IRQ 0 |
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#define DEBUG_Rx_DATA 0 |
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#define DEBUG_Tx_DATA 0 |
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|
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#if DEBUG_UART
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#define PRINT_DEBUG(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
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} while (0) |
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|
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#if DEBUG_UART_EXTEND
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#define PRINT_DEBUG_EXTEND(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
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} while (0) |
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#else
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#define PRINT_DEBUG_EXTEND(fmt, args...) \
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do {} while (0) |
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#endif /* EXTEND */ |
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|
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#else
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#define PRINT_DEBUG(fmt, args...) \
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do {} while (0) |
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#define PRINT_DEBUG_EXTEND(fmt, args...) \
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do {} while (0) |
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#endif
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#define PRINT_ERROR(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
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} while (0) |
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|
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/*
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* Offsets for UART registers relative to SFR base address
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* for UARTn
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*
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*/
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#define ULCON 0x0000 /* Line Control */ |
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#define UCON 0x0004 /* Control */ |
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#define UFCON 0x0008 /* FIFO Control */ |
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#define UMCON 0x000C /* Modem Control */ |
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#define UTRSTAT 0x0010 /* Tx/Rx Status */ |
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#define UERSTAT 0x0014 /* UART Error Status */ |
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#define UFSTAT 0x0018 /* FIFO Status */ |
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#define UMSTAT 0x001C /* Modem Status */ |
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#define UTXH 0x0020 /* Transmit Buffer */ |
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#define URXH 0x0024 /* Receive Buffer */ |
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#define UBRDIV 0x0028 /* Baud Rate Divisor */ |
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#define UFRACVAL 0x002C /* Divisor Fractional Value */ |
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#define UINTP 0x0030 /* Interrupt Pending */ |
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#define UINTSP 0x0034 /* Interrupt Source Pending */ |
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#define UINTM 0x0038 /* Interrupt Mask */ |
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|
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/*
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* for indexing register in the uint32_t array
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*
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* 'reg' - register offset (see offsets definitions above)
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*
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*/
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#define I_(reg) (reg / sizeof(uint32_t)) |
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typedef struct Exynos4210UartReg { |
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const char *name; /* the only reason is the debug output */ |
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hwaddr offset; |
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uint32_t reset_value; |
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} Exynos4210UartReg; |
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static Exynos4210UartReg exynos4210_uart_regs[] = {
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{"ULCON", ULCON, 0x00000000},
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{"UCON", UCON, 0x00003000},
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{"UFCON", UFCON, 0x00000000},
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{"UMCON", UMCON, 0x00000000},
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{"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
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{"UERSTAT", UERSTAT, 0x00000000}, /* RO */
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{"UFSTAT", UFSTAT, 0x00000000}, /* RO */
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{"UMSTAT", UMSTAT, 0x00000000}, /* RO */
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{"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
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{"URXH", URXH, 0x00000000}, /* RO */
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{"UBRDIV", UBRDIV, 0x00000000},
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{"UFRACVAL", UFRACVAL, 0x00000000},
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{"UINTP", UINTP, 0x00000000},
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{"UINTSP", UINTSP, 0x00000000},
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{"UINTM", UINTM, 0x00000000},
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}; |
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#define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C |
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/* UART FIFO Control */
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#define UFCON_FIFO_ENABLE 0x1 |
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#define UFCON_Rx_FIFO_RESET 0x2 |
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#define UFCON_Tx_FIFO_RESET 0x4 |
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#define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 |
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#define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) |
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#define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 |
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#define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) |
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/* Uart FIFO Status */
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#define UFSTAT_Rx_FIFO_COUNT 0xff |
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#define UFSTAT_Rx_FIFO_FULL 0x100 |
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#define UFSTAT_Rx_FIFO_ERROR 0x200 |
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#define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 |
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#define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) |
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#define UFSTAT_Tx_FIFO_FULL_SHIFT 24 |
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#define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) |
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|
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/* UART Interrupt Source Pending */
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#define UINTSP_RXD 0x1 /* Receive interrupt */ |
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#define UINTSP_ERROR 0x2 /* Error interrupt */ |
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#define UINTSP_TXD 0x4 /* Transmit interrupt */ |
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#define UINTSP_MODEM 0x8 /* Modem interrupt */ |
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|
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/* UART Line Control */
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#define ULCON_IR_MODE_SHIFT 6 |
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#define ULCON_PARITY_SHIFT 3 |
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#define ULCON_STOP_BIT_SHIFT 1 |
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|
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/* UART Tx/Rx Status */
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#define UTRSTAT_TRANSMITTER_EMPTY 0x4 |
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#define UTRSTAT_Tx_BUFFER_EMPTY 0x2 |
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#define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 |
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|
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/* UART Error Status */
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#define UERSTAT_OVERRUN 0x1 |
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#define UERSTAT_PARITY 0x2 |
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#define UERSTAT_FRAME 0x4 |
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#define UERSTAT_BREAK 0x8 |
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|
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typedef struct { |
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uint8_t *data; |
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uint32_t sp, rp; /* store and retrieve pointers */
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uint32_t size; |
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} Exynos4210UartFIFO; |
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typedef struct { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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|
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uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
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Exynos4210UartFIFO rx; |
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Exynos4210UartFIFO tx; |
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CharDriverState *chr; |
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qemu_irq irq; |
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uint32_t channel; |
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|
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} Exynos4210UartState; |
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#if DEBUG_UART
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/* Used only for debugging inside PRINT_DEBUG_... macros */
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static const char *exynos4210_uart_regname(hwaddr offset) |
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{
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int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg); |
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int i;
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for (i = 0; i < regs_number; i++) { |
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if (offset == exynos4210_uart_regs[i].offset) {
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return exynos4210_uart_regs[i].name;
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} |
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} |
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return NULL; |
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} |
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#endif
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static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) |
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{
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q->data[q->sp] = ch; |
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q->sp = (q->sp + 1) % q->size;
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} |
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static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
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{
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uint8_t ret = q->data[q->rp]; |
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q->rp = (q->rp + 1) % q->size;
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return ret;
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} |
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static int fifo_elements_number(Exynos4210UartFIFO *q) |
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{
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if (q->sp < q->rp) {
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return q->size - q->rp + q->sp;
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} |
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return q->sp - q->rp;
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} |
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static int fifo_empty_elements_number(Exynos4210UartFIFO *q) |
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{
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return q->size - fifo_elements_number(q);
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} |
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static void fifo_reset(Exynos4210UartFIFO *q) |
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{
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if (q->data != NULL) { |
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g_free(q->data); |
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q->data = NULL;
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} |
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q->data = (uint8_t *)g_malloc0(q->size); |
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q->sp = 0;
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q->rp = 0;
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} |
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static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
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{
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uint32_t level = 0;
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uint32_t reg; |
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reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> |
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UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; |
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switch (s->channel) {
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case 0: |
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level = reg * 32;
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break;
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case 1: |
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case 4: |
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level = reg * 8;
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break;
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case 2: |
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case 3: |
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level = reg * 2;
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break;
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default:
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level = 0;
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PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
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} |
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return level;
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} |
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|
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static void exynos4210_uart_update_irq(Exynos4210UartState *s) |
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{
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/*
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* The Tx interrupt is always requested if the number of data in the
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* transmit FIFO is smaller than the trigger level.
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*/
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if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
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uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> |
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UFSTAT_Tx_FIFO_COUNT_SHIFT; |
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|
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if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
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s->reg[I_(UINTSP)] |= UINTSP_TXD; |
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} |
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} |
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s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; |
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|
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if (s->reg[I_(UINTP)]) {
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qemu_irq_raise(s->irq); |
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#if DEBUG_IRQ
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fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
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s->channel, s->reg[I_(UINTP)]); |
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#endif
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} else {
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qemu_irq_lower(s->irq); |
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} |
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} |
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|
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static void exynos4210_uart_update_parameters(Exynos4210UartState *s) |
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{
|
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int speed, parity, data_bits, stop_bits, frame_size;
|
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QEMUSerialSetParams ssp; |
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uint64_t uclk_rate; |
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|
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if (s->reg[I_(UBRDIV)] == 0) { |
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return;
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} |
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|
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frame_size = 1; /* start bit */ |
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if (s->reg[I_(ULCON)] & 0x20) { |
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frame_size++; /* parity bit */
|
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if (s->reg[I_(ULCON)] & 0x28) { |
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parity = 'E';
|
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} else {
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parity = 'O';
|
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} |
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} else {
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parity = 'N';
|
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} |
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|
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if (s->reg[I_(ULCON)] & 0x4) { |
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stop_bits = 2;
|
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} else {
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stop_bits = 1;
|
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} |
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|
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data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; |
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|
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frame_size += data_bits + stop_bits; |
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|
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uclk_rate = 24000000;
|
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|
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speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + |
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(s->reg[I_(UFRACVAL)] & 0x7) + 16); |
| 339 |
|
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ssp.speed = speed; |
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ssp.parity = parity; |
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ssp.data_bits = data_bits; |
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ssp.stop_bits = stop_bits; |
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|
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 346 |
|
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PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
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s->channel, speed, parity, data_bits, stop_bits); |
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} |
| 350 |
|
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static void exynos4210_uart_write(void *opaque, hwaddr offset, |
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uint64_t val, unsigned size)
|
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{
|
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Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
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uint8_t ch; |
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|
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PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
|
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offset, exynos4210_uart_regname(offset), (long long unsigned int)val); |
| 359 |
|
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switch (offset) {
|
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case ULCON:
|
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case UBRDIV:
|
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case UFRACVAL:
|
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s->reg[I_(offset)] = val; |
| 365 |
exynos4210_uart_update_parameters(s); |
| 366 |
break;
|
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case UFCON:
|
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s->reg[I_(UFCON)] = val; |
| 369 |
if (val & UFCON_Rx_FIFO_RESET) {
|
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fifo_reset(&s->rx); |
| 371 |
s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; |
| 372 |
PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
|
| 373 |
} |
| 374 |
if (val & UFCON_Tx_FIFO_RESET) {
|
| 375 |
fifo_reset(&s->tx); |
| 376 |
s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; |
| 377 |
PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
|
| 378 |
} |
| 379 |
break;
|
| 380 |
|
| 381 |
case UTXH:
|
| 382 |
if (s->chr) {
|
| 383 |
s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | |
| 384 |
UTRSTAT_Tx_BUFFER_EMPTY); |
| 385 |
ch = (uint8_t)val; |
| 386 |
qemu_chr_fe_write(s->chr, &ch, 1);
|
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#if DEBUG_Tx_DATA
|
| 388 |
fprintf(stderr, "%c", ch);
|
| 389 |
#endif
|
| 390 |
s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | |
| 391 |
UTRSTAT_Tx_BUFFER_EMPTY; |
| 392 |
s->reg[I_(UINTSP)] |= UINTSP_TXD; |
| 393 |
exynos4210_uart_update_irq(s); |
| 394 |
} |
| 395 |
break;
|
| 396 |
|
| 397 |
case UINTP:
|
| 398 |
s->reg[I_(UINTP)] &= ~val; |
| 399 |
s->reg[I_(UINTSP)] &= ~val; |
| 400 |
PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
|
| 401 |
s->channel, offset, s->reg[I_(UINTP)]); |
| 402 |
exynos4210_uart_update_irq(s); |
| 403 |
break;
|
| 404 |
case UTRSTAT:
|
| 405 |
case UERSTAT:
|
| 406 |
case UFSTAT:
|
| 407 |
case UMSTAT:
|
| 408 |
case URXH:
|
| 409 |
PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
|
| 410 |
s->channel, exynos4210_uart_regname(offset), offset); |
| 411 |
break;
|
| 412 |
case UINTSP:
|
| 413 |
s->reg[I_(UINTSP)] &= ~val; |
| 414 |
break;
|
| 415 |
case UINTM:
|
| 416 |
s->reg[I_(UINTM)] = val; |
| 417 |
exynos4210_uart_update_irq(s); |
| 418 |
break;
|
| 419 |
case UCON:
|
| 420 |
case UMCON:
|
| 421 |
default:
|
| 422 |
s->reg[I_(offset)] = val; |
| 423 |
break;
|
| 424 |
} |
| 425 |
} |
| 426 |
static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, |
| 427 |
unsigned size)
|
| 428 |
{
|
| 429 |
Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 430 |
uint32_t res; |
| 431 |
|
| 432 |
switch (offset) {
|
| 433 |
case UERSTAT: /* Read Only */ |
| 434 |
res = s->reg[I_(UERSTAT)]; |
| 435 |
s->reg[I_(UERSTAT)] = 0;
|
| 436 |
return res;
|
| 437 |
case UFSTAT: /* Read Only */ |
| 438 |
s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
|
| 439 |
if (fifo_empty_elements_number(&s->rx) == 0) { |
| 440 |
s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; |
| 441 |
s->reg[I_(UFSTAT)] &= ~0xff;
|
| 442 |
} |
| 443 |
return s->reg[I_(UFSTAT)];
|
| 444 |
case URXH:
|
| 445 |
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
| 446 |
if (fifo_elements_number(&s->rx)) {
|
| 447 |
res = fifo_retrieve(&s->rx); |
| 448 |
#if DEBUG_Rx_DATA
|
| 449 |
fprintf(stderr, "%c", res);
|
| 450 |
#endif
|
| 451 |
if (!fifo_elements_number(&s->rx)) {
|
| 452 |
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; |
| 453 |
} else {
|
| 454 |
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 455 |
} |
| 456 |
} else {
|
| 457 |
s->reg[I_(UINTSP)] |= UINTSP_ERROR; |
| 458 |
exynos4210_uart_update_irq(s); |
| 459 |
res = 0;
|
| 460 |
} |
| 461 |
} else {
|
| 462 |
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; |
| 463 |
res = s->reg[I_(URXH)]; |
| 464 |
} |
| 465 |
return res;
|
| 466 |
case UTXH:
|
| 467 |
PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
|
| 468 |
s->channel, exynos4210_uart_regname(offset), offset); |
| 469 |
break;
|
| 470 |
default:
|
| 471 |
return s->reg[I_(offset)];
|
| 472 |
} |
| 473 |
|
| 474 |
return 0; |
| 475 |
} |
| 476 |
|
| 477 |
static const MemoryRegionOps exynos4210_uart_ops = { |
| 478 |
.read = exynos4210_uart_read, |
| 479 |
.write = exynos4210_uart_write, |
| 480 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 481 |
.valid = {
|
| 482 |
.max_access_size = 4,
|
| 483 |
.unaligned = false
|
| 484 |
}, |
| 485 |
}; |
| 486 |
|
| 487 |
static int exynos4210_uart_can_receive(void *opaque) |
| 488 |
{
|
| 489 |
Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 490 |
|
| 491 |
return fifo_empty_elements_number(&s->rx);
|
| 492 |
} |
| 493 |
|
| 494 |
|
| 495 |
static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) |
| 496 |
{
|
| 497 |
Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 498 |
int i;
|
| 499 |
|
| 500 |
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
| 501 |
if (fifo_empty_elements_number(&s->rx) < size) {
|
| 502 |
for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { |
| 503 |
fifo_store(&s->rx, buf[i]); |
| 504 |
} |
| 505 |
s->reg[I_(UINTSP)] |= UINTSP_ERROR; |
| 506 |
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 507 |
} else {
|
| 508 |
for (i = 0; i < size; i++) { |
| 509 |
fifo_store(&s->rx, buf[i]); |
| 510 |
} |
| 511 |
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 512 |
} |
| 513 |
/* XXX: Around here we maybe should check Rx trigger level */
|
| 514 |
s->reg[I_(UINTSP)] |= UINTSP_RXD; |
| 515 |
} else {
|
| 516 |
s->reg[I_(URXH)] = buf[0];
|
| 517 |
s->reg[I_(UINTSP)] |= UINTSP_RXD; |
| 518 |
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 519 |
} |
| 520 |
|
| 521 |
exynos4210_uart_update_irq(s); |
| 522 |
} |
| 523 |
|
| 524 |
|
| 525 |
static void exynos4210_uart_event(void *opaque, int event) |
| 526 |
{
|
| 527 |
Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 528 |
|
| 529 |
if (event == CHR_EVENT_BREAK) {
|
| 530 |
/* When the RxDn is held in logic 0, then a null byte is pushed into the
|
| 531 |
* fifo */
|
| 532 |
fifo_store(&s->rx, '\0');
|
| 533 |
s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; |
| 534 |
exynos4210_uart_update_irq(s); |
| 535 |
} |
| 536 |
} |
| 537 |
|
| 538 |
|
| 539 |
static void exynos4210_uart_reset(DeviceState *dev) |
| 540 |
{
|
| 541 |
Exynos4210UartState *s = |
| 542 |
container_of(dev, Exynos4210UartState, busdev.qdev); |
| 543 |
int regs_number = sizeof(exynos4210_uart_regs)/sizeof(Exynos4210UartReg); |
| 544 |
int i;
|
| 545 |
|
| 546 |
for (i = 0; i < regs_number; i++) { |
| 547 |
s->reg[I_(exynos4210_uart_regs[i].offset)] = |
| 548 |
exynos4210_uart_regs[i].reset_value; |
| 549 |
} |
| 550 |
|
| 551 |
fifo_reset(&s->rx); |
| 552 |
fifo_reset(&s->tx); |
| 553 |
|
| 554 |
PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
|
| 555 |
} |
| 556 |
|
| 557 |
static const VMStateDescription vmstate_exynos4210_uart_fifo = { |
| 558 |
.name = "exynos4210.uart.fifo",
|
| 559 |
.version_id = 1,
|
| 560 |
.minimum_version_id = 1,
|
| 561 |
.minimum_version_id_old = 1,
|
| 562 |
.fields = (VMStateField[]) {
|
| 563 |
VMSTATE_UINT32(sp, Exynos4210UartFIFO), |
| 564 |
VMSTATE_UINT32(rp, Exynos4210UartFIFO), |
| 565 |
VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size), |
| 566 |
VMSTATE_END_OF_LIST() |
| 567 |
} |
| 568 |
}; |
| 569 |
|
| 570 |
static const VMStateDescription vmstate_exynos4210_uart = { |
| 571 |
.name = "exynos4210.uart",
|
| 572 |
.version_id = 1,
|
| 573 |
.minimum_version_id = 1,
|
| 574 |
.minimum_version_id_old = 1,
|
| 575 |
.fields = (VMStateField[]) {
|
| 576 |
VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
|
| 577 |
vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), |
| 578 |
VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, |
| 579 |
EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
|
| 580 |
VMSTATE_END_OF_LIST() |
| 581 |
} |
| 582 |
}; |
| 583 |
|
| 584 |
DeviceState *exynos4210_uart_create(hwaddr addr, |
| 585 |
int fifo_size,
|
| 586 |
int channel,
|
| 587 |
CharDriverState *chr, |
| 588 |
qemu_irq irq) |
| 589 |
{
|
| 590 |
DeviceState *dev; |
| 591 |
SysBusDevice *bus; |
| 592 |
|
| 593 |
const char chr_name[] = "serial"; |
| 594 |
char label[ARRAY_SIZE(chr_name) + 1]; |
| 595 |
|
| 596 |
dev = qdev_create(NULL, "exynos4210.uart"); |
| 597 |
|
| 598 |
if (!chr) {
|
| 599 |
if (channel >= MAX_SERIAL_PORTS) {
|
| 600 |
hw_error("Only %d serial ports are supported by QEMU.\n",
|
| 601 |
MAX_SERIAL_PORTS); |
| 602 |
} |
| 603 |
chr = serial_hds[channel]; |
| 604 |
if (!chr) {
|
| 605 |
snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
|
| 606 |
chr = qemu_chr_new(label, "null", NULL); |
| 607 |
if (!(chr)) {
|
| 608 |
hw_error("Can't assign serial port to UART%d.\n", channel);
|
| 609 |
} |
| 610 |
} |
| 611 |
} |
| 612 |
|
| 613 |
qdev_prop_set_chr(dev, "chardev", chr);
|
| 614 |
qdev_prop_set_uint32(dev, "channel", channel);
|
| 615 |
qdev_prop_set_uint32(dev, "rx-size", fifo_size);
|
| 616 |
qdev_prop_set_uint32(dev, "tx-size", fifo_size);
|
| 617 |
|
| 618 |
bus = SYS_BUS_DEVICE(dev); |
| 619 |
qdev_init_nofail(dev); |
| 620 |
if (addr != (hwaddr)-1) { |
| 621 |
sysbus_mmio_map(bus, 0, addr);
|
| 622 |
} |
| 623 |
sysbus_connect_irq(bus, 0, irq);
|
| 624 |
|
| 625 |
return dev;
|
| 626 |
} |
| 627 |
|
| 628 |
static int exynos4210_uart_init(SysBusDevice *dev) |
| 629 |
{
|
| 630 |
Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev); |
| 631 |
|
| 632 |
/* memory mapping */
|
| 633 |
memory_region_init_io(&s->iomem, &exynos4210_uart_ops, s, "exynos4210.uart",
|
| 634 |
EXYNOS4210_UART_REGS_MEM_SIZE); |
| 635 |
sysbus_init_mmio(dev, &s->iomem); |
| 636 |
|
| 637 |
sysbus_init_irq(dev, &s->irq); |
| 638 |
|
| 639 |
qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive, |
| 640 |
exynos4210_uart_receive, exynos4210_uart_event, s); |
| 641 |
|
| 642 |
return 0; |
| 643 |
} |
| 644 |
|
| 645 |
static Property exynos4210_uart_properties[] = {
|
| 646 |
DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
|
| 647 |
DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), |
| 648 |
DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), |
| 649 |
DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), |
| 650 |
DEFINE_PROP_END_OF_LIST(), |
| 651 |
}; |
| 652 |
|
| 653 |
static void exynos4210_uart_class_init(ObjectClass *klass, void *data) |
| 654 |
{
|
| 655 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 656 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 657 |
|
| 658 |
k->init = exynos4210_uart_init; |
| 659 |
dc->reset = exynos4210_uart_reset; |
| 660 |
dc->props = exynos4210_uart_properties; |
| 661 |
dc->vmsd = &vmstate_exynos4210_uart; |
| 662 |
} |
| 663 |
|
| 664 |
static const TypeInfo exynos4210_uart_info = { |
| 665 |
.name = "exynos4210.uart",
|
| 666 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 667 |
.instance_size = sizeof(Exynos4210UartState),
|
| 668 |
.class_init = exynos4210_uart_class_init, |
| 669 |
}; |
| 670 |
|
| 671 |
static void exynos4210_uart_register(void) |
| 672 |
{
|
| 673 |
type_register_static(&exynos4210_uart_info); |
| 674 |
} |
| 675 |
|
| 676 |
type_init(exynos4210_uart_register) |