root / hw / pxa2xx_timer.c @ 0d09e41a
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/*
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* Intel XScale PXA255/270 OS Timers.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2006 Thorsten Zitterell
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/hw.h" |
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#include "qemu/timer.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/arm/pxa.h" |
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#include "hw/sysbus.h" |
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|
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#define OSMR0 0x00 |
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#define OSMR1 0x04 |
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#define OSMR2 0x08 |
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#define OSMR3 0x0c |
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#define OSMR4 0x80 |
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#define OSMR5 0x84 |
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#define OSMR6 0x88 |
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#define OSMR7 0x8c |
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#define OSMR8 0x90 |
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#define OSMR9 0x94 |
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#define OSMR10 0x98 |
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#define OSMR11 0x9c |
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#define OSCR 0x10 /* OS Timer Count */ |
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#define OSCR4 0x40 |
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#define OSCR5 0x44 |
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#define OSCR6 0x48 |
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#define OSCR7 0x4c |
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#define OSCR8 0x50 |
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#define OSCR9 0x54 |
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#define OSCR10 0x58 |
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#define OSCR11 0x5c |
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#define OSSR 0x14 /* Timer status register */ |
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#define OWER 0x18 |
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#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
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#define OMCR4 0xc0 /* OS Match Control registers */ |
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#define OMCR5 0xc4 |
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#define OMCR6 0xc8 |
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#define OMCR7 0xcc |
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#define OMCR8 0xd0 |
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#define OMCR9 0xd4 |
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#define OMCR10 0xd8 |
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#define OMCR11 0xdc |
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#define OSNR 0x20 |
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|
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#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
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#define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
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|
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static int pxa2xx_timer4_freq[8] = { |
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[0] = 0, |
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[1] = 32768, |
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[2] = 1000, |
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[3] = 1, |
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[4] = 1000000, |
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/* [5] is the "Externally supplied clock". Assign if necessary. */
|
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[5 ... 7] = 0, |
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}; |
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|
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typedef struct PXA2xxTimerInfo PXA2xxTimerInfo; |
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typedef struct { |
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uint32_t value; |
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qemu_irq irq; |
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QEMUTimer *qtimer; |
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int num;
|
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PXA2xxTimerInfo *info; |
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} PXA2xxTimer0; |
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|
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typedef struct { |
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PXA2xxTimer0 tm; |
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int32_t oldclock; |
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int32_t clock; |
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uint64_t lastload; |
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uint32_t freq; |
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uint32_t control; |
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} PXA2xxTimer4; |
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|
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struct PXA2xxTimerInfo {
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t flags; |
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|
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int32_t clock; |
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int32_t oldclock; |
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uint64_t lastload; |
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uint32_t freq; |
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PXA2xxTimer0 timer[4];
|
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uint32_t events; |
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uint32_t irq_enabled; |
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uint32_t reset3; |
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uint32_t snapshot; |
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|
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qemu_irq irq4; |
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PXA2xxTimer4 tm4[8];
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}; |
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|
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#define PXA2XX_TIMER_HAVE_TM4 0 |
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|
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static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) |
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{
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return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4); |
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} |
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|
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static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
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{
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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int i;
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uint32_t now_vm; |
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uint64_t new_qemu; |
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|
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now_vm = s->clock + |
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muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec()); |
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for (i = 0; i < 4; i ++) { |
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new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
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get_ticks_per_sec(), s->freq); |
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qemu_mod_timer(s->timer[i].qtimer, new_qemu); |
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} |
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} |
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|
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static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
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{
|
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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uint32_t now_vm; |
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uint64_t new_qemu; |
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static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
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int counter;
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|
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if (s->tm4[n].control & (1 << 7)) |
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counter = n; |
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else
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counter = counters[n]; |
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|
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if (!s->tm4[counter].freq) {
|
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qemu_del_timer(s->tm4[n].tm.qtimer); |
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return;
|
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} |
| 142 |
|
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now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
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s->tm4[counter].lastload, |
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s->tm4[counter].freq, get_ticks_per_sec()); |
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|
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new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
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get_ticks_per_sec(), s->tm4[counter].freq); |
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qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); |
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} |
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|
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static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, |
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unsigned size)
|
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{
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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int tm = 0; |
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|
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switch (offset) {
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case OSMR3: tm ++;
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/* fall through */
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case OSMR2: tm ++;
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/* fall through */
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case OSMR1: tm ++;
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/* fall through */
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case OSMR0:
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return s->timer[tm].value;
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case OSMR11: tm ++;
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/* fall through */
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case OSMR10: tm ++;
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/* fall through */
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case OSMR9: tm ++;
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/* fall through */
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case OSMR8: tm ++;
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/* fall through */
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case OSMR7: tm ++;
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/* fall through */
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case OSMR6: tm ++;
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/* fall through */
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case OSMR5: tm ++;
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/* fall through */
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case OSMR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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return s->tm4[tm].tm.value;
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case OSCR:
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return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
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s->lastload, s->freq, get_ticks_per_sec()); |
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case OSCR11: tm ++;
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/* fall through */
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case OSCR10: tm ++;
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/* fall through */
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case OSCR9: tm ++;
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/* fall through */
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case OSCR8: tm ++;
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/* fall through */
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case OSCR7: tm ++;
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/* fall through */
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case OSCR6: tm ++;
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/* fall through */
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case OSCR5: tm ++;
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/* fall through */
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case OSCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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|
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if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
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if (s->tm4[tm - 1].freq) |
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s->snapshot = s->tm4[tm - 1].clock + muldiv64(
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qemu_get_clock_ns(vm_clock) - |
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s->tm4[tm - 1].lastload,
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s->tm4[tm - 1].freq, get_ticks_per_sec());
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else
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s->snapshot = s->tm4[tm - 1].clock;
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} |
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|
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if (!s->tm4[tm].freq)
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return s->tm4[tm].clock;
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return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
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s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); |
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case OIER:
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return s->irq_enabled;
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case OSSR: /* Status register */ |
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return s->events;
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case OWER:
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return s->reset3;
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case OMCR11: tm ++;
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/* fall through */
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case OMCR10: tm ++;
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/* fall through */
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case OMCR9: tm ++;
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/* fall through */
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case OMCR8: tm ++;
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/* fall through */
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case OMCR7: tm ++;
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/* fall through */
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case OMCR6: tm ++;
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/* fall through */
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case OMCR5: tm ++;
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/* fall through */
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case OMCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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return s->tm4[tm].control;
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case OSNR:
|
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return s->snapshot;
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default:
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badreg:
|
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hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset); |
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} |
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|
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return 0; |
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} |
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|
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static void pxa2xx_timer_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size)
|
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{
|
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int i, tm = 0; |
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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|
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switch (offset) {
|
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case OSMR3: tm ++;
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/* fall through */
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case OSMR2: tm ++;
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/* fall through */
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case OSMR1: tm ++;
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/* fall through */
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case OSMR0:
|
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s->timer[tm].value = value; |
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pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock)); |
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break;
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case OSMR11: tm ++;
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/* fall through */
|
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case OSMR10: tm ++;
|
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/* fall through */
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case OSMR9: tm ++;
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/* fall through */
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case OSMR8: tm ++;
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/* fall through */
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case OSMR7: tm ++;
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/* fall through */
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case OSMR6: tm ++;
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/* fall through */
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case OSMR5: tm ++;
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/* fall through */
|
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case OSMR4:
|
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].tm.value = value; |
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pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); |
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break;
|
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case OSCR:
|
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s->oldclock = s->clock; |
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s->lastload = qemu_get_clock_ns(vm_clock); |
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s->clock = value; |
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pxa2xx_timer_update(s, s->lastload); |
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break;
|
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case OSCR11: tm ++;
|
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/* fall through */
|
| 299 |
case OSCR10: tm ++;
|
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/* fall through */
|
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case OSCR9: tm ++;
|
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/* fall through */
|
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case OSCR8: tm ++;
|
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/* fall through */
|
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case OSCR7: tm ++;
|
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/* fall through */
|
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case OSCR6: tm ++;
|
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/* fall through */
|
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case OSCR5: tm ++;
|
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/* fall through */
|
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case OSCR4:
|
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if (!pxa2xx_timer_has_tm4(s))
|
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goto badreg;
|
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s->tm4[tm].oldclock = s->tm4[tm].clock; |
| 315 |
s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock); |
| 316 |
s->tm4[tm].clock = value; |
| 317 |
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
| 318 |
break;
|
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case OIER:
|
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s->irq_enabled = value & 0xfff;
|
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break;
|
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case OSSR: /* Status register */ |
| 323 |
value &= s->events; |
| 324 |
s->events &= ~value; |
| 325 |
for (i = 0; i < 4; i ++, value >>= 1) |
| 326 |
if (value & 1) |
| 327 |
qemu_irq_lower(s->timer[i].irq); |
| 328 |
if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) |
| 329 |
qemu_irq_lower(s->irq4); |
| 330 |
break;
|
| 331 |
case OWER: /* XXX: Reset on OSMR3 match? */ |
| 332 |
s->reset3 = value; |
| 333 |
break;
|
| 334 |
case OMCR7: tm ++;
|
| 335 |
/* fall through */
|
| 336 |
case OMCR6: tm ++;
|
| 337 |
/* fall through */
|
| 338 |
case OMCR5: tm ++;
|
| 339 |
/* fall through */
|
| 340 |
case OMCR4:
|
| 341 |
if (!pxa2xx_timer_has_tm4(s))
|
| 342 |
goto badreg;
|
| 343 |
s->tm4[tm].control = value & 0x0ff;
|
| 344 |
/* XXX Stop if running (shouldn't happen) */
|
| 345 |
if ((value & (1 << 7)) || tm == 0) |
| 346 |
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
|
| 347 |
else {
|
| 348 |
s->tm4[tm].freq = 0;
|
| 349 |
pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); |
| 350 |
} |
| 351 |
break;
|
| 352 |
case OMCR11: tm ++;
|
| 353 |
/* fall through */
|
| 354 |
case OMCR10: tm ++;
|
| 355 |
/* fall through */
|
| 356 |
case OMCR9: tm ++;
|
| 357 |
/* fall through */
|
| 358 |
case OMCR8: tm += 4; |
| 359 |
if (!pxa2xx_timer_has_tm4(s))
|
| 360 |
goto badreg;
|
| 361 |
s->tm4[tm].control = value & 0x3ff;
|
| 362 |
/* XXX Stop if running (shouldn't happen) */
|
| 363 |
if ((value & (1 << 7)) || !(tm & 1)) |
| 364 |
s->tm4[tm].freq = |
| 365 |
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
| 366 |
else {
|
| 367 |
s->tm4[tm].freq = 0;
|
| 368 |
pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); |
| 369 |
} |
| 370 |
break;
|
| 371 |
default:
|
| 372 |
badreg:
|
| 373 |
hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset); |
| 374 |
} |
| 375 |
} |
| 376 |
|
| 377 |
static const MemoryRegionOps pxa2xx_timer_ops = { |
| 378 |
.read = pxa2xx_timer_read, |
| 379 |
.write = pxa2xx_timer_write, |
| 380 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 381 |
}; |
| 382 |
|
| 383 |
static void pxa2xx_timer_tick(void *opaque) |
| 384 |
{
|
| 385 |
PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque; |
| 386 |
PXA2xxTimerInfo *i = t->info; |
| 387 |
|
| 388 |
if (i->irq_enabled & (1 << t->num)) { |
| 389 |
i->events |= 1 << t->num;
|
| 390 |
qemu_irq_raise(t->irq); |
| 391 |
} |
| 392 |
|
| 393 |
if (t->num == 3) |
| 394 |
if (i->reset3 & 1) { |
| 395 |
i->reset3 = 0;
|
| 396 |
qemu_system_reset_request(); |
| 397 |
} |
| 398 |
} |
| 399 |
|
| 400 |
static void pxa2xx_timer_tick4(void *opaque) |
| 401 |
{
|
| 402 |
PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque; |
| 403 |
PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info; |
| 404 |
|
| 405 |
pxa2xx_timer_tick(&t->tm); |
| 406 |
if (t->control & (1 << 3)) |
| 407 |
t->clock = 0;
|
| 408 |
if (t->control & (1 << 6)) |
| 409 |
pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
|
| 410 |
if (i->events & 0xff0) |
| 411 |
qemu_irq_raise(i->irq4); |
| 412 |
} |
| 413 |
|
| 414 |
static int pxa25x_timer_post_load(void *opaque, int version_id) |
| 415 |
{
|
| 416 |
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
| 417 |
int64_t now; |
| 418 |
int i;
|
| 419 |
|
| 420 |
now = qemu_get_clock_ns(vm_clock); |
| 421 |
pxa2xx_timer_update(s, now); |
| 422 |
|
| 423 |
if (pxa2xx_timer_has_tm4(s))
|
| 424 |
for (i = 0; i < 8; i ++) |
| 425 |
pxa2xx_timer_update4(s, now, i); |
| 426 |
|
| 427 |
return 0; |
| 428 |
} |
| 429 |
|
| 430 |
static int pxa2xx_timer_init(SysBusDevice *dev) |
| 431 |
{
|
| 432 |
int i;
|
| 433 |
PXA2xxTimerInfo *s; |
| 434 |
|
| 435 |
s = FROM_SYSBUS(PXA2xxTimerInfo, dev); |
| 436 |
s->irq_enabled = 0;
|
| 437 |
s->oldclock = 0;
|
| 438 |
s->clock = 0;
|
| 439 |
s->lastload = qemu_get_clock_ns(vm_clock); |
| 440 |
s->reset3 = 0;
|
| 441 |
|
| 442 |
for (i = 0; i < 4; i ++) { |
| 443 |
s->timer[i].value = 0;
|
| 444 |
sysbus_init_irq(dev, &s->timer[i].irq); |
| 445 |
s->timer[i].info = s; |
| 446 |
s->timer[i].num = i; |
| 447 |
s->timer[i].qtimer = qemu_new_timer_ns(vm_clock, |
| 448 |
pxa2xx_timer_tick, &s->timer[i]); |
| 449 |
} |
| 450 |
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { |
| 451 |
sysbus_init_irq(dev, &s->irq4); |
| 452 |
|
| 453 |
for (i = 0; i < 8; i ++) { |
| 454 |
s->tm4[i].tm.value = 0;
|
| 455 |
s->tm4[i].tm.info = s; |
| 456 |
s->tm4[i].tm.num = i + 4;
|
| 457 |
s->tm4[i].freq = 0;
|
| 458 |
s->tm4[i].control = 0x0;
|
| 459 |
s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock, |
| 460 |
pxa2xx_timer_tick4, &s->tm4[i]); |
| 461 |
} |
| 462 |
} |
| 463 |
|
| 464 |
memory_region_init_io(&s->iomem, &pxa2xx_timer_ops, s, |
| 465 |
"pxa2xx-timer", 0x00001000); |
| 466 |
sysbus_init_mmio(dev, &s->iomem); |
| 467 |
|
| 468 |
return 0; |
| 469 |
} |
| 470 |
|
| 471 |
static const VMStateDescription vmstate_pxa2xx_timer0_regs = { |
| 472 |
.name = "pxa2xx_timer0",
|
| 473 |
.version_id = 2,
|
| 474 |
.minimum_version_id = 2,
|
| 475 |
.minimum_version_id_old = 2,
|
| 476 |
.fields = (VMStateField[]) {
|
| 477 |
VMSTATE_UINT32(value, PXA2xxTimer0), |
| 478 |
VMSTATE_END_OF_LIST(), |
| 479 |
}, |
| 480 |
}; |
| 481 |
|
| 482 |
static const VMStateDescription vmstate_pxa2xx_timer4_regs = { |
| 483 |
.name = "pxa2xx_timer4",
|
| 484 |
.version_id = 1,
|
| 485 |
.minimum_version_id = 1,
|
| 486 |
.minimum_version_id_old = 1,
|
| 487 |
.fields = (VMStateField[]) {
|
| 488 |
VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
|
| 489 |
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
| 490 |
VMSTATE_INT32(oldclock, PXA2xxTimer4), |
| 491 |
VMSTATE_INT32(clock, PXA2xxTimer4), |
| 492 |
VMSTATE_UINT64(lastload, PXA2xxTimer4), |
| 493 |
VMSTATE_UINT32(freq, PXA2xxTimer4), |
| 494 |
VMSTATE_UINT32(control, PXA2xxTimer4), |
| 495 |
VMSTATE_END_OF_LIST(), |
| 496 |
}, |
| 497 |
}; |
| 498 |
|
| 499 |
static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id) |
| 500 |
{
|
| 501 |
return pxa2xx_timer_has_tm4(opaque);
|
| 502 |
} |
| 503 |
|
| 504 |
static const VMStateDescription vmstate_pxa2xx_timer_regs = { |
| 505 |
.name = "pxa2xx_timer",
|
| 506 |
.version_id = 1,
|
| 507 |
.minimum_version_id = 1,
|
| 508 |
.minimum_version_id_old = 1,
|
| 509 |
.post_load = pxa25x_timer_post_load, |
| 510 |
.fields = (VMStateField[]) {
|
| 511 |
VMSTATE_INT32(clock, PXA2xxTimerInfo), |
| 512 |
VMSTATE_INT32(oldclock, PXA2xxTimerInfo), |
| 513 |
VMSTATE_UINT64(lastload, PXA2xxTimerInfo), |
| 514 |
VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1, |
| 515 |
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
| 516 |
VMSTATE_UINT32(events, PXA2xxTimerInfo), |
| 517 |
VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo), |
| 518 |
VMSTATE_UINT32(reset3, PXA2xxTimerInfo), |
| 519 |
VMSTATE_UINT32(snapshot, PXA2xxTimerInfo), |
| 520 |
VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
|
| 521 |
pxa2xx_timer_has_tm4_test, 0,
|
| 522 |
vmstate_pxa2xx_timer4_regs, PXA2xxTimer4), |
| 523 |
VMSTATE_END_OF_LIST(), |
| 524 |
} |
| 525 |
}; |
| 526 |
|
| 527 |
static Property pxa25x_timer_dev_properties[] = {
|
| 528 |
DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
|
| 529 |
DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
| 530 |
PXA2XX_TIMER_HAVE_TM4, false),
|
| 531 |
DEFINE_PROP_END_OF_LIST(), |
| 532 |
}; |
| 533 |
|
| 534 |
static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data) |
| 535 |
{
|
| 536 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 537 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 538 |
|
| 539 |
k->init = pxa2xx_timer_init; |
| 540 |
dc->desc = "PXA25x timer";
|
| 541 |
dc->vmsd = &vmstate_pxa2xx_timer_regs; |
| 542 |
dc->props = pxa25x_timer_dev_properties; |
| 543 |
} |
| 544 |
|
| 545 |
static const TypeInfo pxa25x_timer_dev_info = { |
| 546 |
.name = "pxa25x-timer",
|
| 547 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 548 |
.instance_size = sizeof(PXA2xxTimerInfo),
|
| 549 |
.class_init = pxa25x_timer_dev_class_init, |
| 550 |
}; |
| 551 |
|
| 552 |
static Property pxa27x_timer_dev_properties[] = {
|
| 553 |
DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
|
| 554 |
DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
| 555 |
PXA2XX_TIMER_HAVE_TM4, true),
|
| 556 |
DEFINE_PROP_END_OF_LIST(), |
| 557 |
}; |
| 558 |
|
| 559 |
static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data) |
| 560 |
{
|
| 561 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 562 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 563 |
|
| 564 |
k->init = pxa2xx_timer_init; |
| 565 |
dc->desc = "PXA27x timer";
|
| 566 |
dc->vmsd = &vmstate_pxa2xx_timer_regs; |
| 567 |
dc->props = pxa27x_timer_dev_properties; |
| 568 |
} |
| 569 |
|
| 570 |
static const TypeInfo pxa27x_timer_dev_info = { |
| 571 |
.name = "pxa27x-timer",
|
| 572 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 573 |
.instance_size = sizeof(PXA2xxTimerInfo),
|
| 574 |
.class_init = pxa27x_timer_dev_class_init, |
| 575 |
}; |
| 576 |
|
| 577 |
static void pxa2xx_timer_register_types(void) |
| 578 |
{
|
| 579 |
type_register_static(&pxa25x_timer_dev_info); |
| 580 |
type_register_static(&pxa27x_timer_dev_info); |
| 581 |
} |
| 582 |
|
| 583 |
type_init(pxa2xx_timer_register_types) |