root / include / hw / i386 / ich9.h @ 0d09e41a
History | View | Annotate | Download (8.1 kB)
1 |
#ifndef HW_ICH9_H
|
---|---|
2 |
#define HW_ICH9_H
|
3 |
|
4 |
#include "hw/hw.h" |
5 |
#include "qemu/range.h" |
6 |
#include "hw/isa/isa.h" |
7 |
#include "hw/sysbus.h" |
8 |
#include "hw/i386/pc.h" |
9 |
#include "hw/isa/apm.h" |
10 |
#include "hw/i386/ioapic.h" |
11 |
#include "hw/pci/pci.h" |
12 |
#include "hw/pci/pcie_host.h" |
13 |
#include "hw/pci/pci_bridge.h" |
14 |
#include "hw/acpi/acpi.h" |
15 |
#include "hw/acpi/ich9.h" |
16 |
#include "hw/pci/pci_bus.h" |
17 |
|
18 |
void ich9_lpc_set_irq(void *opaque, int irq_num, int level); |
19 |
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); |
20 |
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); |
21 |
void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
|
22 |
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus); |
23 |
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
|
24 |
|
25 |
#define ICH9_CC_SIZE (16 * 1024) /* 16KB */ |
26 |
|
27 |
#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC" |
28 |
#define ICH9_LPC_DEVICE(obj) \
|
29 |
OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE) |
30 |
|
31 |
typedef struct ICH9LPCState { |
32 |
/* ICH9 LPC PCI to ISA bridge */
|
33 |
PCIDevice d; |
34 |
|
35 |
/* (pci device, intx) -> pirq
|
36 |
* In real chipset case, the unused slots are never used
|
37 |
* as ICH9 supports only D25-D32 irq routing.
|
38 |
* On the other hand in qemu case, any slot/function can be populated
|
39 |
* via command line option.
|
40 |
* So fallback interrupt routing for any devices in any slots is necessary.
|
41 |
*/
|
42 |
uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; |
43 |
|
44 |
APMState apm; |
45 |
ICH9LPCPMRegs pm; |
46 |
uint32_t sci_level; /* track sci level */
|
47 |
|
48 |
/* 10.1 Chipset Configuration registers(Memory Space)
|
49 |
which is pointed by RCBA */
|
50 |
uint8_t chip_config[ICH9_CC_SIZE]; |
51 |
|
52 |
/*
|
53 |
* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
|
54 |
*
|
55 |
* register contents and IO memory region
|
56 |
*/
|
57 |
uint8_t rst_cnt; |
58 |
MemoryRegion rst_cnt_mem; |
59 |
|
60 |
/* isa bus */
|
61 |
ISABus *isa_bus; |
62 |
MemoryRegion rbca_mem; |
63 |
Notifier machine_ready; |
64 |
|
65 |
qemu_irq *pic; |
66 |
qemu_irq *ioapic; |
67 |
} ICH9LPCState; |
68 |
|
69 |
#define Q35_MASK(bit, ms_bit, ls_bit) \
|
70 |
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) |
71 |
|
72 |
/* ICH9: Chipset Configuration Registers */
|
73 |
#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) |
74 |
|
75 |
#define ICH9_CC
|
76 |
#define ICH9_CC_D28IP 0x310C |
77 |
#define ICH9_CC_D28IP_SHIFT 4 |
78 |
#define ICH9_CC_D28IP_MASK 0xf |
79 |
#define ICH9_CC_D28IP_DEFAULT 0x00214321 |
80 |
#define ICH9_CC_D31IR 0x3140 |
81 |
#define ICH9_CC_D30IR 0x3142 |
82 |
#define ICH9_CC_D29IR 0x3144 |
83 |
#define ICH9_CC_D28IR 0x3146 |
84 |
#define ICH9_CC_D27IR 0x3148 |
85 |
#define ICH9_CC_D26IR 0x314C |
86 |
#define ICH9_CC_D25IR 0x3150 |
87 |
#define ICH9_CC_DIR_DEFAULT 0x3210 |
88 |
#define ICH9_CC_D30IR_DEFAULT 0x0 |
89 |
#define ICH9_CC_DIR_SHIFT 4 |
90 |
#define ICH9_CC_DIR_MASK 0x7 |
91 |
#define ICH9_CC_OIC 0x31FF |
92 |
#define ICH9_CC_OIC_AEN 0x1 |
93 |
|
94 |
/* D28:F[0-5] */
|
95 |
#define ICH9_PCIE_DEV 28 |
96 |
#define ICH9_PCIE_FUNC_MAX 6 |
97 |
|
98 |
|
99 |
/* D29:F0 USB UHCI Controller #1 */
|
100 |
#define ICH9_USB_UHCI1_DEV 29 |
101 |
#define ICH9_USB_UHCI1_FUNC 0 |
102 |
|
103 |
/* D30:F0 DMI-to-PCI brdige */
|
104 |
#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" |
105 |
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 |
106 |
|
107 |
#define ICH9_D2P_BRIDGE_DEV 30 |
108 |
#define ICH9_D2P_BRIDGE_FUNC 0 |
109 |
|
110 |
#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) |
111 |
|
112 |
#define ICH9_D2P_A2_REVISION 0x92 |
113 |
|
114 |
/* D31:F0 LPC Processor Interface */
|
115 |
#define ICH9_RST_CNT_IOPORT 0xCF9 |
116 |
|
117 |
/* D31:F1 LPC controller */
|
118 |
#define ICH9_A2_LPC "ICH9 A2 LPC" |
119 |
#define ICH9_A2_LPC_SAVEVM_VERSION 0 |
120 |
|
121 |
#define ICH9_LPC_DEV 31 |
122 |
#define ICH9_LPC_FUNC 0 |
123 |
|
124 |
#define ICH9_A2_LPC_REVISION 0x2 |
125 |
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ |
126 |
|
127 |
#define ICH9_LPC_PMBASE 0x40 |
128 |
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7) |
129 |
#define ICH9_LPC_PMBASE_RTE 0x1 |
130 |
#define ICH9_LPC_PMBASE_DEFAULT 0x1 |
131 |
#define ICH9_LPC_ACPI_CTRL 0x44 |
132 |
#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 |
133 |
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0) |
134 |
#define ICH9_LPC_ACPI_CTRL_9 0x0 |
135 |
#define ICH9_LPC_ACPI_CTRL_10 0x1 |
136 |
#define ICH9_LPC_ACPI_CTRL_11 0x2 |
137 |
#define ICH9_LPC_ACPI_CTRL_20 0x4 |
138 |
#define ICH9_LPC_ACPI_CTRL_21 0x5 |
139 |
#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 |
140 |
|
141 |
#define ICH9_LPC_PIRQA_ROUT 0x60 |
142 |
#define ICH9_LPC_PIRQB_ROUT 0x61 |
143 |
#define ICH9_LPC_PIRQC_ROUT 0x62 |
144 |
#define ICH9_LPC_PIRQD_ROUT 0x63 |
145 |
|
146 |
#define ICH9_LPC_PIRQE_ROUT 0x68 |
147 |
#define ICH9_LPC_PIRQF_ROUT 0x69 |
148 |
#define ICH9_LPC_PIRQG_ROUT 0x6a |
149 |
#define ICH9_LPC_PIRQH_ROUT 0x6b |
150 |
|
151 |
#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 |
152 |
#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) |
153 |
#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 |
154 |
|
155 |
#define ICH9_LPC_RCBA 0xf0 |
156 |
#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) |
157 |
#define ICH9_LPC_RCBA_EN 0x1 |
158 |
#define ICH9_LPC_RCBA_DEFAULT 0x0 |
159 |
|
160 |
#define ICH9_LPC_PIC_NUM_PINS 16 |
161 |
#define ICH9_LPC_IOAPIC_NUM_PINS 24 |
162 |
|
163 |
/* D31:F2 SATA Controller #1 */
|
164 |
#define ICH9_SATA1_DEV 31 |
165 |
#define ICH9_SATA1_FUNC 2 |
166 |
|
167 |
/* D30:F1 power management I/O registers
|
168 |
offset from the address ICH9_LPC_PMBASE */
|
169 |
|
170 |
/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
|
171 |
#define ICH9_PMIO_SIZE 128 |
172 |
#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) |
173 |
|
174 |
#define ICH9_PMIO_PM1_STS 0x00 |
175 |
#define ICH9_PMIO_PM1_EN 0x02 |
176 |
#define ICH9_PMIO_PM1_CNT 0x04 |
177 |
#define ICH9_PMIO_PM1_TMR 0x08 |
178 |
#define ICH9_PMIO_GPE0_STS 0x20 |
179 |
#define ICH9_PMIO_GPE0_EN 0x28 |
180 |
#define ICH9_PMIO_GPE0_LEN 16 |
181 |
#define ICH9_PMIO_SMI_EN 0x30 |
182 |
#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) |
183 |
#define ICH9_PMIO_SMI_STS 0x34 |
184 |
|
185 |
/* FADT ACPI_ENABLE/ACPI_DISABLE */
|
186 |
#define ICH9_APM_ACPI_ENABLE 0x2 |
187 |
#define ICH9_APM_ACPI_DISABLE 0x3 |
188 |
|
189 |
|
190 |
/* D31:F3 SMBus controller */
|
191 |
#define ICH9_A2_SMB_REVISION 0x02 |
192 |
#define ICH9_SMB_PI 0x00 |
193 |
|
194 |
#define ICH9_SMB_SMBMBAR0 0x10 |
195 |
#define ICH9_SMB_SMBMBAR1 0x14 |
196 |
#define ICH9_SMB_SMBM_BAR 0 |
197 |
#define ICH9_SMB_SMBM_SIZE (1 << 8) |
198 |
#define ICH9_SMB_SMB_BASE 0x20 |
199 |
#define ICH9_SMB_SMB_BASE_BAR 4 |
200 |
#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) |
201 |
#define ICH9_SMB_HOSTC 0x40 |
202 |
#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) |
203 |
#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) |
204 |
#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) |
205 |
#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) |
206 |
|
207 |
/* D31:F3 SMBus I/O and memory mapped I/O registers */
|
208 |
#define ICH9_SMB_DEV 31 |
209 |
#define ICH9_SMB_FUNC 3 |
210 |
|
211 |
#define ICH9_SMB_HST_STS 0x00 |
212 |
#define ICH9_SMB_HST_CNT 0x02 |
213 |
#define ICH9_SMB_HST_CMD 0x03 |
214 |
#define ICH9_SMB_XMIT_SLVA 0x04 |
215 |
#define ICH9_SMB_HST_D0 0x05 |
216 |
#define ICH9_SMB_HST_D1 0x06 |
217 |
#define ICH9_SMB_HOST_BLOCK_DB 0x07 |
218 |
|
219 |
#endif /* HW_ICH9_H */ |