root / target-i386 / machine.c @ 0d09e41a
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#include "hw/hw.h" |
|---|---|
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#include "hw/boards.h" |
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#include "hw/i386/pc.h" |
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#include "hw/isa/isa.h" |
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|
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#include "cpu.h" |
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#include "sysemu/kvm.h" |
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|
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static const VMStateDescription vmstate_segment = { |
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.name = "segment",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
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VMSTATE_UINT32(selector, SegmentCache), |
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VMSTATE_UINTTL(base, SegmentCache), |
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VMSTATE_UINT32(limit, SegmentCache), |
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VMSTATE_UINT32(flags, SegmentCache), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_SEGMENT(_field, _state) { \
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.name = (stringify(_field)), \ |
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.size = sizeof(SegmentCache), \
|
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.vmsd = &vmstate_segment, \ |
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.flags = VMS_STRUCT, \ |
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.offset = offsetof(_state, _field) \ |
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+ type_check(SegmentCache,typeof_field(_state, _field)) \ |
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} |
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|
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#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
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|
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static const VMStateDescription vmstate_xmm_reg = { |
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.name = "xmm_reg",
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
|
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
|
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_XMM_REGS(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
|
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|
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/* YMMH format is the same as XMM */
|
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static const VMStateDescription vmstate_ymmh_reg = { |
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.name = "ymmh_reg",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg) |
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|
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static const VMStateDescription vmstate_mtrr_var = { |
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.name = "mtrr_var",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(base, MTRRVar), |
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VMSTATE_UINT64(mask, MTRRVar), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) |
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|
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static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size) |
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{
|
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fprintf(stderr, "call put_fpreg() with invalid arguments\n");
|
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exit(0);
|
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} |
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|
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/* XXX: add that in a FPU generic layer */
|
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union x86_longdouble {
|
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uint64_t mant; |
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uint16_t exp; |
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}; |
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|
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#define MANTD1(fp) (fp & ((1LL << 52) - 1)) |
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#define EXPBIAS1 1023 |
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#define EXPD1(fp) ((fp >> 52) & 0x7FF) |
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#define SIGND1(fp) ((fp >> 32) & 0x80000000) |
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|
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static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp) |
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{
|
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int e;
|
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/* mantissa */
|
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p->mant = (MANTD1(temp) << 11) | (1LL << 63); |
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/* exponent + sign */
|
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e = EXPD1(temp) - EXPBIAS1 + 16383;
|
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e |= SIGND1(temp) >> 16;
|
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p->exp = e; |
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} |
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|
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static int get_fpreg(QEMUFile *f, void *opaque, size_t size) |
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{
|
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FPReg *fp_reg = opaque; |
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uint64_t mant; |
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uint16_t exp; |
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|
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qemu_get_be64s(f, &mant); |
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qemu_get_be16s(f, &exp); |
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fp_reg->d = cpu_set_fp80(mant, exp); |
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return 0; |
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} |
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|
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static void put_fpreg(QEMUFile *f, void *opaque, size_t size) |
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{
|
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FPReg *fp_reg = opaque; |
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uint64_t mant; |
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uint16_t exp; |
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/* we save the real CPU data (in case of MMX usage only 'mant'
|
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contains the MMX register */
|
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cpu_get_fp80(&mant, &exp, fp_reg->d); |
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qemu_put_be64s(f, &mant); |
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qemu_put_be16s(f, &exp); |
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} |
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|
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static const VMStateInfo vmstate_fpreg = { |
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.name = "fpreg",
|
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.get = get_fpreg, |
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.put = put_fpreg, |
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}; |
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|
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static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size) |
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{
|
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union x86_longdouble *p = opaque;
|
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uint64_t mant; |
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|
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qemu_get_be64s(f, &mant); |
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p->mant = mant; |
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p->exp = 0xffff;
|
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return 0; |
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} |
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|
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static const VMStateInfo vmstate_fpreg_1_mmx = { |
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.name = "fpreg_1_mmx",
|
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.get = get_fpreg_1_mmx, |
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.put = put_fpreg_error, |
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}; |
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|
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static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size) |
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{
|
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union x86_longdouble *p = opaque;
|
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uint64_t mant; |
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|
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qemu_get_be64s(f, &mant); |
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fp64_to_fp80(p, mant); |
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return 0; |
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} |
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|
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static const VMStateInfo vmstate_fpreg_1_no_mmx = { |
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.name = "fpreg_1_no_mmx",
|
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.get = get_fpreg_1_no_mmx, |
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.put = put_fpreg_error, |
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}; |
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|
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static bool fpregs_is_0(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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|
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return (env->fpregs_format_vmstate == 0); |
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} |
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|
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static bool fpregs_is_1_mmx(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int guess_mmx;
|
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|
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guess_mmx = ((env->fptag_vmstate == 0xff) &&
|
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(env->fpus_vmstate & 0x3800) == 0); |
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return (guess_mmx && (env->fpregs_format_vmstate == 1)); |
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} |
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|
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static bool fpregs_is_1_no_mmx(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int guess_mmx;
|
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|
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guess_mmx = ((env->fptag_vmstate == 0xff) &&
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(env->fpus_vmstate & 0x3800) == 0); |
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return (!guess_mmx && (env->fpregs_format_vmstate == 1)); |
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} |
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|
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#define VMSTATE_FP_REGS(_field, _state, _n) \
|
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \ |
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \ |
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg) |
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|
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static bool version_is_5(void *opaque, int version_id) |
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{
|
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return version_id == 5; |
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} |
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|
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#ifdef TARGET_X86_64
|
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static bool less_than_7(void *opaque, int version_id) |
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{
|
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return version_id < 7; |
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} |
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|
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static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) |
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{
|
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uint64_t *v = pv; |
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*v = qemu_get_be32(f); |
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return 0; |
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} |
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|
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static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) |
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{
|
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uint64_t *v = pv; |
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qemu_put_be32(f, *v); |
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} |
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|
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static const VMStateInfo vmstate_hack_uint64_as_uint32 = { |
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.name = "uint64_as_uint32",
|
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.get = get_uint64_as_uint32, |
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.put = put_uint64_as_uint32, |
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}; |
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|
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#define VMSTATE_HACK_UINT32(_f, _s, _t) \
|
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VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
|
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#endif
|
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|
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static void cpu_pre_save(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int i;
|
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|
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/* FPU */
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env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
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env->fptag_vmstate = 0;
|
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for(i = 0; i < 8; i++) { |
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env->fptag_vmstate |= ((!env->fptags[i]) << i); |
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} |
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|
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env->fpregs_format_vmstate = 0;
|
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} |
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|
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static int cpu_post_load(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int i;
|
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|
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/* XXX: restore FPU round state */
|
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env->fpstt = (env->fpus_vmstate >> 11) & 7; |
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env->fpus = env->fpus_vmstate & ~0x3800;
|
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env->fptag_vmstate ^= 0xff;
|
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for(i = 0; i < 8; i++) { |
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env->fptags[i] = (env->fptag_vmstate >> i) & 1;
|
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} |
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|
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cpu_breakpoint_remove_all(env, BP_CPU); |
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cpu_watchpoint_remove_all(env, BP_CPU); |
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for (i = 0; i < DR7_MAX_BP; i++) { |
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hw_breakpoint_insert(env, i); |
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} |
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tlb_flush(env, 1);
|
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|
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return 0; |
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} |
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|
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static bool async_pf_msr_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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|
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return cpu->env.async_pf_en_msr != 0; |
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} |
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|
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static bool pv_eoi_msr_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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|
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return cpu->env.pv_eoi_en_msr != 0; |
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} |
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|
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static const VMStateDescription vmstate_async_pf_msr = { |
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.name = "cpu/async_pf_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static const VMStateDescription vmstate_pv_eoi_msr = { |
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.name = "cpu/async_pv_eoi_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static bool fpop_ip_dp_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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|
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return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; |
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} |
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|
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static const VMStateDescription vmstate_fpop_ip_dp = { |
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.name = "cpu/fpop_ip_dp",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT16(env.fpop, X86CPU), |
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VMSTATE_UINT64(env.fpip, X86CPU), |
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VMSTATE_UINT64(env.fpdp, X86CPU), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static bool tsc_adjust_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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|
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return env->tsc_adjust != 0; |
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} |
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|
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static const VMStateDescription vmstate_msr_tsc_adjust = { |
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.name = "cpu/msr_tsc_adjust",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField[]) {
|
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VMSTATE_UINT64(env.tsc_adjust, X86CPU), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static bool tscdeadline_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
| 361 |
|
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return env->tsc_deadline != 0; |
| 363 |
} |
| 364 |
|
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static const VMStateDescription vmstate_msr_tscdeadline = { |
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.name = "cpu/msr_tscdeadline",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.tsc_deadline, X86CPU), |
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VMSTATE_END_OF_LIST() |
| 373 |
} |
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}; |
| 375 |
|
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static bool misc_enable_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
| 379 |
CPUX86State *env = &cpu->env; |
| 380 |
|
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return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
|
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} |
| 383 |
|
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static const VMStateDescription vmstate_msr_ia32_misc_enable = { |
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.name = "cpu/msr_ia32_misc_enable",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), |
| 391 |
VMSTATE_END_OF_LIST() |
| 392 |
} |
| 393 |
}; |
| 394 |
|
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const VMStateDescription vmstate_x86_cpu = {
|
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.name = "cpu",
|
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.version_id = 12,
|
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.minimum_version_id = 3,
|
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.minimum_version_id_old = 3,
|
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.pre_save = cpu_pre_save, |
| 401 |
.post_load = cpu_post_load, |
| 402 |
.fields = (VMStateField []) {
|
| 403 |
VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), |
| 404 |
VMSTATE_UINTTL(env.eip, X86CPU), |
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VMSTATE_UINTTL(env.eflags, X86CPU), |
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VMSTATE_UINT32(env.hflags, X86CPU), |
| 407 |
/* FPU */
|
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VMSTATE_UINT16(env.fpuc, X86CPU), |
| 409 |
VMSTATE_UINT16(env.fpus_vmstate, X86CPU), |
| 410 |
VMSTATE_UINT16(env.fptag_vmstate, X86CPU), |
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VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), |
| 412 |
VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
|
| 413 |
|
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VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
|
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VMSTATE_SEGMENT(env.ldt, X86CPU), |
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VMSTATE_SEGMENT(env.tr, X86CPU), |
| 417 |
VMSTATE_SEGMENT(env.gdt, X86CPU), |
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VMSTATE_SEGMENT(env.idt, X86CPU), |
| 419 |
|
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VMSTATE_UINT32(env.sysenter_cs, X86CPU), |
| 421 |
#ifdef TARGET_X86_64
|
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/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
|
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VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7), |
| 424 |
VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7), |
| 425 |
VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
|
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VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
|
| 427 |
#else
|
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VMSTATE_UINTTL(env.sysenter_esp, X86CPU), |
| 429 |
VMSTATE_UINTTL(env.sysenter_eip, X86CPU), |
| 430 |
#endif
|
| 431 |
|
| 432 |
VMSTATE_UINTTL(env.cr[0], X86CPU),
|
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VMSTATE_UINTTL(env.cr[2], X86CPU),
|
| 434 |
VMSTATE_UINTTL(env.cr[3], X86CPU),
|
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VMSTATE_UINTTL(env.cr[4], X86CPU),
|
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VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
|
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/* MMU */
|
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VMSTATE_INT32(env.a20_mask, X86CPU), |
| 439 |
/* XMM */
|
| 440 |
VMSTATE_UINT32(env.mxcsr, X86CPU), |
| 441 |
VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS), |
| 442 |
|
| 443 |
#ifdef TARGET_X86_64
|
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VMSTATE_UINT64(env.efer, X86CPU), |
| 445 |
VMSTATE_UINT64(env.star, X86CPU), |
| 446 |
VMSTATE_UINT64(env.lstar, X86CPU), |
| 447 |
VMSTATE_UINT64(env.cstar, X86CPU), |
| 448 |
VMSTATE_UINT64(env.fmask, X86CPU), |
| 449 |
VMSTATE_UINT64(env.kernelgsbase, X86CPU), |
| 450 |
#endif
|
| 451 |
VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
|
| 452 |
|
| 453 |
VMSTATE_UINT64_V(env.pat, X86CPU, 5),
|
| 454 |
VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
|
| 455 |
|
| 456 |
VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5), |
| 457 |
VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
|
| 458 |
VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
|
| 459 |
VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
|
| 460 |
VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
|
| 461 |
VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
|
| 462 |
VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
|
| 463 |
VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
|
| 464 |
VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
|
| 465 |
VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
|
| 466 |
VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
|
| 467 |
/* MTRRs */
|
| 468 |
VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8), |
| 469 |
VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
|
| 470 |
VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8), |
| 471 |
/* KVM-related states */
|
| 472 |
VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
|
| 473 |
VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
|
| 474 |
VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
|
| 475 |
VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
|
| 476 |
VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
|
| 477 |
VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
|
| 478 |
VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
|
| 479 |
VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
|
| 480 |
VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
|
| 481 |
/* MCE */
|
| 482 |
VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
|
| 483 |
VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
|
| 484 |
VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
|
| 485 |
VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10), |
| 486 |
/* rdtscp */
|
| 487 |
VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
|
| 488 |
/* KVM pvclock msr */
|
| 489 |
VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
|
| 490 |
VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
|
| 491 |
/* XSAVE related fields */
|
| 492 |
VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
|
| 493 |
VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
|
| 494 |
VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
|
| 495 |
VMSTATE_END_OF_LIST() |
| 496 |
/* The above list is not sorted /wrt version numbers, watch out! */
|
| 497 |
}, |
| 498 |
.subsections = (VMStateSubsection []) {
|
| 499 |
{
|
| 500 |
.vmsd = &vmstate_async_pf_msr, |
| 501 |
.needed = async_pf_msr_needed, |
| 502 |
} , {
|
| 503 |
.vmsd = &vmstate_pv_eoi_msr, |
| 504 |
.needed = pv_eoi_msr_needed, |
| 505 |
} , {
|
| 506 |
.vmsd = &vmstate_fpop_ip_dp, |
| 507 |
.needed = fpop_ip_dp_needed, |
| 508 |
}, {
|
| 509 |
.vmsd = &vmstate_msr_tsc_adjust, |
| 510 |
.needed = tsc_adjust_needed, |
| 511 |
}, {
|
| 512 |
.vmsd = &vmstate_msr_tscdeadline, |
| 513 |
.needed = tscdeadline_needed, |
| 514 |
}, {
|
| 515 |
.vmsd = &vmstate_msr_ia32_misc_enable, |
| 516 |
.needed = misc_enable_needed, |
| 517 |
} , {
|
| 518 |
/* empty */
|
| 519 |
} |
| 520 |
} |
| 521 |
}; |