root / target-lm32 / translate.c @ 0d09e41a
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/*
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* LatticeMico32 main translation routines.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "disas/disas.h" |
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#include "helper.h" |
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#include "tcg-op.h" |
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|
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#include "hw/lm32/lm32_pic.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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#define DISAS_LM32 1 |
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#if DISAS_LM32
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# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
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#else
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# define LOG_DIS(...) do { } while (0) |
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#endif
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|
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1)) |
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#define MEM_INDEX 0 |
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static TCGv_ptr cpu_env;
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static TCGv cpu_R[32]; |
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static TCGv cpu_pc;
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static TCGv cpu_ie;
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static TCGv cpu_icc;
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static TCGv cpu_dcc;
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static TCGv cpu_cc;
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static TCGv cpu_cfg;
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static TCGv cpu_eba;
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static TCGv cpu_dc;
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static TCGv cpu_deba;
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static TCGv cpu_bp[4]; |
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static TCGv cpu_wp[4]; |
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|
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#include "exec/gen-icount.h" |
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enum {
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OP_FMT_RI, |
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OP_FMT_RR, |
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OP_FMT_CR, |
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OP_FMT_I |
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}; |
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|
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/* This is the state at translation time. */
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typedef struct DisasContext { |
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CPULM32State *env; |
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target_ulong pc; |
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|
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/* Decoder. */
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int format;
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uint32_t ir; |
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uint8_t opcode; |
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uint8_t r0, r1, r2, csr; |
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uint16_t imm5; |
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uint16_t imm16; |
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uint32_t imm26; |
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unsigned int delayed_branch; |
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unsigned int tb_flags, synced_flags; /* tb dependent flags. */ |
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int is_jmp;
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int nr_nops;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext; |
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|
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static const char *regnames[] = { |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
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"r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra", |
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"r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0", |
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"wp1", "wp2", "wp3" |
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}; |
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static inline int zero_extend(unsigned int val, int width) |
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{
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return val & ((1 << width) - 1); |
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} |
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static inline int sign_extend(unsigned int val, int width) |
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{
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int sval;
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/* LSL. */
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val <<= 32 - width;
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sval = val; |
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/* ASR. */
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sval >>= 32 - width;
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return sval;
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} |
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static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) |
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{
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TCGv_i32 tmp = tcg_const_i32(index); |
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gen_helper_raise_exception(cpu_env, tmp); |
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tcg_temp_free_i32(tmp); |
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} |
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
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{
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TranslationBlock *tb; |
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tb = dc->tb; |
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if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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likely(!dc->singlestep_enabled)) {
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tcg_gen_goto_tb(n); |
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tcg_gen_movi_tl(cpu_pc, dest); |
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tcg_gen_exit_tb((tcg_target_long)tb + n); |
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} else {
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tcg_gen_movi_tl(cpu_pc, dest); |
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if (dc->singlestep_enabled) {
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t_gen_raise_exception(dc, EXCP_DEBUG); |
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} |
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tcg_gen_exit_tb(0);
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} |
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} |
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static void dec_add(DisasContext *dc) |
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->r0 == R_R0) {
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if (dc->r1 == R_R0 && dc->imm16 == 0) { |
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LOG_DIS("nop\n");
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} else {
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LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16)); |
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} |
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} else {
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LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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} |
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} else {
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LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
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if (dc->format == OP_FMT_RI) {
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tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
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sign_extend(dc->imm16, 16));
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} else {
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tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
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} |
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} |
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static void dec_and(DisasContext *dc) |
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{
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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} else {
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LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
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if (dc->format == OP_FMT_RI) {
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tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
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zero_extend(dc->imm16, 16));
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} else {
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if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) { |
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tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
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gen_helper_hlt(cpu_env); |
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} else {
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tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
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} |
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} |
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} |
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static void dec_andhi(DisasContext *dc) |
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{
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LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
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tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
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} |
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static void dec_b(DisasContext *dc) |
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{
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if (dc->r0 == R_RA) {
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LOG_DIS("ret\n");
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} else if (dc->r0 == R_EA) { |
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LOG_DIS("eret\n");
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} else if (dc->r0 == R_BA) { |
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LOG_DIS("bret\n");
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} else {
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LOG_DIS("b r%d\n", dc->r0);
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} |
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/* restore IE.IE in case of an eret */
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if (dc->r0 == R_EA) {
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TCGv t0 = tcg_temp_new(); |
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int l1 = gen_new_label();
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tcg_gen_andi_tl(t0, cpu_ie, IE_EIE); |
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tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE); |
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tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1); |
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tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); |
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gen_set_label(l1); |
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tcg_temp_free(t0); |
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} else if (dc->r0 == R_BA) { |
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TCGv t0 = tcg_temp_new(); |
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int l1 = gen_new_label();
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tcg_gen_andi_tl(t0, cpu_ie, IE_BIE); |
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tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE); |
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tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1); |
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tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); |
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gen_set_label(l1); |
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tcg_temp_free(t0); |
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} |
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tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]); |
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dc->is_jmp = DISAS_JUMP; |
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} |
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|
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static void dec_bi(DisasContext *dc) |
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{
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LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26)); |
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gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26))); |
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dc->is_jmp = DISAS_TB_JUMP; |
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} |
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static inline void gen_cond_branch(DisasContext *dc, int cond) |
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{
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int l1;
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l1 = gen_new_label(); |
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tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1); |
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gen_goto_tb(dc, 0, dc->pc + 4); |
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gen_set_label(l1); |
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gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16))); |
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dc->is_jmp = DISAS_TB_JUMP; |
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} |
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|
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static void dec_be(DisasContext *dc) |
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{
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LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_EQ); |
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} |
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static void dec_bg(DisasContext *dc) |
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{
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LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16 * 4)); |
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gen_cond_branch(dc, TCG_COND_GT); |
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} |
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|
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static void dec_bge(DisasContext *dc) |
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{
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LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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|
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gen_cond_branch(dc, TCG_COND_GE); |
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} |
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|
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static void dec_bgeu(DisasContext *dc) |
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{
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LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_GEU); |
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} |
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static void dec_bgu(DisasContext *dc) |
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{
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LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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|
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gen_cond_branch(dc, TCG_COND_GTU); |
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} |
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|
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static void dec_bne(DisasContext *dc) |
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{
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LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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|
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gen_cond_branch(dc, TCG_COND_NE); |
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} |
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|
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static void dec_call(DisasContext *dc) |
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{
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LOG_DIS("call r%d\n", dc->r0);
|
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|
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tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
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tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]); |
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dc->is_jmp = DISAS_JUMP; |
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} |
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|
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static void dec_calli(DisasContext *dc) |
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{
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LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4); |
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|
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tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
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gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26))); |
| 318 |
|
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dc->is_jmp = DISAS_TB_JUMP; |
| 320 |
} |
| 321 |
|
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static inline void gen_compare(DisasContext *dc, int cond) |
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{
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int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
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int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
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int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1; |
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int i;
|
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|
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if (dc->format == OP_FMT_RI) {
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switch (cond) {
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case TCG_COND_GEU:
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case TCG_COND_GTU:
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i = zero_extend(dc->imm16, 16);
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break;
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default:
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i = sign_extend(dc->imm16, 16);
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break;
|
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} |
| 339 |
|
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tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i); |
| 341 |
} else {
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tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]); |
| 343 |
} |
| 344 |
} |
| 345 |
|
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static void dec_cmpe(DisasContext *dc) |
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{
|
| 348 |
if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
|
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} else {
|
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LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
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} |
| 354 |
|
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gen_compare(dc, TCG_COND_EQ); |
| 356 |
} |
| 357 |
|
| 358 |
static void dec_cmpg(DisasContext *dc) |
| 359 |
{
|
| 360 |
if (dc->format == OP_FMT_RI) {
|
| 361 |
LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
|
| 363 |
} else {
|
| 364 |
LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 365 |
} |
| 366 |
|
| 367 |
gen_compare(dc, TCG_COND_GT); |
| 368 |
} |
| 369 |
|
| 370 |
static void dec_cmpge(DisasContext *dc) |
| 371 |
{
|
| 372 |
if (dc->format == OP_FMT_RI) {
|
| 373 |
LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 374 |
sign_extend(dc->imm16, 16));
|
| 375 |
} else {
|
| 376 |
LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 377 |
} |
| 378 |
|
| 379 |
gen_compare(dc, TCG_COND_GE); |
| 380 |
} |
| 381 |
|
| 382 |
static void dec_cmpgeu(DisasContext *dc) |
| 383 |
{
|
| 384 |
if (dc->format == OP_FMT_RI) {
|
| 385 |
LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 386 |
zero_extend(dc->imm16, 16));
|
| 387 |
} else {
|
| 388 |
LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 389 |
} |
| 390 |
|
| 391 |
gen_compare(dc, TCG_COND_GEU); |
| 392 |
} |
| 393 |
|
| 394 |
static void dec_cmpgu(DisasContext *dc) |
| 395 |
{
|
| 396 |
if (dc->format == OP_FMT_RI) {
|
| 397 |
LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 398 |
zero_extend(dc->imm16, 16));
|
| 399 |
} else {
|
| 400 |
LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 401 |
} |
| 402 |
|
| 403 |
gen_compare(dc, TCG_COND_GTU); |
| 404 |
} |
| 405 |
|
| 406 |
static void dec_cmpne(DisasContext *dc) |
| 407 |
{
|
| 408 |
if (dc->format == OP_FMT_RI) {
|
| 409 |
LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 410 |
sign_extend(dc->imm16, 16));
|
| 411 |
} else {
|
| 412 |
LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 413 |
} |
| 414 |
|
| 415 |
gen_compare(dc, TCG_COND_NE); |
| 416 |
} |
| 417 |
|
| 418 |
static void dec_divu(DisasContext *dc) |
| 419 |
{
|
| 420 |
int l1;
|
| 421 |
|
| 422 |
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 423 |
|
| 424 |
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
|
| 425 |
cpu_abort(dc->env, "hardware divider is not available\n");
|
| 426 |
} |
| 427 |
|
| 428 |
l1 = gen_new_label(); |
| 429 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
|
| 430 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
| 431 |
t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO); |
| 432 |
gen_set_label(l1); |
| 433 |
tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 434 |
} |
| 435 |
|
| 436 |
static void dec_lb(DisasContext *dc) |
| 437 |
{
|
| 438 |
TCGv t0; |
| 439 |
|
| 440 |
LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
| 441 |
|
| 442 |
t0 = tcg_temp_new(); |
| 443 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 444 |
tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX); |
| 445 |
tcg_temp_free(t0); |
| 446 |
} |
| 447 |
|
| 448 |
static void dec_lbu(DisasContext *dc) |
| 449 |
{
|
| 450 |
TCGv t0; |
| 451 |
|
| 452 |
LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
| 453 |
|
| 454 |
t0 = tcg_temp_new(); |
| 455 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 456 |
tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX); |
| 457 |
tcg_temp_free(t0); |
| 458 |
} |
| 459 |
|
| 460 |
static void dec_lh(DisasContext *dc) |
| 461 |
{
|
| 462 |
TCGv t0; |
| 463 |
|
| 464 |
LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
| 465 |
|
| 466 |
t0 = tcg_temp_new(); |
| 467 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 468 |
tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX); |
| 469 |
tcg_temp_free(t0); |
| 470 |
} |
| 471 |
|
| 472 |
static void dec_lhu(DisasContext *dc) |
| 473 |
{
|
| 474 |
TCGv t0; |
| 475 |
|
| 476 |
LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
| 477 |
|
| 478 |
t0 = tcg_temp_new(); |
| 479 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 480 |
tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX); |
| 481 |
tcg_temp_free(t0); |
| 482 |
} |
| 483 |
|
| 484 |
static void dec_lw(DisasContext *dc) |
| 485 |
{
|
| 486 |
TCGv t0; |
| 487 |
|
| 488 |
LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16)); |
| 489 |
|
| 490 |
t0 = tcg_temp_new(); |
| 491 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 492 |
tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX); |
| 493 |
tcg_temp_free(t0); |
| 494 |
} |
| 495 |
|
| 496 |
static void dec_modu(DisasContext *dc) |
| 497 |
{
|
| 498 |
int l1;
|
| 499 |
|
| 500 |
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
|
| 501 |
|
| 502 |
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
|
| 503 |
cpu_abort(dc->env, "hardware divider is not available\n");
|
| 504 |
} |
| 505 |
|
| 506 |
l1 = gen_new_label(); |
| 507 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
|
| 508 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
| 509 |
t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO); |
| 510 |
gen_set_label(l1); |
| 511 |
tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 512 |
} |
| 513 |
|
| 514 |
static void dec_mul(DisasContext *dc) |
| 515 |
{
|
| 516 |
if (dc->format == OP_FMT_RI) {
|
| 517 |
LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 518 |
sign_extend(dc->imm16, 16));
|
| 519 |
} else {
|
| 520 |
LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 521 |
} |
| 522 |
|
| 523 |
if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
|
| 524 |
cpu_abort(dc->env, "hardware multiplier is not available\n");
|
| 525 |
} |
| 526 |
|
| 527 |
if (dc->format == OP_FMT_RI) {
|
| 528 |
tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
| 529 |
sign_extend(dc->imm16, 16));
|
| 530 |
} else {
|
| 531 |
tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 532 |
} |
| 533 |
} |
| 534 |
|
| 535 |
static void dec_nor(DisasContext *dc) |
| 536 |
{
|
| 537 |
if (dc->format == OP_FMT_RI) {
|
| 538 |
LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 539 |
zero_extend(dc->imm16, 16));
|
| 540 |
} else {
|
| 541 |
LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 542 |
} |
| 543 |
|
| 544 |
if (dc->format == OP_FMT_RI) {
|
| 545 |
TCGv t0 = tcg_temp_new(); |
| 546 |
tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
|
| 547 |
tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0); |
| 548 |
tcg_temp_free(t0); |
| 549 |
} else {
|
| 550 |
tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 551 |
} |
| 552 |
} |
| 553 |
|
| 554 |
static void dec_or(DisasContext *dc) |
| 555 |
{
|
| 556 |
if (dc->format == OP_FMT_RI) {
|
| 557 |
LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
|
| 558 |
zero_extend(dc->imm16, 16));
|
| 559 |
} else {
|
| 560 |
if (dc->r1 == R_R0) {
|
| 561 |
LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
|
| 562 |
} else {
|
| 563 |
LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 564 |
} |
| 565 |
} |
| 566 |
|
| 567 |
if (dc->format == OP_FMT_RI) {
|
| 568 |
tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
| 569 |
zero_extend(dc->imm16, 16));
|
| 570 |
} else {
|
| 571 |
tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 572 |
} |
| 573 |
} |
| 574 |
|
| 575 |
static void dec_orhi(DisasContext *dc) |
| 576 |
{
|
| 577 |
if (dc->r0 == R_R0) {
|
| 578 |
LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
|
| 579 |
} else {
|
| 580 |
LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
|
| 581 |
} |
| 582 |
|
| 583 |
tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
|
| 584 |
} |
| 585 |
|
| 586 |
static void dec_scall(DisasContext *dc) |
| 587 |
{
|
| 588 |
if (dc->imm5 == 7) { |
| 589 |
LOG_DIS("scall\n");
|
| 590 |
} else if (dc->imm5 == 2) { |
| 591 |
LOG_DIS("break\n");
|
| 592 |
} else {
|
| 593 |
cpu_abort(dc->env, "invalid opcode\n");
|
| 594 |
} |
| 595 |
|
| 596 |
if (dc->imm5 == 7) { |
| 597 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
| 598 |
t_gen_raise_exception(dc, EXCP_SYSTEMCALL); |
| 599 |
} else {
|
| 600 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
| 601 |
t_gen_raise_exception(dc, EXCP_BREAKPOINT); |
| 602 |
} |
| 603 |
} |
| 604 |
|
| 605 |
static void dec_rcsr(DisasContext *dc) |
| 606 |
{
|
| 607 |
LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
|
| 608 |
|
| 609 |
switch (dc->csr) {
|
| 610 |
case CSR_IE:
|
| 611 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie); |
| 612 |
break;
|
| 613 |
case CSR_IM:
|
| 614 |
gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env); |
| 615 |
break;
|
| 616 |
case CSR_IP:
|
| 617 |
gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env); |
| 618 |
break;
|
| 619 |
case CSR_CC:
|
| 620 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc); |
| 621 |
break;
|
| 622 |
case CSR_CFG:
|
| 623 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg); |
| 624 |
break;
|
| 625 |
case CSR_EBA:
|
| 626 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba); |
| 627 |
break;
|
| 628 |
case CSR_DC:
|
| 629 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc); |
| 630 |
break;
|
| 631 |
case CSR_DEBA:
|
| 632 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba); |
| 633 |
break;
|
| 634 |
case CSR_JTX:
|
| 635 |
gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env); |
| 636 |
break;
|
| 637 |
case CSR_JRX:
|
| 638 |
gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env); |
| 639 |
break;
|
| 640 |
case CSR_ICC:
|
| 641 |
case CSR_DCC:
|
| 642 |
case CSR_BP0:
|
| 643 |
case CSR_BP1:
|
| 644 |
case CSR_BP2:
|
| 645 |
case CSR_BP3:
|
| 646 |
case CSR_WP0:
|
| 647 |
case CSR_WP1:
|
| 648 |
case CSR_WP2:
|
| 649 |
case CSR_WP3:
|
| 650 |
cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
|
| 651 |
break;
|
| 652 |
default:
|
| 653 |
cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
|
| 654 |
break;
|
| 655 |
} |
| 656 |
} |
| 657 |
|
| 658 |
static void dec_sb(DisasContext *dc) |
| 659 |
{
|
| 660 |
TCGv t0; |
| 661 |
|
| 662 |
LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
|
| 663 |
|
| 664 |
t0 = tcg_temp_new(); |
| 665 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 666 |
tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX); |
| 667 |
tcg_temp_free(t0); |
| 668 |
} |
| 669 |
|
| 670 |
static void dec_sextb(DisasContext *dc) |
| 671 |
{
|
| 672 |
LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
|
| 673 |
|
| 674 |
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
|
| 675 |
cpu_abort(dc->env, "hardware sign extender is not available\n");
|
| 676 |
} |
| 677 |
|
| 678 |
tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); |
| 679 |
} |
| 680 |
|
| 681 |
static void dec_sexth(DisasContext *dc) |
| 682 |
{
|
| 683 |
LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
|
| 684 |
|
| 685 |
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
|
| 686 |
cpu_abort(dc->env, "hardware sign extender is not available\n");
|
| 687 |
} |
| 688 |
|
| 689 |
tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); |
| 690 |
} |
| 691 |
|
| 692 |
static void dec_sh(DisasContext *dc) |
| 693 |
{
|
| 694 |
TCGv t0; |
| 695 |
|
| 696 |
LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
|
| 697 |
|
| 698 |
t0 = tcg_temp_new(); |
| 699 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 700 |
tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX); |
| 701 |
tcg_temp_free(t0); |
| 702 |
} |
| 703 |
|
| 704 |
static void dec_sl(DisasContext *dc) |
| 705 |
{
|
| 706 |
if (dc->format == OP_FMT_RI) {
|
| 707 |
LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
|
| 708 |
} else {
|
| 709 |
LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 710 |
} |
| 711 |
|
| 712 |
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
| 713 |
cpu_abort(dc->env, "hardware shifter is not available\n");
|
| 714 |
} |
| 715 |
|
| 716 |
if (dc->format == OP_FMT_RI) {
|
| 717 |
tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); |
| 718 |
} else {
|
| 719 |
TCGv t0 = tcg_temp_new(); |
| 720 |
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
| 721 |
tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); |
| 722 |
tcg_temp_free(t0); |
| 723 |
} |
| 724 |
} |
| 725 |
|
| 726 |
static void dec_sr(DisasContext *dc) |
| 727 |
{
|
| 728 |
if (dc->format == OP_FMT_RI) {
|
| 729 |
LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
|
| 730 |
} else {
|
| 731 |
LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 732 |
} |
| 733 |
|
| 734 |
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
| 735 |
if (dc->format == OP_FMT_RI) {
|
| 736 |
/* TODO: check r1 == 1 during runtime */
|
| 737 |
} else {
|
| 738 |
if (dc->imm5 != 1) { |
| 739 |
cpu_abort(dc->env, "hardware shifter is not available\n");
|
| 740 |
} |
| 741 |
} |
| 742 |
} |
| 743 |
|
| 744 |
if (dc->format == OP_FMT_RI) {
|
| 745 |
tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); |
| 746 |
} else {
|
| 747 |
TCGv t0 = tcg_temp_new(); |
| 748 |
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
| 749 |
tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); |
| 750 |
tcg_temp_free(t0); |
| 751 |
} |
| 752 |
} |
| 753 |
|
| 754 |
static void dec_sru(DisasContext *dc) |
| 755 |
{
|
| 756 |
if (dc->format == OP_FMT_RI) {
|
| 757 |
LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
|
| 758 |
} else {
|
| 759 |
LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 760 |
} |
| 761 |
|
| 762 |
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
| 763 |
if (dc->format == OP_FMT_RI) {
|
| 764 |
/* TODO: check r1 == 1 during runtime */
|
| 765 |
} else {
|
| 766 |
if (dc->imm5 != 1) { |
| 767 |
cpu_abort(dc->env, "hardware shifter is not available\n");
|
| 768 |
} |
| 769 |
} |
| 770 |
} |
| 771 |
|
| 772 |
if (dc->format == OP_FMT_RI) {
|
| 773 |
tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); |
| 774 |
} else {
|
| 775 |
TCGv t0 = tcg_temp_new(); |
| 776 |
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
| 777 |
tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); |
| 778 |
tcg_temp_free(t0); |
| 779 |
} |
| 780 |
} |
| 781 |
|
| 782 |
static void dec_sub(DisasContext *dc) |
| 783 |
{
|
| 784 |
LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 785 |
|
| 786 |
tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 787 |
} |
| 788 |
|
| 789 |
static void dec_sw(DisasContext *dc) |
| 790 |
{
|
| 791 |
TCGv t0; |
| 792 |
|
| 793 |
LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1); |
| 794 |
|
| 795 |
t0 = tcg_temp_new(); |
| 796 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
| 797 |
tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX); |
| 798 |
tcg_temp_free(t0); |
| 799 |
} |
| 800 |
|
| 801 |
static void dec_user(DisasContext *dc) |
| 802 |
{
|
| 803 |
LOG_DIS("user");
|
| 804 |
|
| 805 |
cpu_abort(dc->env, "user insn undefined\n");
|
| 806 |
} |
| 807 |
|
| 808 |
static void dec_wcsr(DisasContext *dc) |
| 809 |
{
|
| 810 |
int no;
|
| 811 |
|
| 812 |
LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
|
| 813 |
|
| 814 |
switch (dc->csr) {
|
| 815 |
case CSR_IE:
|
| 816 |
tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]); |
| 817 |
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
|
| 818 |
dc->is_jmp = DISAS_UPDATE; |
| 819 |
break;
|
| 820 |
case CSR_IM:
|
| 821 |
/* mark as an io operation because it could cause an interrupt */
|
| 822 |
if (use_icount) {
|
| 823 |
gen_io_start(); |
| 824 |
} |
| 825 |
gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]); |
| 826 |
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
|
| 827 |
if (use_icount) {
|
| 828 |
gen_io_end(); |
| 829 |
} |
| 830 |
dc->is_jmp = DISAS_UPDATE; |
| 831 |
break;
|
| 832 |
case CSR_IP:
|
| 833 |
/* mark as an io operation because it could cause an interrupt */
|
| 834 |
if (use_icount) {
|
| 835 |
gen_io_start(); |
| 836 |
} |
| 837 |
gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]); |
| 838 |
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
|
| 839 |
if (use_icount) {
|
| 840 |
gen_io_end(); |
| 841 |
} |
| 842 |
dc->is_jmp = DISAS_UPDATE; |
| 843 |
break;
|
| 844 |
case CSR_ICC:
|
| 845 |
/* TODO */
|
| 846 |
break;
|
| 847 |
case CSR_DCC:
|
| 848 |
/* TODO */
|
| 849 |
break;
|
| 850 |
case CSR_EBA:
|
| 851 |
tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]); |
| 852 |
break;
|
| 853 |
case CSR_DEBA:
|
| 854 |
tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]); |
| 855 |
break;
|
| 856 |
case CSR_JTX:
|
| 857 |
gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]); |
| 858 |
break;
|
| 859 |
case CSR_JRX:
|
| 860 |
gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]); |
| 861 |
break;
|
| 862 |
case CSR_DC:
|
| 863 |
tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]); |
| 864 |
break;
|
| 865 |
case CSR_BP0:
|
| 866 |
case CSR_BP1:
|
| 867 |
case CSR_BP2:
|
| 868 |
case CSR_BP3:
|
| 869 |
no = dc->csr - CSR_BP0; |
| 870 |
if (dc->env->num_bps <= no) {
|
| 871 |
cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
|
| 872 |
} |
| 873 |
tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]); |
| 874 |
break;
|
| 875 |
case CSR_WP0:
|
| 876 |
case CSR_WP1:
|
| 877 |
case CSR_WP2:
|
| 878 |
case CSR_WP3:
|
| 879 |
no = dc->csr - CSR_WP0; |
| 880 |
if (dc->env->num_wps <= no) {
|
| 881 |
cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
|
| 882 |
} |
| 883 |
tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]); |
| 884 |
break;
|
| 885 |
case CSR_CC:
|
| 886 |
case CSR_CFG:
|
| 887 |
cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
|
| 888 |
break;
|
| 889 |
default:
|
| 890 |
cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
|
| 891 |
break;
|
| 892 |
} |
| 893 |
} |
| 894 |
|
| 895 |
static void dec_xnor(DisasContext *dc) |
| 896 |
{
|
| 897 |
if (dc->format == OP_FMT_RI) {
|
| 898 |
LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 899 |
zero_extend(dc->imm16, 16));
|
| 900 |
} else {
|
| 901 |
if (dc->r1 == R_R0) {
|
| 902 |
LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
|
| 903 |
} else {
|
| 904 |
LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 905 |
} |
| 906 |
} |
| 907 |
|
| 908 |
if (dc->format == OP_FMT_RI) {
|
| 909 |
tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
| 910 |
zero_extend(dc->imm16, 16));
|
| 911 |
tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]); |
| 912 |
} else {
|
| 913 |
tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 914 |
} |
| 915 |
} |
| 916 |
|
| 917 |
static void dec_xor(DisasContext *dc) |
| 918 |
{
|
| 919 |
if (dc->format == OP_FMT_RI) {
|
| 920 |
LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
|
| 921 |
zero_extend(dc->imm16, 16));
|
| 922 |
} else {
|
| 923 |
LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
| 924 |
} |
| 925 |
|
| 926 |
if (dc->format == OP_FMT_RI) {
|
| 927 |
tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
| 928 |
zero_extend(dc->imm16, 16));
|
| 929 |
} else {
|
| 930 |
tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
| 931 |
} |
| 932 |
} |
| 933 |
|
| 934 |
static void dec_ill(DisasContext *dc) |
| 935 |
{
|
| 936 |
cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
|
| 937 |
} |
| 938 |
|
| 939 |
typedef void (*DecoderInfo)(DisasContext *dc); |
| 940 |
static const DecoderInfo decinfo[] = { |
| 941 |
dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh, |
| 942 |
dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl, |
| 943 |
dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne, |
| 944 |
dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi, |
| 945 |
dec_cmpne, |
| 946 |
dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill, |
| 947 |
dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl, |
| 948 |
dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth, |
| 949 |
dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli, |
| 950 |
dec_cmpne |
| 951 |
}; |
| 952 |
|
| 953 |
static inline void decode(DisasContext *dc, uint32_t ir) |
| 954 |
{
|
| 955 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
| 956 |
tcg_gen_debug_insn_start(dc->pc); |
| 957 |
} |
| 958 |
|
| 959 |
dc->ir = ir; |
| 960 |
LOG_DIS("%8.8x\t", dc->ir);
|
| 961 |
|
| 962 |
/* try guessing 'empty' instruction memory, although it may be a valid
|
| 963 |
* instruction sequence (eg. srui r0, r0, 0) */
|
| 964 |
if (dc->ir) {
|
| 965 |
dc->nr_nops = 0;
|
| 966 |
} else {
|
| 967 |
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
|
| 968 |
dc->nr_nops++; |
| 969 |
if (dc->nr_nops > 4) { |
| 970 |
cpu_abort(dc->env, "fetching nop sequence\n");
|
| 971 |
} |
| 972 |
} |
| 973 |
|
| 974 |
dc->opcode = EXTRACT_FIELD(ir, 26, 31); |
| 975 |
|
| 976 |
dc->imm5 = EXTRACT_FIELD(ir, 0, 4); |
| 977 |
dc->imm16 = EXTRACT_FIELD(ir, 0, 15); |
| 978 |
dc->imm26 = EXTRACT_FIELD(ir, 0, 25); |
| 979 |
|
| 980 |
dc->csr = EXTRACT_FIELD(ir, 21, 25); |
| 981 |
dc->r0 = EXTRACT_FIELD(ir, 21, 25); |
| 982 |
dc->r1 = EXTRACT_FIELD(ir, 16, 20); |
| 983 |
dc->r2 = EXTRACT_FIELD(ir, 11, 15); |
| 984 |
|
| 985 |
/* bit 31 seems to indicate insn type. */
|
| 986 |
if (ir & (1 << 31)) { |
| 987 |
dc->format = OP_FMT_RR; |
| 988 |
} else {
|
| 989 |
dc->format = OP_FMT_RI; |
| 990 |
} |
| 991 |
|
| 992 |
assert(ARRAY_SIZE(decinfo) == 64);
|
| 993 |
assert(dc->opcode < 64);
|
| 994 |
|
| 995 |
decinfo[dc->opcode](dc); |
| 996 |
} |
| 997 |
|
| 998 |
static void check_breakpoint(CPULM32State *env, DisasContext *dc) |
| 999 |
{
|
| 1000 |
CPUBreakpoint *bp; |
| 1001 |
|
| 1002 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
| 1003 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
| 1004 |
if (bp->pc == dc->pc) {
|
| 1005 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
| 1006 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
| 1007 |
dc->is_jmp = DISAS_UPDATE; |
| 1008 |
} |
| 1009 |
} |
| 1010 |
} |
| 1011 |
} |
| 1012 |
|
| 1013 |
/* generate intermediate code for basic block 'tb'. */
|
| 1014 |
static void gen_intermediate_code_internal(CPULM32State *env, |
| 1015 |
TranslationBlock *tb, int search_pc)
|
| 1016 |
{
|
| 1017 |
struct DisasContext ctx, *dc = &ctx;
|
| 1018 |
uint16_t *gen_opc_end; |
| 1019 |
uint32_t pc_start; |
| 1020 |
int j, lj;
|
| 1021 |
uint32_t next_page_start; |
| 1022 |
int num_insns;
|
| 1023 |
int max_insns;
|
| 1024 |
|
| 1025 |
pc_start = tb->pc; |
| 1026 |
dc->env = env; |
| 1027 |
dc->tb = tb; |
| 1028 |
|
| 1029 |
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
| 1030 |
|
| 1031 |
dc->is_jmp = DISAS_NEXT; |
| 1032 |
dc->pc = pc_start; |
| 1033 |
dc->singlestep_enabled = env->singlestep_enabled; |
| 1034 |
dc->nr_nops = 0;
|
| 1035 |
|
| 1036 |
if (pc_start & 3) { |
| 1037 |
cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
|
| 1038 |
} |
| 1039 |
|
| 1040 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
| 1041 |
lj = -1;
|
| 1042 |
num_insns = 0;
|
| 1043 |
max_insns = tb->cflags & CF_COUNT_MASK; |
| 1044 |
if (max_insns == 0) { |
| 1045 |
max_insns = CF_COUNT_MASK; |
| 1046 |
} |
| 1047 |
|
| 1048 |
gen_tb_start(); |
| 1049 |
do {
|
| 1050 |
check_breakpoint(env, dc); |
| 1051 |
|
| 1052 |
if (search_pc) {
|
| 1053 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
| 1054 |
if (lj < j) {
|
| 1055 |
lj++; |
| 1056 |
while (lj < j) {
|
| 1057 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
| 1058 |
} |
| 1059 |
} |
| 1060 |
tcg_ctx.gen_opc_pc[lj] = dc->pc; |
| 1061 |
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
| 1062 |
tcg_ctx.gen_opc_icount[lj] = num_insns; |
| 1063 |
} |
| 1064 |
|
| 1065 |
/* Pretty disas. */
|
| 1066 |
LOG_DIS("%8.8x:\t", dc->pc);
|
| 1067 |
|
| 1068 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { |
| 1069 |
gen_io_start(); |
| 1070 |
} |
| 1071 |
|
| 1072 |
decode(dc, cpu_ldl_code(env, dc->pc)); |
| 1073 |
dc->pc += 4;
|
| 1074 |
num_insns++; |
| 1075 |
|
| 1076 |
} while (!dc->is_jmp
|
| 1077 |
&& tcg_ctx.gen_opc_ptr < gen_opc_end |
| 1078 |
&& !env->singlestep_enabled |
| 1079 |
&& !singlestep |
| 1080 |
&& (dc->pc < next_page_start) |
| 1081 |
&& num_insns < max_insns); |
| 1082 |
|
| 1083 |
if (tb->cflags & CF_LAST_IO) {
|
| 1084 |
gen_io_end(); |
| 1085 |
} |
| 1086 |
|
| 1087 |
if (unlikely(env->singlestep_enabled)) {
|
| 1088 |
if (dc->is_jmp == DISAS_NEXT) {
|
| 1089 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
| 1090 |
} |
| 1091 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
| 1092 |
} else {
|
| 1093 |
switch (dc->is_jmp) {
|
| 1094 |
case DISAS_NEXT:
|
| 1095 |
gen_goto_tb(dc, 1, dc->pc);
|
| 1096 |
break;
|
| 1097 |
default:
|
| 1098 |
case DISAS_JUMP:
|
| 1099 |
case DISAS_UPDATE:
|
| 1100 |
/* indicate that the hash table must be used
|
| 1101 |
to find the next TB */
|
| 1102 |
tcg_gen_exit_tb(0);
|
| 1103 |
break;
|
| 1104 |
case DISAS_TB_JUMP:
|
| 1105 |
/* nothing more to generate */
|
| 1106 |
break;
|
| 1107 |
} |
| 1108 |
} |
| 1109 |
|
| 1110 |
gen_tb_end(tb, num_insns); |
| 1111 |
*tcg_ctx.gen_opc_ptr = INDEX_op_end; |
| 1112 |
if (search_pc) {
|
| 1113 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
| 1114 |
lj++; |
| 1115 |
while (lj <= j) {
|
| 1116 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
| 1117 |
} |
| 1118 |
} else {
|
| 1119 |
tb->size = dc->pc - pc_start; |
| 1120 |
tb->icount = num_insns; |
| 1121 |
} |
| 1122 |
|
| 1123 |
#ifdef DEBUG_DISAS
|
| 1124 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
| 1125 |
qemu_log("\n");
|
| 1126 |
log_target_disas(env, pc_start, dc->pc - pc_start, 0);
|
| 1127 |
qemu_log("\nisize=%d osize=%td\n",
|
| 1128 |
dc->pc - pc_start, tcg_ctx.gen_opc_ptr - |
| 1129 |
tcg_ctx.gen_opc_buf); |
| 1130 |
} |
| 1131 |
#endif
|
| 1132 |
} |
| 1133 |
|
| 1134 |
void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) |
| 1135 |
{
|
| 1136 |
gen_intermediate_code_internal(env, tb, 0);
|
| 1137 |
} |
| 1138 |
|
| 1139 |
void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb) |
| 1140 |
{
|
| 1141 |
gen_intermediate_code_internal(env, tb, 1);
|
| 1142 |
} |
| 1143 |
|
| 1144 |
void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf,
|
| 1145 |
int flags)
|
| 1146 |
{
|
| 1147 |
int i;
|
| 1148 |
|
| 1149 |
if (!env || !f) {
|
| 1150 |
return;
|
| 1151 |
} |
| 1152 |
|
| 1153 |
cpu_fprintf(f, "IN: PC=%x %s\n",
|
| 1154 |
env->pc, lookup_symbol(env->pc)); |
| 1155 |
|
| 1156 |
cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
|
| 1157 |
env->ie, |
| 1158 |
(env->ie & IE_IE) ? 1 : 0, |
| 1159 |
(env->ie & IE_EIE) ? 1 : 0, |
| 1160 |
(env->ie & IE_BIE) ? 1 : 0, |
| 1161 |
lm32_pic_get_im(env->pic_state), |
| 1162 |
lm32_pic_get_ip(env->pic_state)); |
| 1163 |
cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
|
| 1164 |
env->eba, |
| 1165 |
env->deba); |
| 1166 |
|
| 1167 |
for (i = 0; i < 32; i++) { |
| 1168 |
cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
|
| 1169 |
if ((i + 1) % 4 == 0) { |
| 1170 |
cpu_fprintf(f, "\n");
|
| 1171 |
} |
| 1172 |
} |
| 1173 |
cpu_fprintf(f, "\n\n");
|
| 1174 |
} |
| 1175 |
|
| 1176 |
void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos) |
| 1177 |
{
|
| 1178 |
env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
| 1179 |
} |
| 1180 |
|
| 1181 |
void lm32_translate_init(void) |
| 1182 |
{
|
| 1183 |
int i;
|
| 1184 |
|
| 1185 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
| 1186 |
|
| 1187 |
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { |
| 1188 |
cpu_R[i] = tcg_global_mem_new(TCG_AREG0, |
| 1189 |
offsetof(CPULM32State, regs[i]), |
| 1190 |
regnames[i]); |
| 1191 |
} |
| 1192 |
|
| 1193 |
for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) { |
| 1194 |
cpu_bp[i] = tcg_global_mem_new(TCG_AREG0, |
| 1195 |
offsetof(CPULM32State, bp[i]), |
| 1196 |
regnames[32+i]);
|
| 1197 |
} |
| 1198 |
|
| 1199 |
for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) { |
| 1200 |
cpu_wp[i] = tcg_global_mem_new(TCG_AREG0, |
| 1201 |
offsetof(CPULM32State, wp[i]), |
| 1202 |
regnames[36+i]);
|
| 1203 |
} |
| 1204 |
|
| 1205 |
cpu_pc = tcg_global_mem_new(TCG_AREG0, |
| 1206 |
offsetof(CPULM32State, pc), |
| 1207 |
"pc");
|
| 1208 |
cpu_ie = tcg_global_mem_new(TCG_AREG0, |
| 1209 |
offsetof(CPULM32State, ie), |
| 1210 |
"ie");
|
| 1211 |
cpu_icc = tcg_global_mem_new(TCG_AREG0, |
| 1212 |
offsetof(CPULM32State, icc), |
| 1213 |
"icc");
|
| 1214 |
cpu_dcc = tcg_global_mem_new(TCG_AREG0, |
| 1215 |
offsetof(CPULM32State, dcc), |
| 1216 |
"dcc");
|
| 1217 |
cpu_cc = tcg_global_mem_new(TCG_AREG0, |
| 1218 |
offsetof(CPULM32State, cc), |
| 1219 |
"cc");
|
| 1220 |
cpu_cfg = tcg_global_mem_new(TCG_AREG0, |
| 1221 |
offsetof(CPULM32State, cfg), |
| 1222 |
"cfg");
|
| 1223 |
cpu_eba = tcg_global_mem_new(TCG_AREG0, |
| 1224 |
offsetof(CPULM32State, eba), |
| 1225 |
"eba");
|
| 1226 |
cpu_dc = tcg_global_mem_new(TCG_AREG0, |
| 1227 |
offsetof(CPULM32State, dc), |
| 1228 |
"dc");
|
| 1229 |
cpu_deba = tcg_global_mem_new(TCG_AREG0, |
| 1230 |
offsetof(CPULM32State, deba), |
| 1231 |
"deba");
|
| 1232 |
} |
| 1233 |
|