root / target-cris / translate_v10.c @ 0d84be5b
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1 | 40e9eddd | Edgar E. Iglesias | /*
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2 | 40e9eddd | Edgar E. Iglesias | * CRISv10 emulation for qemu: main translation routines.
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3 | 40e9eddd | Edgar E. Iglesias | *
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4 | 40e9eddd | Edgar E. Iglesias | * Copyright (c) 2010 AXIS Communications AB
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5 | 40e9eddd | Edgar E. Iglesias | * Written by Edgar E. Iglesias.
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6 | 40e9eddd | Edgar E. Iglesias | *
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7 | 40e9eddd | Edgar E. Iglesias | * This library is free software; you can redistribute it and/or
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8 | 40e9eddd | Edgar E. Iglesias | * modify it under the terms of the GNU Lesser General Public
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9 | 40e9eddd | Edgar E. Iglesias | * License as published by the Free Software Foundation; either
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10 | 40e9eddd | Edgar E. Iglesias | * version 2 of the License, or (at your option) any later version.
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11 | 40e9eddd | Edgar E. Iglesias | *
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12 | 40e9eddd | Edgar E. Iglesias | * This library is distributed in the hope that it will be useful,
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13 | 40e9eddd | Edgar E. Iglesias | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 40e9eddd | Edgar E. Iglesias | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 40e9eddd | Edgar E. Iglesias | * Lesser General Public License for more details.
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16 | 40e9eddd | Edgar E. Iglesias | *
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17 | 40e9eddd | Edgar E. Iglesias | * You should have received a copy of the GNU Lesser General Public
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18 | 70539e18 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 40e9eddd | Edgar E. Iglesias | */
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20 | 40e9eddd | Edgar E. Iglesias | |
21 | 40e9eddd | Edgar E. Iglesias | #include "crisv10-decode.h" |
22 | 40e9eddd | Edgar E. Iglesias | |
23 | 40e9eddd | Edgar E. Iglesias | static const char *regnames_v10[] = |
24 | 40e9eddd | Edgar E. Iglesias | { |
25 | bf76bafa | Edgar E. Iglesias | "$r0", "$r1", "$r2", "$r3", |
26 | bf76bafa | Edgar E. Iglesias | "$r4", "$r5", "$r6", "$r7", |
27 | bf76bafa | Edgar E. Iglesias | "$r8", "$r9", "$r10", "$r11", |
28 | bf76bafa | Edgar E. Iglesias | "$r12", "$r13", "$sp", "$pc", |
29 | 40e9eddd | Edgar E. Iglesias | }; |
30 | 40e9eddd | Edgar E. Iglesias | |
31 | 40e9eddd | Edgar E. Iglesias | static const char *pregnames_v10[] = |
32 | 40e9eddd | Edgar E. Iglesias | { |
33 | bf76bafa | Edgar E. Iglesias | "$bz", "$vr", "$p2", "$p3", |
34 | bf76bafa | Edgar E. Iglesias | "$wz", "$ccr", "$p6-prefix", "$mof", |
35 | bf76bafa | Edgar E. Iglesias | "$dz", "$ibr", "$irp", "$srp", |
36 | bf76bafa | Edgar E. Iglesias | "$bar", "$dccr", "$brp", "$usp", |
37 | 40e9eddd | Edgar E. Iglesias | }; |
38 | 40e9eddd | Edgar E. Iglesias | |
39 | 40e9eddd | Edgar E. Iglesias | /* We need this table to handle preg-moves with implicit width. */
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40 | 40e9eddd | Edgar E. Iglesias | static int preg_sizes_v10[] = { |
41 | bf76bafa | Edgar E. Iglesias | 1, /* bz. */ |
42 | bf76bafa | Edgar E. Iglesias | 1, /* vr. */ |
43 | bf76bafa | Edgar E. Iglesias | 1, /* pid. */ |
44 | bf76bafa | Edgar E. Iglesias | 1, /* srs. */ |
45 | bf76bafa | Edgar E. Iglesias | 2, /* wz. */ |
46 | bf76bafa | Edgar E. Iglesias | 2, 2, 4, |
47 | bf76bafa | Edgar E. Iglesias | 4, 4, 4, 4, |
48 | bf76bafa | Edgar E. Iglesias | 4, 4, 4, 4, |
49 | 40e9eddd | Edgar E. Iglesias | }; |
50 | 40e9eddd | Edgar E. Iglesias | |
51 | 40e9eddd | Edgar E. Iglesias | static inline int dec10_size(unsigned int size) |
52 | 40e9eddd | Edgar E. Iglesias | { |
53 | 40e9eddd | Edgar E. Iglesias | size++; |
54 | 40e9eddd | Edgar E. Iglesias | if (size == 3) |
55 | 40e9eddd | Edgar E. Iglesias | size++; |
56 | 40e9eddd | Edgar E. Iglesias | return size;
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57 | 40e9eddd | Edgar E. Iglesias | } |
58 | 40e9eddd | Edgar E. Iglesias | |
59 | 40e9eddd | Edgar E. Iglesias | static inline void cris_illegal_insn(DisasContext *dc) |
60 | 40e9eddd | Edgar E. Iglesias | { |
61 | 40e9eddd | Edgar E. Iglesias | qemu_log("illegal insn at pc=%x\n", dc->pc);
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62 | 40e9eddd | Edgar E. Iglesias | t_gen_raise_exception(EXCP_BREAK); |
63 | 40e9eddd | Edgar E. Iglesias | } |
64 | 40e9eddd | Edgar E. Iglesias | |
65 | 40e9eddd | Edgar E. Iglesias | /* Prefix flag and register are used to handle the more complex
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66 | 40e9eddd | Edgar E. Iglesias | addressing modes. */
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67 | 40e9eddd | Edgar E. Iglesias | static void cris_set_prefix(DisasContext *dc) |
68 | 40e9eddd | Edgar E. Iglesias | { |
69 | 40e9eddd | Edgar E. Iglesias | dc->clear_prefix = 0;
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70 | 40e9eddd | Edgar E. Iglesias | dc->tb_flags |= PFIX_FLAG; |
71 | 40e9eddd | Edgar E. Iglesias | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG); |
72 | 40e9eddd | Edgar E. Iglesias | |
73 | 40e9eddd | Edgar E. Iglesias | /* prefix insns dont clear the x flag. */
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74 | 40e9eddd | Edgar E. Iglesias | dc->clear_x = 0;
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75 | 40e9eddd | Edgar E. Iglesias | cris_lock_irq(dc); |
76 | 40e9eddd | Edgar E. Iglesias | } |
77 | 40e9eddd | Edgar E. Iglesias | |
78 | 40e9eddd | Edgar E. Iglesias | static void crisv10_prepare_memaddr(DisasContext *dc, |
79 | 40e9eddd | Edgar E. Iglesias | TCGv addr, unsigned int size) |
80 | 40e9eddd | Edgar E. Iglesias | { |
81 | 40e9eddd | Edgar E. Iglesias | if (dc->tb_flags & PFIX_FLAG) {
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82 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]); |
83 | 40e9eddd | Edgar E. Iglesias | } else {
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84 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(addr, cpu_R[dc->src]); |
85 | 40e9eddd | Edgar E. Iglesias | } |
86 | 40e9eddd | Edgar E. Iglesias | } |
87 | 40e9eddd | Edgar E. Iglesias | |
88 | 40e9eddd | Edgar E. Iglesias | static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size) |
89 | 40e9eddd | Edgar E. Iglesias | { |
90 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 0; |
91 | 40e9eddd | Edgar E. Iglesias | |
92 | 40e9eddd | Edgar E. Iglesias | if (dc->tb_flags & PFIX_FLAG) {
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93 | 40e9eddd | Edgar E. Iglesias | if (dc->mode == CRISV10_MODE_AUTOINC) {
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94 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]); |
95 | 40e9eddd | Edgar E. Iglesias | } |
96 | 40e9eddd | Edgar E. Iglesias | } else {
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97 | 40e9eddd | Edgar E. Iglesias | if (dc->mode == CRISV10_MODE_AUTOINC) {
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98 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15) { |
99 | 40e9eddd | Edgar E. Iglesias | insn_len += size & ~1;
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100 | 40e9eddd | Edgar E. Iglesias | } else {
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101 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size); |
102 | 40e9eddd | Edgar E. Iglesias | } |
103 | 40e9eddd | Edgar E. Iglesias | } |
104 | 40e9eddd | Edgar E. Iglesias | } |
105 | 40e9eddd | Edgar E. Iglesias | return insn_len;
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106 | 40e9eddd | Edgar E. Iglesias | } |
107 | 40e9eddd | Edgar E. Iglesias | |
108 | 40e9eddd | Edgar E. Iglesias | static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize, |
109 | 40e9eddd | Edgar E. Iglesias | TCGv dst) |
110 | 40e9eddd | Edgar E. Iglesias | { |
111 | bf76bafa | Edgar E. Iglesias | unsigned int rs, rd; |
112 | bf76bafa | Edgar E. Iglesias | uint32_t imm; |
113 | bf76bafa | Edgar E. Iglesias | int is_imm;
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114 | bf76bafa | Edgar E. Iglesias | int insn_len = 0; |
115 | bf76bafa | Edgar E. Iglesias | |
116 | bf76bafa | Edgar E. Iglesias | rs = dc->src; |
117 | bf76bafa | Edgar E. Iglesias | rd = dc->dst; |
118 | bf76bafa | Edgar E. Iglesias | is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
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119 | bf76bafa | Edgar E. Iglesias | LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
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120 | bf76bafa | Edgar E. Iglesias | rs, rd, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG); |
121 | bf76bafa | Edgar E. Iglesias | |
122 | bf76bafa | Edgar E. Iglesias | /* Load [$rs] onto T1. */
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123 | bf76bafa | Edgar E. Iglesias | if (is_imm) {
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124 | bf76bafa | Edgar E. Iglesias | if (memsize != 4) { |
125 | bf76bafa | Edgar E. Iglesias | if (s_ext) {
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126 | bf76bafa | Edgar E. Iglesias | if (memsize == 1) |
127 | bf76bafa | Edgar E. Iglesias | imm = ldsb_code(dc->pc + 2);
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128 | 40e9eddd | Edgar E. Iglesias | else
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129 | bf76bafa | Edgar E. Iglesias | imm = ldsw_code(dc->pc + 2);
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130 | bf76bafa | Edgar E. Iglesias | } else {
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131 | bf76bafa | Edgar E. Iglesias | if (memsize == 1) |
132 | bf76bafa | Edgar E. Iglesias | imm = ldub_code(dc->pc + 2);
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133 | bf76bafa | Edgar E. Iglesias | else
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134 | bf76bafa | Edgar E. Iglesias | imm = lduw_code(dc->pc + 2);
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135 | bf76bafa | Edgar E. Iglesias | } |
136 | bf76bafa | Edgar E. Iglesias | } else
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137 | bf76bafa | Edgar E. Iglesias | imm = ldl_code(dc->pc + 2);
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138 | bf76bafa | Edgar E. Iglesias | |
139 | bf76bafa | Edgar E. Iglesias | tcg_gen_movi_tl(dst, imm); |
140 | 40e9eddd | Edgar E. Iglesias | |
141 | bf76bafa | Edgar E. Iglesias | if (dc->mode == CRISV10_MODE_AUTOINC) {
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142 | bf76bafa | Edgar E. Iglesias | insn_len += memsize; |
143 | bf76bafa | Edgar E. Iglesias | if (memsize == 1) |
144 | bf76bafa | Edgar E. Iglesias | insn_len++; |
145 | bf76bafa | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len); |
146 | 40e9eddd | Edgar E. Iglesias | } |
147 | bf76bafa | Edgar E. Iglesias | } else {
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148 | bf76bafa | Edgar E. Iglesias | TCGv addr; |
149 | bf76bafa | Edgar E. Iglesias | |
150 | bf76bafa | Edgar E. Iglesias | addr = tcg_temp_new(); |
151 | bf76bafa | Edgar E. Iglesias | cris_flush_cc_state(dc); |
152 | bf76bafa | Edgar E. Iglesias | crisv10_prepare_memaddr(dc, addr, memsize); |
153 | bf76bafa | Edgar E. Iglesias | gen_load(dc, dst, addr, memsize, 0);
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154 | bf76bafa | Edgar E. Iglesias | if (s_ext)
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155 | bf76bafa | Edgar E. Iglesias | t_gen_sext(dst, dst, memsize); |
156 | bf76bafa | Edgar E. Iglesias | else
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157 | bf76bafa | Edgar E. Iglesias | t_gen_zext(dst, dst, memsize); |
158 | bf76bafa | Edgar E. Iglesias | insn_len += crisv10_post_memaddr(dc, memsize); |
159 | bf76bafa | Edgar E. Iglesias | tcg_temp_free(addr); |
160 | bf76bafa | Edgar E. Iglesias | } |
161 | bf76bafa | Edgar E. Iglesias | |
162 | bf76bafa | Edgar E. Iglesias | if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
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163 | bf76bafa | Edgar E. Iglesias | dc->dst = dc->src; |
164 | bf76bafa | Edgar E. Iglesias | } |
165 | bf76bafa | Edgar E. Iglesias | return insn_len;
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166 | 40e9eddd | Edgar E. Iglesias | } |
167 | 40e9eddd | Edgar E. Iglesias | |
168 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_quick_imm(DisasContext *dc) |
169 | 40e9eddd | Edgar E. Iglesias | { |
170 | 40e9eddd | Edgar E. Iglesias | int32_t imm, simm; |
171 | 40e9eddd | Edgar E. Iglesias | int op;
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172 | 40e9eddd | Edgar E. Iglesias | |
173 | 40e9eddd | Edgar E. Iglesias | /* sign extend. */
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174 | 40e9eddd | Edgar E. Iglesias | imm = dc->ir & ((1 << 6) - 1); |
175 | 40e9eddd | Edgar E. Iglesias | simm = (int8_t) (imm << 2);
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176 | 40e9eddd | Edgar E. Iglesias | simm >>= 2;
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177 | 40e9eddd | Edgar E. Iglesias | switch (dc->opcode) {
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178 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BDAP_R0:
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179 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BDAP_R1:
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180 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BDAP_R2:
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181 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BDAP_R3:
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182 | 40e9eddd | Edgar E. Iglesias | simm = (int8_t)dc->ir; |
183 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
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184 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
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185 | 40e9eddd | Edgar E. Iglesias | dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); |
186 | 40e9eddd | Edgar E. Iglesias | cris_set_prefix(dc); |
187 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 15) { |
188 | 40e9eddd | Edgar E. Iglesias | tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
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189 | 40e9eddd | Edgar E. Iglesias | } else {
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190 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); |
191 | 40e9eddd | Edgar E. Iglesias | } |
192 | 40e9eddd | Edgar E. Iglesias | break;
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193 | 40e9eddd | Edgar E. Iglesias | |
194 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_MOVEQ:
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195 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
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196 | 40e9eddd | Edgar E. Iglesias | |
197 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
198 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], |
199 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(simm), 4);
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200 | 40e9eddd | Edgar E. Iglesias | break;
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201 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_CMPQ:
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202 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
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203 | 40e9eddd | Edgar E. Iglesias | |
204 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
205 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], |
206 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(simm), 4);
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207 | 40e9eddd | Edgar E. Iglesias | break;
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208 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_ADDQ:
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209 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
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210 | 40e9eddd | Edgar E. Iglesias | |
211 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
212 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], |
213 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(imm), 4);
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214 | 40e9eddd | Edgar E. Iglesias | break;
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215 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_ANDQ:
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216 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
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217 | 40e9eddd | Edgar E. Iglesias | |
218 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
219 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], |
220 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(simm), 4);
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221 | 40e9eddd | Edgar E. Iglesias | break;
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222 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_ASHQ:
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223 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
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224 | 40e9eddd | Edgar E. Iglesias | |
225 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
226 | 40e9eddd | Edgar E. Iglesias | op = imm & (1 << 5); |
227 | 40e9eddd | Edgar E. Iglesias | imm &= 0x1f;
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228 | 40e9eddd | Edgar E. Iglesias | if (op) {
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229 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst], |
230 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(imm), 4);
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231 | 40e9eddd | Edgar E. Iglesias | } else {
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232 | 40e9eddd | Edgar E. Iglesias | /* BTST */
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233 | 40e9eddd | Edgar E. Iglesias | cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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234 | 40e9eddd | Edgar E. Iglesias | gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst], |
235 | 40e9eddd | Edgar E. Iglesias | tcg_const_tl(imm), cpu_PR[PR_CCS]); |
236 | 40e9eddd | Edgar E. Iglesias | } |
237 | 40e9eddd | Edgar E. Iglesias | break;
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238 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_LSHQ:
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239 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
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240 | 40e9eddd | Edgar E. Iglesias | |
241 | 40e9eddd | Edgar E. Iglesias | op = CC_OP_LSL; |
242 | 40e9eddd | Edgar E. Iglesias | if (imm & (1 << 5)) { |
243 | 40e9eddd | Edgar E. Iglesias | op = CC_OP_LSR; |
244 | 40e9eddd | Edgar E. Iglesias | } |
245 | 40e9eddd | Edgar E. Iglesias | imm &= 0x1f;
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246 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
247 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, op, cpu_R[dc->dst], |
248 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(imm), 4);
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249 | 40e9eddd | Edgar E. Iglesias | break;
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250 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_SUBQ:
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251 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
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252 | 40e9eddd | Edgar E. Iglesias | |
253 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
254 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], |
255 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(imm), 4);
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256 | 40e9eddd | Edgar E. Iglesias | break;
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257 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_ORQ:
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258 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
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259 | 40e9eddd | Edgar E. Iglesias | |
260 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
261 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], |
262 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], tcg_const_tl(simm), 4);
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263 | 40e9eddd | Edgar E. Iglesias | break;
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264 | 40e9eddd | Edgar E. Iglesias | |
265 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BCC_R0:
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266 | 40e9eddd | Edgar E. Iglesias | if (!dc->ir) {
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267 | 40e9eddd | Edgar E. Iglesias | cpu_abort(dc->env, "opcode zero\n");
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268 | 40e9eddd | Edgar E. Iglesias | } |
269 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BCC_R1:
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270 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BCC_R2:
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271 | 40e9eddd | Edgar E. Iglesias | case CRISV10_QIMM_BCC_R3:
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272 | 40e9eddd | Edgar E. Iglesias | imm = dc->ir & 0xff;
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273 | 40e9eddd | Edgar E. Iglesias | /* bit 0 is a sign bit. */
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274 | 40e9eddd | Edgar E. Iglesias | if (imm & 1) { |
275 | 40e9eddd | Edgar E. Iglesias | imm |= 0xffffff00; /* sign extend. */ |
276 | 40e9eddd | Edgar E. Iglesias | imm &= ~1; /* get rid of the sign bit. */ |
277 | 40e9eddd | Edgar E. Iglesias | } |
278 | 40e9eddd | Edgar E. Iglesias | imm += 2;
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279 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
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280 | 40e9eddd | Edgar E. Iglesias | |
281 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, 0);
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282 | 40e9eddd | Edgar E. Iglesias | cris_prepare_cc_branch(dc, imm, dc->cond); |
283 | 40e9eddd | Edgar E. Iglesias | break;
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284 | 40e9eddd | Edgar E. Iglesias | |
285 | 40e9eddd | Edgar E. Iglesias | default:
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286 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
|
287 | 40e9eddd | Edgar E. Iglesias | dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); |
288 | 43dc2a64 | Blue Swirl | cpu_abort(dc->env, "Unhandled quickimm\n");
|
289 | 40e9eddd | Edgar E. Iglesias | break;
|
290 | 40e9eddd | Edgar E. Iglesias | } |
291 | 40e9eddd | Edgar E. Iglesias | return 2; |
292 | 40e9eddd | Edgar E. Iglesias | } |
293 | 40e9eddd | Edgar E. Iglesias | |
294 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_setclrf(DisasContext *dc) |
295 | 40e9eddd | Edgar E. Iglesias | { |
296 | 40e9eddd | Edgar E. Iglesias | uint32_t flags; |
297 | 40e9eddd | Edgar E. Iglesias | unsigned int set = ~dc->opcode & 1; |
298 | 40e9eddd | Edgar E. Iglesias | |
299 | 40e9eddd | Edgar E. Iglesias | flags = EXTRACT_FIELD(dc->ir, 0, 3) |
300 | 40e9eddd | Edgar E. Iglesias | | (EXTRACT_FIELD(dc->ir, 12, 15) << 4); |
301 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
|
302 | 40e9eddd | Edgar E. Iglesias | |
303 | 40e9eddd | Edgar E. Iglesias | |
304 | 40e9eddd | Edgar E. Iglesias | if (flags & X_FLAG) {
|
305 | 40e9eddd | Edgar E. Iglesias | dc->flagx_known = 1;
|
306 | 40e9eddd | Edgar E. Iglesias | if (set)
|
307 | 40e9eddd | Edgar E. Iglesias | dc->flags_x = X_FLAG; |
308 | 40e9eddd | Edgar E. Iglesias | else
|
309 | 40e9eddd | Edgar E. Iglesias | dc->flags_x = 0;
|
310 | 40e9eddd | Edgar E. Iglesias | } |
311 | 40e9eddd | Edgar E. Iglesias | |
312 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags (dc); |
313 | 40e9eddd | Edgar E. Iglesias | cris_update_cc_op(dc, CC_OP_FLAGS, 4);
|
314 | 40e9eddd | Edgar E. Iglesias | cris_update_cc_x(dc); |
315 | 40e9eddd | Edgar E. Iglesias | tcg_gen_movi_tl(cc_op, dc->cc_op); |
316 | 40e9eddd | Edgar E. Iglesias | |
317 | 40e9eddd | Edgar E. Iglesias | if (set) {
|
318 | 40e9eddd | Edgar E. Iglesias | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); |
319 | 40e9eddd | Edgar E. Iglesias | } else {
|
320 | 40e9eddd | Edgar E. Iglesias | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); |
321 | 40e9eddd | Edgar E. Iglesias | } |
322 | 40e9eddd | Edgar E. Iglesias | |
323 | 40e9eddd | Edgar E. Iglesias | dc->flags_uptodate = 1;
|
324 | 40e9eddd | Edgar E. Iglesias | dc->clear_x = 0;
|
325 | 40e9eddd | Edgar E. Iglesias | cris_lock_irq(dc); |
326 | 40e9eddd | Edgar E. Iglesias | return 2; |
327 | 40e9eddd | Edgar E. Iglesias | } |
328 | 40e9eddd | Edgar E. Iglesias | |
329 | 40e9eddd | Edgar E. Iglesias | static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext, |
330 | 40e9eddd | Edgar E. Iglesias | TCGv dd, TCGv ds, TCGv sd, TCGv ss) |
331 | 40e9eddd | Edgar E. Iglesias | { |
332 | 40e9eddd | Edgar E. Iglesias | if (sext) {
|
333 | 40e9eddd | Edgar E. Iglesias | t_gen_sext(dd, sd, size); |
334 | 40e9eddd | Edgar E. Iglesias | t_gen_sext(ds, ss, size); |
335 | 40e9eddd | Edgar E. Iglesias | } else {
|
336 | 40e9eddd | Edgar E. Iglesias | t_gen_zext(dd, sd, size); |
337 | 40e9eddd | Edgar E. Iglesias | t_gen_zext(ds, ss, size); |
338 | 40e9eddd | Edgar E. Iglesias | } |
339 | 40e9eddd | Edgar E. Iglesias | } |
340 | 40e9eddd | Edgar E. Iglesias | |
341 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext) |
342 | 40e9eddd | Edgar E. Iglesias | { |
343 | 40e9eddd | Edgar E. Iglesias | TCGv t[2];
|
344 | 40e9eddd | Edgar E. Iglesias | |
345 | 40e9eddd | Edgar E. Iglesias | t[0] = tcg_temp_new();
|
346 | 40e9eddd | Edgar E. Iglesias | t[1] = tcg_temp_new();
|
347 | 40e9eddd | Edgar E. Iglesias | dec10_reg_prep_sext(dc, size, sext, |
348 | 40e9eddd | Edgar E. Iglesias | t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); |
349 | 40e9eddd | Edgar E. Iglesias | |
350 | 40e9eddd | Edgar E. Iglesias | if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
|
351 | 40e9eddd | Edgar E. Iglesias | tcg_gen_andi_tl(t[1], t[1], 63); |
352 | 40e9eddd | Edgar E. Iglesias | } |
353 | 40e9eddd | Edgar E. Iglesias | |
354 | 40e9eddd | Edgar E. Iglesias | assert(dc->dst != 15);
|
355 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size); |
356 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t[0]);
|
357 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t[1]);
|
358 | 40e9eddd | Edgar E. Iglesias | } |
359 | 40e9eddd | Edgar E. Iglesias | |
360 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_bound(DisasContext *dc, int size) |
361 | 40e9eddd | Edgar E. Iglesias | { |
362 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
363 | 40e9eddd | Edgar E. Iglesias | |
364 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_local_new(); |
365 | 40e9eddd | Edgar E. Iglesias | t_gen_zext(t, cpu_R[dc->src], size); |
366 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
|
367 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
368 | 40e9eddd | Edgar E. Iglesias | } |
369 | 40e9eddd | Edgar E. Iglesias | |
370 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_mul(DisasContext *dc, int size, int sext) |
371 | 40e9eddd | Edgar E. Iglesias | { |
372 | 40e9eddd | Edgar E. Iglesias | int op = sext ? CC_OP_MULS : CC_OP_MULU;
|
373 | 40e9eddd | Edgar E. Iglesias | TCGv t[2];
|
374 | 40e9eddd | Edgar E. Iglesias | |
375 | 40e9eddd | Edgar E. Iglesias | t[0] = tcg_temp_new();
|
376 | 40e9eddd | Edgar E. Iglesias | t[1] = tcg_temp_new();
|
377 | 40e9eddd | Edgar E. Iglesias | dec10_reg_prep_sext(dc, size, sext, |
378 | 40e9eddd | Edgar E. Iglesias | t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); |
379 | 40e9eddd | Edgar E. Iglesias | |
380 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4); |
381 | 40e9eddd | Edgar E. Iglesias | |
382 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t[0]);
|
383 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t[1]);
|
384 | 40e9eddd | Edgar E. Iglesias | } |
385 | 40e9eddd | Edgar E. Iglesias | |
386 | 40e9eddd | Edgar E. Iglesias | |
387 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_movs(DisasContext *dc) |
388 | 40e9eddd | Edgar E. Iglesias | { |
389 | 40e9eddd | Edgar E. Iglesias | int size = (dc->size & 1) + 1; |
390 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
391 | 40e9eddd | Edgar E. Iglesias | |
392 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
|
393 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
394 | 40e9eddd | Edgar E. Iglesias | |
395 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
396 | 40e9eddd | Edgar E. Iglesias | if (dc->ir & 32) |
397 | 40e9eddd | Edgar E. Iglesias | t_gen_sext(t, cpu_R[dc->src], size); |
398 | 40e9eddd | Edgar E. Iglesias | else
|
399 | 40e9eddd | Edgar E. Iglesias | t_gen_zext(t, cpu_R[dc->src], size); |
400 | 40e9eddd | Edgar E. Iglesias | |
401 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
|
402 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
403 | 40e9eddd | Edgar E. Iglesias | } |
404 | 40e9eddd | Edgar E. Iglesias | |
405 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_alux(DisasContext *dc, int op) |
406 | 40e9eddd | Edgar E. Iglesias | { |
407 | 40e9eddd | Edgar E. Iglesias | int size = (dc->size & 1) + 1; |
408 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
409 | 40e9eddd | Edgar E. Iglesias | |
410 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
|
411 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
412 | 40e9eddd | Edgar E. Iglesias | |
413 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
414 | 40e9eddd | Edgar E. Iglesias | if (dc->ir & 32) |
415 | 40e9eddd | Edgar E. Iglesias | t_gen_sext(t, cpu_R[dc->src], size); |
416 | 40e9eddd | Edgar E. Iglesias | else
|
417 | 40e9eddd | Edgar E. Iglesias | t_gen_zext(t, cpu_R[dc->src], size); |
418 | 40e9eddd | Edgar E. Iglesias | |
419 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
|
420 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
421 | 40e9eddd | Edgar E. Iglesias | } |
422 | 40e9eddd | Edgar E. Iglesias | |
423 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_mov_pr(DisasContext *dc) |
424 | 40e9eddd | Edgar E. Iglesias | { |
425 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
|
426 | 40e9eddd | Edgar E. Iglesias | cris_lock_irq(dc); |
427 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15) { |
428 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]); |
429 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
430 | 40e9eddd | Edgar E. Iglesias | return;
|
431 | 40e9eddd | Edgar E. Iglesias | } |
432 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == PR_CCS) {
|
433 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
434 | 40e9eddd | Edgar E. Iglesias | } |
435 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], |
436 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]); |
437 | 40e9eddd | Edgar E. Iglesias | } |
438 | 40e9eddd | Edgar E. Iglesias | |
439 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_abs(DisasContext *dc) |
440 | 40e9eddd | Edgar E. Iglesias | { |
441 | bf76bafa | Edgar E. Iglesias | TCGv t0; |
442 | 40e9eddd | Edgar E. Iglesias | |
443 | bf76bafa | Edgar E. Iglesias | LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
|
444 | 40e9eddd | Edgar E. Iglesias | |
445 | bf76bafa | Edgar E. Iglesias | assert(dc->dst != 15);
|
446 | bf76bafa | Edgar E. Iglesias | t0 = tcg_temp_new(); |
447 | bf76bafa | Edgar E. Iglesias | tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
|
448 | bf76bafa | Edgar E. Iglesias | tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0); |
449 | bf76bafa | Edgar E. Iglesias | tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0); |
450 | 40e9eddd | Edgar E. Iglesias | |
451 | bf76bafa | Edgar E. Iglesias | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
|
452 | bf76bafa | Edgar E. Iglesias | tcg_temp_free(t0); |
453 | 40e9eddd | Edgar E. Iglesias | } |
454 | 40e9eddd | Edgar E. Iglesias | |
455 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_swap(DisasContext *dc) |
456 | 40e9eddd | Edgar E. Iglesias | { |
457 | 40e9eddd | Edgar E. Iglesias | TCGv t0; |
458 | 40e9eddd | Edgar E. Iglesias | |
459 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
|
460 | 40e9eddd | Edgar E. Iglesias | |
461 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
462 | 40e9eddd | Edgar E. Iglesias | t0 = tcg_temp_new(); |
463 | 40e9eddd | Edgar E. Iglesias | t_gen_mov_TN_reg(t0, dc->src); |
464 | 40e9eddd | Edgar E. Iglesias | if (dc->dst & 8) |
465 | 40e9eddd | Edgar E. Iglesias | tcg_gen_not_tl(t0, t0); |
466 | 40e9eddd | Edgar E. Iglesias | if (dc->dst & 4) |
467 | 40e9eddd | Edgar E. Iglesias | t_gen_swapw(t0, t0); |
468 | 40e9eddd | Edgar E. Iglesias | if (dc->dst & 2) |
469 | 40e9eddd | Edgar E. Iglesias | t_gen_swapb(t0, t0); |
470 | 40e9eddd | Edgar E. Iglesias | if (dc->dst & 1) |
471 | 40e9eddd | Edgar E. Iglesias | t_gen_swapr(t0, t0); |
472 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
|
473 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t0); |
474 | 40e9eddd | Edgar E. Iglesias | } |
475 | 40e9eddd | Edgar E. Iglesias | |
476 | 40e9eddd | Edgar E. Iglesias | static void dec10_reg_scc(DisasContext *dc) |
477 | 40e9eddd | Edgar E. Iglesias | { |
478 | bf76bafa | Edgar E. Iglesias | int cond = dc->dst;
|
479 | 40e9eddd | Edgar E. Iglesias | |
480 | bf76bafa | Edgar E. Iglesias | LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
|
481 | 40e9eddd | Edgar E. Iglesias | |
482 | bf76bafa | Edgar E. Iglesias | if (cond != CC_A)
|
483 | bf76bafa | Edgar E. Iglesias | { |
484 | bf76bafa | Edgar E. Iglesias | int l1;
|
485 | 40e9eddd | Edgar E. Iglesias | |
486 | bf76bafa | Edgar E. Iglesias | gen_tst_cc (dc, cpu_R[dc->src], cond); |
487 | bf76bafa | Edgar E. Iglesias | l1 = gen_new_label(); |
488 | bf76bafa | Edgar E. Iglesias | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->src], 0, l1);
|
489 | bf76bafa | Edgar E. Iglesias | tcg_gen_movi_tl(cpu_R[dc->src], 1);
|
490 | bf76bafa | Edgar E. Iglesias | gen_set_label(l1); |
491 | bf76bafa | Edgar E. Iglesias | } else {
|
492 | bf76bafa | Edgar E. Iglesias | tcg_gen_movi_tl(cpu_R[dc->src], 1);
|
493 | bf76bafa | Edgar E. Iglesias | } |
494 | 40e9eddd | Edgar E. Iglesias | |
495 | bf76bafa | Edgar E. Iglesias | cris_cc_mask(dc, 0);
|
496 | 40e9eddd | Edgar E. Iglesias | } |
497 | 40e9eddd | Edgar E. Iglesias | |
498 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_reg(DisasContext *dc) |
499 | 40e9eddd | Edgar E. Iglesias | { |
500 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
501 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2; |
502 | 40e9eddd | Edgar E. Iglesias | unsigned int size = dec10_size(dc->size); |
503 | 40e9eddd | Edgar E. Iglesias | unsigned int tmp; |
504 | 40e9eddd | Edgar E. Iglesias | |
505 | 40e9eddd | Edgar E. Iglesias | if (dc->size != 3) { |
506 | 40e9eddd | Edgar E. Iglesias | switch (dc->opcode) {
|
507 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_MOVE_R:
|
508 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
|
509 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
510 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
|
511 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 15) { |
512 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); |
513 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
514 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch = 1;
|
515 | 40e9eddd | Edgar E. Iglesias | } |
516 | 40e9eddd | Edgar E. Iglesias | break;
|
517 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_MOVX:
|
518 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
519 | 40e9eddd | Edgar E. Iglesias | dec10_reg_movs(dc); |
520 | 40e9eddd | Edgar E. Iglesias | break;
|
521 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_ADDX:
|
522 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
523 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alux(dc, CC_OP_ADD); |
524 | 40e9eddd | Edgar E. Iglesias | break;
|
525 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_SUBX:
|
526 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
527 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alux(dc, CC_OP_SUB); |
528 | 40e9eddd | Edgar E. Iglesias | break;
|
529 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_ADD:
|
530 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
531 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
532 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_ADD, size, 0);
|
533 | 40e9eddd | Edgar E. Iglesias | break;
|
534 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_SUB:
|
535 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
536 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
537 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_SUB, size, 0);
|
538 | 40e9eddd | Edgar E. Iglesias | break;
|
539 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_CMP:
|
540 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
541 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
542 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_CMP, size, 0);
|
543 | 40e9eddd | Edgar E. Iglesias | break;
|
544 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_BOUND:
|
545 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
546 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
547 | 40e9eddd | Edgar E. Iglesias | dec10_reg_bound(dc, size); |
548 | 40e9eddd | Edgar E. Iglesias | break;
|
549 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_AND:
|
550 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
551 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
552 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_AND, size, 0);
|
553 | 40e9eddd | Edgar E. Iglesias | break;
|
554 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_ADDI:
|
555 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15) { |
556 | 40e9eddd | Edgar E. Iglesias | /* nop. */
|
557 | 40e9eddd | Edgar E. Iglesias | return 2; |
558 | 40e9eddd | Edgar E. Iglesias | } |
559 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
560 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
|
561 | 40e9eddd | Edgar E. Iglesias | tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
|
562 | 40e9eddd | Edgar E. Iglesias | tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t); |
563 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
564 | 40e9eddd | Edgar E. Iglesias | break;
|
565 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_LSL:
|
566 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
567 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
568 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_LSL, size, 0);
|
569 | 40e9eddd | Edgar E. Iglesias | break;
|
570 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_LSR:
|
571 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
572 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
573 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_LSR, size, 0);
|
574 | 40e9eddd | Edgar E. Iglesias | break;
|
575 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_ASR:
|
576 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
577 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
578 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_ASR, size, 1);
|
579 | 40e9eddd | Edgar E. Iglesias | break;
|
580 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_OR:
|
581 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
582 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
583 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_OR, size, 0);
|
584 | 40e9eddd | Edgar E. Iglesias | break;
|
585 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_NEG:
|
586 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
587 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
588 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_NEG, size, 0);
|
589 | 40e9eddd | Edgar E. Iglesias | break;
|
590 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_BIAP:
|
591 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
|
592 | 40e9eddd | Edgar E. Iglesias | dc->opcode, dc->src, dc->dst, size); |
593 | 40e9eddd | Edgar E. Iglesias | switch (size) {
|
594 | 40e9eddd | Edgar E. Iglesias | case 4: tmp = 2; break; |
595 | 40e9eddd | Edgar E. Iglesias | case 2: tmp = 1; break; |
596 | 40e9eddd | Edgar E. Iglesias | case 1: tmp = 0; break; |
597 | 43dc2a64 | Blue Swirl | default:
|
598 | 43dc2a64 | Blue Swirl | cpu_abort(dc->env, "Unhandled BIAP");
|
599 | 43dc2a64 | Blue Swirl | break;
|
600 | 40e9eddd | Edgar E. Iglesias | } |
601 | 40e9eddd | Edgar E. Iglesias | |
602 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
603 | 40e9eddd | Edgar E. Iglesias | tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp); |
604 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15) { |
605 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1); |
606 | 40e9eddd | Edgar E. Iglesias | } else {
|
607 | 40e9eddd | Edgar E. Iglesias | tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t); |
608 | 40e9eddd | Edgar E. Iglesias | } |
609 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
610 | 40e9eddd | Edgar E. Iglesias | cris_set_prefix(dc); |
611 | 40e9eddd | Edgar E. Iglesias | break;
|
612 | 40e9eddd | Edgar E. Iglesias | |
613 | 40e9eddd | Edgar E. Iglesias | default:
|
614 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
|
615 | 40e9eddd | Edgar E. Iglesias | dc->opcode, dc->src, dc->dst); |
616 | 43dc2a64 | Blue Swirl | cpu_abort(dc->env, "Unhandled opcode");
|
617 | 40e9eddd | Edgar E. Iglesias | break;
|
618 | 40e9eddd | Edgar E. Iglesias | } |
619 | 40e9eddd | Edgar E. Iglesias | } else {
|
620 | 40e9eddd | Edgar E. Iglesias | switch (dc->opcode) {
|
621 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_MOVX:
|
622 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
623 | 40e9eddd | Edgar E. Iglesias | dec10_reg_movs(dc); |
624 | 40e9eddd | Edgar E. Iglesias | break;
|
625 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_ADDX:
|
626 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
627 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alux(dc, CC_OP_ADD); |
628 | 40e9eddd | Edgar E. Iglesias | break;
|
629 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_SUBX:
|
630 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
631 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alux(dc, CC_OP_SUB); |
632 | 40e9eddd | Edgar E. Iglesias | break;
|
633 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_MOVE_SPR_R:
|
634 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
635 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, 0);
|
636 | 40e9eddd | Edgar E. Iglesias | dec10_reg_mov_pr(dc); |
637 | 40e9eddd | Edgar E. Iglesias | break;
|
638 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_MOVE_R_SPR:
|
639 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
|
640 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
641 | 40e9eddd | Edgar E. Iglesias | if (dc->src != 11) /* fast for srp. */ |
642 | 40e9eddd | Edgar E. Iglesias | dc->cpustate_changed = 1;
|
643 | 40e9eddd | Edgar E. Iglesias | t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]); |
644 | 40e9eddd | Edgar E. Iglesias | break;
|
645 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_SETF:
|
646 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_CLEARF:
|
647 | 40e9eddd | Edgar E. Iglesias | dec10_setclrf(dc); |
648 | 40e9eddd | Edgar E. Iglesias | break;
|
649 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_SWAP:
|
650 | 40e9eddd | Edgar E. Iglesias | dec10_reg_swap(dc); |
651 | 40e9eddd | Edgar E. Iglesias | break;
|
652 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_ABS:
|
653 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
654 | 40e9eddd | Edgar E. Iglesias | dec10_reg_abs(dc); |
655 | 40e9eddd | Edgar E. Iglesias | break;
|
656 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_LZ:
|
657 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
658 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
659 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_LZ, 4, 0); |
660 | 40e9eddd | Edgar E. Iglesias | break;
|
661 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_XOR:
|
662 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
663 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
664 | 40e9eddd | Edgar E. Iglesias | dec10_reg_alu(dc, CC_OP_XOR, 4, 0); |
665 | 40e9eddd | Edgar E. Iglesias | break;
|
666 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_BTST:
|
667 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
668 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
669 | 40e9eddd | Edgar E. Iglesias | cris_update_cc_op(dc, CC_OP_FLAGS, 4);
|
670 | 40e9eddd | Edgar E. Iglesias | gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst], |
671 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->src], cpu_PR[PR_CCS]); |
672 | 40e9eddd | Edgar E. Iglesias | break;
|
673 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_DSTEP:
|
674 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
675 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
676 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst], |
677 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], cpu_R[dc->src], 4);
|
678 | 40e9eddd | Edgar E. Iglesias | break;
|
679 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_MSTEP:
|
680 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
|
681 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
682 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
683 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst], |
684 | 40e9eddd | Edgar E. Iglesias | cpu_R[dc->dst], cpu_R[dc->src], 4);
|
685 | 40e9eddd | Edgar E. Iglesias | break;
|
686 | 40e9eddd | Edgar E. Iglesias | case CRISV10_REG_SCC:
|
687 | 40e9eddd | Edgar E. Iglesias | dec10_reg_scc(dc); |
688 | 40e9eddd | Edgar E. Iglesias | break;
|
689 | 40e9eddd | Edgar E. Iglesias | default:
|
690 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
|
691 | 40e9eddd | Edgar E. Iglesias | dc->opcode, dc->src, dc->dst); |
692 | 43dc2a64 | Blue Swirl | cpu_abort(dc->env, "Unhandled opcode");
|
693 | 40e9eddd | Edgar E. Iglesias | break;
|
694 | 40e9eddd | Edgar E. Iglesias | } |
695 | 40e9eddd | Edgar E. Iglesias | } |
696 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
697 | 40e9eddd | Edgar E. Iglesias | } |
698 | 40e9eddd | Edgar E. Iglesias | |
699 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size) |
700 | 40e9eddd | Edgar E. Iglesias | { |
701 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2; |
702 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
703 | 40e9eddd | Edgar E. Iglesias | |
704 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
|
705 | 40e9eddd | Edgar E. Iglesias | size, dc->src, dc->dst); |
706 | 40e9eddd | Edgar E. Iglesias | |
707 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
708 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
709 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, 0, size, t);
|
710 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size); |
711 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 15) { |
712 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); |
713 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
714 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch = 1;
|
715 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
716 | 40e9eddd | Edgar E. Iglesias | } |
717 | 40e9eddd | Edgar E. Iglesias | |
718 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
719 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
720 | 40e9eddd | Edgar E. Iglesias | } |
721 | 40e9eddd | Edgar E. Iglesias | |
722 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size) |
723 | 40e9eddd | Edgar E. Iglesias | { |
724 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2; |
725 | 40e9eddd | Edgar E. Iglesias | TCGv addr; |
726 | 40e9eddd | Edgar E. Iglesias | |
727 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
|
728 | 40e9eddd | Edgar E. Iglesias | addr = tcg_temp_new(); |
729 | 40e9eddd | Edgar E. Iglesias | crisv10_prepare_memaddr(dc, addr, size); |
730 | 40e9eddd | Edgar E. Iglesias | gen_store(dc, addr, cpu_R[dc->dst], size); |
731 | 40e9eddd | Edgar E. Iglesias | insn_len += crisv10_post_memaddr(dc, size); |
732 | 40e9eddd | Edgar E. Iglesias | |
733 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
734 | 40e9eddd | Edgar E. Iglesias | } |
735 | 40e9eddd | Edgar E. Iglesias | |
736 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_ind_move_m_pr(DisasContext *dc) |
737 | 40e9eddd | Edgar E. Iglesias | { |
738 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2, rd = dc->dst; |
739 | 40e9eddd | Edgar E. Iglesias | TCGv t, addr; |
740 | 40e9eddd | Edgar E. Iglesias | |
741 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
|
742 | 40e9eddd | Edgar E. Iglesias | cris_lock_irq(dc); |
743 | 40e9eddd | Edgar E. Iglesias | |
744 | 40e9eddd | Edgar E. Iglesias | addr = tcg_temp_new(); |
745 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
746 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, 0, 4, t); |
747 | 40e9eddd | Edgar E. Iglesias | if (rd == 15) { |
748 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, t); |
749 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
750 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch = 1;
|
751 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
752 | 40e9eddd | Edgar E. Iglesias | } |
753 | 40e9eddd | Edgar E. Iglesias | |
754 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(cpu_PR[rd], t); |
755 | 40e9eddd | Edgar E. Iglesias | dc->cpustate_changed = 1;
|
756 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(addr); |
757 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
758 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
759 | 40e9eddd | Edgar E. Iglesias | } |
760 | 40e9eddd | Edgar E. Iglesias | |
761 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_ind_move_pr_m(DisasContext *dc) |
762 | 40e9eddd | Edgar E. Iglesias | { |
763 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst]; |
764 | 40e9eddd | Edgar E. Iglesias | TCGv addr, t0; |
765 | 40e9eddd | Edgar E. Iglesias | |
766 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
|
767 | 40e9eddd | Edgar E. Iglesias | |
768 | 40e9eddd | Edgar E. Iglesias | addr = tcg_temp_new(); |
769 | 40e9eddd | Edgar E. Iglesias | crisv10_prepare_memaddr(dc, addr, size); |
770 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == PR_CCS) {
|
771 | 40e9eddd | Edgar E. Iglesias | t0 = tcg_temp_new(); |
772 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
773 | 40e9eddd | Edgar E. Iglesias | tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); |
774 | 40e9eddd | Edgar E. Iglesias | gen_store(dc, addr, t0, size); |
775 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t0); |
776 | 40e9eddd | Edgar E. Iglesias | } else {
|
777 | 40e9eddd | Edgar E. Iglesias | gen_store(dc, addr, cpu_PR[dc->dst], size); |
778 | 40e9eddd | Edgar E. Iglesias | } |
779 | 40e9eddd | Edgar E. Iglesias | t0 = tcg_temp_new(); |
780 | 40e9eddd | Edgar E. Iglesias | insn_len += crisv10_post_memaddr(dc, size); |
781 | 40e9eddd | Edgar E. Iglesias | cris_lock_irq(dc); |
782 | 40e9eddd | Edgar E. Iglesias | |
783 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
784 | 40e9eddd | Edgar E. Iglesias | } |
785 | 40e9eddd | Edgar E. Iglesias | |
786 | 40e9eddd | Edgar E. Iglesias | static void dec10_movem_r_m(DisasContext *dc) |
787 | 40e9eddd | Edgar E. Iglesias | { |
788 | 40e9eddd | Edgar E. Iglesias | int i, pfix = dc->tb_flags & PFIX_FLAG;
|
789 | 40e9eddd | Edgar E. Iglesias | TCGv addr, t0; |
790 | 40e9eddd | Edgar E. Iglesias | |
791 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
|
792 | 40e9eddd | Edgar E. Iglesias | dc->dst, dc->src, dc->postinc, dc->ir); |
793 | 40e9eddd | Edgar E. Iglesias | |
794 | 40e9eddd | Edgar E. Iglesias | addr = tcg_temp_new(); |
795 | 40e9eddd | Edgar E. Iglesias | t0 = tcg_temp_new(); |
796 | 40e9eddd | Edgar E. Iglesias | crisv10_prepare_memaddr(dc, addr, 4);
|
797 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(t0, addr); |
798 | 40e9eddd | Edgar E. Iglesias | for (i = dc->dst; i >= 0; i--) { |
799 | 40e9eddd | Edgar E. Iglesias | if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
|
800 | 40e9eddd | Edgar E. Iglesias | gen_store(dc, addr, t0, 4);
|
801 | 40e9eddd | Edgar E. Iglesias | } else {
|
802 | 40e9eddd | Edgar E. Iglesias | gen_store(dc, addr, cpu_R[i], 4);
|
803 | 40e9eddd | Edgar E. Iglesias | } |
804 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(addr, addr, 4);
|
805 | 40e9eddd | Edgar E. Iglesias | } |
806 | 40e9eddd | Edgar E. Iglesias | |
807 | 40e9eddd | Edgar E. Iglesias | if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
|
808 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(cpu_R[dc->src], t0); |
809 | 40e9eddd | Edgar E. Iglesias | } |
810 | 40e9eddd | Edgar E. Iglesias | |
811 | 40e9eddd | Edgar E. Iglesias | if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
|
812 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(cpu_R[dc->src], addr); |
813 | 40e9eddd | Edgar E. Iglesias | } |
814 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(addr); |
815 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t0); |
816 | 40e9eddd | Edgar E. Iglesias | } |
817 | 40e9eddd | Edgar E. Iglesias | |
818 | 40e9eddd | Edgar E. Iglesias | static void dec10_movem_m_r(DisasContext *dc) |
819 | 40e9eddd | Edgar E. Iglesias | { |
820 | 40e9eddd | Edgar E. Iglesias | int i, pfix = dc->tb_flags & PFIX_FLAG;
|
821 | 40e9eddd | Edgar E. Iglesias | TCGv addr, t0; |
822 | 40e9eddd | Edgar E. Iglesias | |
823 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
|
824 | 40e9eddd | Edgar E. Iglesias | dc->src, dc->dst, dc->postinc, dc->ir); |
825 | 40e9eddd | Edgar E. Iglesias | |
826 | 40e9eddd | Edgar E. Iglesias | addr = tcg_temp_new(); |
827 | 40e9eddd | Edgar E. Iglesias | t0 = tcg_temp_new(); |
828 | 40e9eddd | Edgar E. Iglesias | crisv10_prepare_memaddr(dc, addr, 4);
|
829 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(t0, addr); |
830 | 40e9eddd | Edgar E. Iglesias | for (i = dc->dst; i >= 0; i--) { |
831 | 40e9eddd | Edgar E. Iglesias | gen_load(dc, cpu_R[i], addr, 4, 0); |
832 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(addr, addr, 4);
|
833 | 40e9eddd | Edgar E. Iglesias | } |
834 | 40e9eddd | Edgar E. Iglesias | |
835 | 40e9eddd | Edgar E. Iglesias | if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
|
836 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(cpu_R[dc->src], t0); |
837 | 40e9eddd | Edgar E. Iglesias | } |
838 | 40e9eddd | Edgar E. Iglesias | |
839 | 40e9eddd | Edgar E. Iglesias | if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
|
840 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(cpu_R[dc->src], addr); |
841 | 40e9eddd | Edgar E. Iglesias | } |
842 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(addr); |
843 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t0); |
844 | 40e9eddd | Edgar E. Iglesias | } |
845 | 40e9eddd | Edgar E. Iglesias | |
846 | 40e9eddd | Edgar E. Iglesias | static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size) |
847 | 40e9eddd | Edgar E. Iglesias | { |
848 | 40e9eddd | Edgar E. Iglesias | int insn_len = 0; |
849 | 40e9eddd | Edgar E. Iglesias | int rd = dc->dst;
|
850 | 40e9eddd | Edgar E. Iglesias | TCGv t[2];
|
851 | 40e9eddd | Edgar E. Iglesias | |
852 | 40e9eddd | Edgar E. Iglesias | cris_alu_m_alloc_temps(t); |
853 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, 0, size, t[0]); |
854 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
|
855 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 15) { |
856 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); |
857 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
858 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch = 1;
|
859 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
860 | 40e9eddd | Edgar E. Iglesias | } |
861 | 40e9eddd | Edgar E. Iglesias | |
862 | 40e9eddd | Edgar E. Iglesias | cris_alu_m_free_temps(t); |
863 | 40e9eddd | Edgar E. Iglesias | |
864 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
865 | 40e9eddd | Edgar E. Iglesias | } |
866 | 40e9eddd | Edgar E. Iglesias | |
867 | 40e9eddd | Edgar E. Iglesias | static int dec10_ind_bound(DisasContext *dc, unsigned int size) |
868 | 40e9eddd | Edgar E. Iglesias | { |
869 | 40e9eddd | Edgar E. Iglesias | int insn_len = 0; |
870 | 40e9eddd | Edgar E. Iglesias | int rd = dc->dst;
|
871 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
872 | 40e9eddd | Edgar E. Iglesias | |
873 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_local_new(); |
874 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, 0, size, t);
|
875 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
|
876 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 15) { |
877 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); |
878 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
879 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch = 1;
|
880 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
881 | 40e9eddd | Edgar E. Iglesias | } |
882 | 40e9eddd | Edgar E. Iglesias | |
883 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
884 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
885 | 40e9eddd | Edgar E. Iglesias | } |
886 | 40e9eddd | Edgar E. Iglesias | |
887 | 40e9eddd | Edgar E. Iglesias | static int dec10_alux_m(DisasContext *dc, int op) |
888 | 40e9eddd | Edgar E. Iglesias | { |
889 | 40e9eddd | Edgar E. Iglesias | unsigned int size = (dc->size & 1) ? 2 : 1; |
890 | 40e9eddd | Edgar E. Iglesias | unsigned int sx = !!(dc->size & 2); |
891 | 40e9eddd | Edgar E. Iglesias | int insn_len = 2; |
892 | 40e9eddd | Edgar E. Iglesias | int rd = dc->dst;
|
893 | 40e9eddd | Edgar E. Iglesias | TCGv t; |
894 | 40e9eddd | Edgar E. Iglesias | |
895 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
|
896 | 40e9eddd | Edgar E. Iglesias | |
897 | 40e9eddd | Edgar E. Iglesias | t = tcg_temp_new(); |
898 | 40e9eddd | Edgar E. Iglesias | |
899 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
900 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, sx, size, t); |
901 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
|
902 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 15) { |
903 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); |
904 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
905 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch = 1;
|
906 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
907 | 40e9eddd | Edgar E. Iglesias | } |
908 | 40e9eddd | Edgar E. Iglesias | |
909 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t); |
910 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
911 | 40e9eddd | Edgar E. Iglesias | } |
912 | 40e9eddd | Edgar E. Iglesias | |
913 | 40e9eddd | Edgar E. Iglesias | static int dec10_dip(DisasContext *dc) |
914 | 40e9eddd | Edgar E. Iglesias | { |
915 | 40e9eddd | Edgar E. Iglesias | int insn_len = 2; |
916 | 40e9eddd | Edgar E. Iglesias | uint32_t imm; |
917 | 40e9eddd | Edgar E. Iglesias | |
918 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
|
919 | 40e9eddd | Edgar E. Iglesias | dc->pc, dc->opcode, dc->src, dc->dst); |
920 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15) { |
921 | 40e9eddd | Edgar E. Iglesias | imm = ldl_code(dc->pc + 2);
|
922 | 40e9eddd | Edgar E. Iglesias | tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm); |
923 | 40e9eddd | Edgar E. Iglesias | if (dc->postinc)
|
924 | 40e9eddd | Edgar E. Iglesias | insn_len += 4;
|
925 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2); |
926 | 40e9eddd | Edgar E. Iglesias | } else {
|
927 | 40e9eddd | Edgar E. Iglesias | gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0); |
928 | 40e9eddd | Edgar E. Iglesias | if (dc->postinc)
|
929 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
|
930 | 40e9eddd | Edgar E. Iglesias | } |
931 | 40e9eddd | Edgar E. Iglesias | |
932 | 40e9eddd | Edgar E. Iglesias | cris_set_prefix(dc); |
933 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
934 | 40e9eddd | Edgar E. Iglesias | } |
935 | 40e9eddd | Edgar E. Iglesias | |
936 | 40e9eddd | Edgar E. Iglesias | static int dec10_bdap_m(DisasContext *dc, int size) |
937 | 40e9eddd | Edgar E. Iglesias | { |
938 | 40e9eddd | Edgar E. Iglesias | int insn_len = 2; |
939 | 40e9eddd | Edgar E. Iglesias | int rd = dc->dst;
|
940 | 40e9eddd | Edgar E. Iglesias | |
941 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
|
942 | 40e9eddd | Edgar E. Iglesias | dc->pc, dc->opcode, dc->src, dc->dst, size); |
943 | 40e9eddd | Edgar E. Iglesias | |
944 | 40e9eddd | Edgar E. Iglesias | assert(dc->dst != 15);
|
945 | 40e9eddd | Edgar E. Iglesias | #if 0
|
946 | 40e9eddd | Edgar E. Iglesias | /* 8bit embedded offset? */
|
947 | 40e9eddd | Edgar E. Iglesias | if (!dc->postinc && (dc->ir & (1 << 11))) {
|
948 | 40e9eddd | Edgar E. Iglesias | int simm = dc->ir & 0xff;
|
949 | 40e9eddd | Edgar E. Iglesias | |
950 | 43dc2a64 | Blue Swirl | /* cpu_abort(dc->env, "Unhandled opcode"); */
|
951 | 40e9eddd | Edgar E. Iglesias | /* sign extended. */
|
952 | 40e9eddd | Edgar E. Iglesias | simm = (int8_t)simm;
|
953 | 40e9eddd | Edgar E. Iglesias | |
954 | 40e9eddd | Edgar E. Iglesias | tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
|
955 | 40e9eddd | Edgar E. Iglesias | |
956 | 40e9eddd | Edgar E. Iglesias | cris_set_prefix(dc);
|
957 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
958 | 40e9eddd | Edgar E. Iglesias | }
|
959 | 40e9eddd | Edgar E. Iglesias | #endif
|
960 | 40e9eddd | Edgar E. Iglesias | /* Now the rest of the modes are truely indirect. */
|
961 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, 1, size, cpu_PR[PR_PREFIX]);
|
962 | 40e9eddd | Edgar E. Iglesias | tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]); |
963 | 40e9eddd | Edgar E. Iglesias | cris_set_prefix(dc); |
964 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
965 | 40e9eddd | Edgar E. Iglesias | } |
966 | 40e9eddd | Edgar E. Iglesias | |
967 | 40e9eddd | Edgar E. Iglesias | static unsigned int dec10_ind(DisasContext *dc) |
968 | 40e9eddd | Edgar E. Iglesias | { |
969 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2; |
970 | 40e9eddd | Edgar E. Iglesias | unsigned int size = dec10_size(dc->size); |
971 | 40e9eddd | Edgar E. Iglesias | uint32_t imm; |
972 | 40e9eddd | Edgar E. Iglesias | int32_t simm; |
973 | 40e9eddd | Edgar E. Iglesias | TCGv t[2];
|
974 | 40e9eddd | Edgar E. Iglesias | |
975 | 40e9eddd | Edgar E. Iglesias | if (dc->size != 3) { |
976 | 40e9eddd | Edgar E. Iglesias | switch (dc->opcode) {
|
977 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVE_M_R:
|
978 | 40e9eddd | Edgar E. Iglesias | return dec10_ind_move_m_r(dc, size);
|
979 | 40e9eddd | Edgar E. Iglesias | break;
|
980 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVE_R_M:
|
981 | 40e9eddd | Edgar E. Iglesias | return dec10_ind_move_r_m(dc, size);
|
982 | 40e9eddd | Edgar E. Iglesias | break;
|
983 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_CMP:
|
984 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
|
985 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
986 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_ind_alu(dc, CC_OP_CMP, size); |
987 | 40e9eddd | Edgar E. Iglesias | break;
|
988 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_TEST:
|
989 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
|
990 | 40e9eddd | Edgar E. Iglesias | |
991 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
992 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
993 | 40e9eddd | Edgar E. Iglesias | cris_alu_m_alloc_temps(t); |
994 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_prep_move_m(dc, 0, size, t[0]); |
995 | 40e9eddd | Edgar E. Iglesias | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
|
996 | 40e9eddd | Edgar E. Iglesias | cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], |
997 | 40e9eddd | Edgar E. Iglesias | t[0], tcg_const_tl(0), size); |
998 | 40e9eddd | Edgar E. Iglesias | cris_alu_m_free_temps(t); |
999 | 40e9eddd | Edgar E. Iglesias | break;
|
1000 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_ADD:
|
1001 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
|
1002 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
1003 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_ind_alu(dc, CC_OP_ADD, size); |
1004 | 40e9eddd | Edgar E. Iglesias | break;
|
1005 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_SUB:
|
1006 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
|
1007 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
1008 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_ind_alu(dc, CC_OP_SUB, size); |
1009 | 40e9eddd | Edgar E. Iglesias | break;
|
1010 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_BOUND:
|
1011 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
|
1012 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
1013 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_ind_bound(dc, size); |
1014 | 40e9eddd | Edgar E. Iglesias | break;
|
1015 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_AND:
|
1016 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
|
1017 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
1018 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_ind_alu(dc, CC_OP_AND, size); |
1019 | 40e9eddd | Edgar E. Iglesias | break;
|
1020 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_OR:
|
1021 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
|
1022 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
1023 | 40e9eddd | Edgar E. Iglesias | insn_len += dec10_ind_alu(dc, CC_OP_OR, size); |
1024 | 40e9eddd | Edgar E. Iglesias | break;
|
1025 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVX:
|
1026 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_MOVE); |
1027 | 40e9eddd | Edgar E. Iglesias | break;
|
1028 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_ADDX:
|
1029 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_ADD); |
1030 | 40e9eddd | Edgar E. Iglesias | break;
|
1031 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_SUBX:
|
1032 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_SUB); |
1033 | 40e9eddd | Edgar E. Iglesias | break;
|
1034 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_CMPX:
|
1035 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_CMP); |
1036 | 40e9eddd | Edgar E. Iglesias | break;
|
1037 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MUL:
|
1038 | 40e9eddd | Edgar E. Iglesias | /* This is a reg insn coded in the mem indir space. */
|
1039 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
|
1040 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, CC_MASK_NZVC); |
1041 | 40e9eddd | Edgar E. Iglesias | dec10_reg_mul(dc, size, dc->ir & (1 << 10)); |
1042 | 40e9eddd | Edgar E. Iglesias | break;
|
1043 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_BDAP_M:
|
1044 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_bdap_m(dc, size); |
1045 | 40e9eddd | Edgar E. Iglesias | break;
|
1046 | 40e9eddd | Edgar E. Iglesias | default:
|
1047 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
|
1048 | 40e9eddd | Edgar E. Iglesias | dc->pc, size, dc->opcode, dc->src, dc->dst); |
1049 | 43dc2a64 | Blue Swirl | cpu_abort(dc->env, "Unhandled opcode");
|
1050 | 40e9eddd | Edgar E. Iglesias | break;
|
1051 | 40e9eddd | Edgar E. Iglesias | } |
1052 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
1053 | 40e9eddd | Edgar E. Iglesias | } |
1054 | 40e9eddd | Edgar E. Iglesias | |
1055 | 40e9eddd | Edgar E. Iglesias | switch (dc->opcode) {
|
1056 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVE_M_SPR:
|
1057 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_ind_move_m_pr(dc); |
1058 | 40e9eddd | Edgar E. Iglesias | break;
|
1059 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVE_SPR_M:
|
1060 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_ind_move_pr_m(dc); |
1061 | 40e9eddd | Edgar E. Iglesias | break;
|
1062 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_JUMP_M:
|
1063 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15) { |
1064 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("jump.%d %d r%d r%d\n", size,
|
1065 | 40e9eddd | Edgar E. Iglesias | dc->opcode, dc->src, dc->dst); |
1066 | 40e9eddd | Edgar E. Iglesias | imm = ldl_code(dc->pc + 2);
|
1067 | 40e9eddd | Edgar E. Iglesias | if (dc->mode == CRISV10_MODE_AUTOINC)
|
1068 | 40e9eddd | Edgar E. Iglesias | insn_len += size; |
1069 | 40e9eddd | Edgar E. Iglesias | |
1070 | 40e9eddd | Edgar E. Iglesias | t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); |
1071 | 40e9eddd | Edgar E. Iglesias | tcg_gen_movi_tl(env_btarget, imm); |
1072 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
1073 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch--; /* v10 has no dslot here. */
|
1074 | 40e9eddd | Edgar E. Iglesias | } else {
|
1075 | 40e9eddd | Edgar E. Iglesias | if (dc->dst == 14) { |
1076 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("break %d\n", dc->src);
|
1077 | 40e9eddd | Edgar E. Iglesias | cris_evaluate_flags(dc); |
1078 | 40e9eddd | Edgar E. Iglesias | tcg_gen_movi_tl(env_pc, dc->pc + 2);
|
1079 | 40e9eddd | Edgar E. Iglesias | t_gen_raise_exception(EXCP_BREAK); |
1080 | 40e9eddd | Edgar E. Iglesias | dc->is_jmp = DISAS_UPDATE; |
1081 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
1082 | 40e9eddd | Edgar E. Iglesias | } |
1083 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
|
1084 | 40e9eddd | Edgar E. Iglesias | dc->opcode, dc->src, dc->dst); |
1085 | 40e9eddd | Edgar E. Iglesias | t[0] = tcg_temp_new();
|
1086 | 40e9eddd | Edgar E. Iglesias | t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); |
1087 | 40e9eddd | Edgar E. Iglesias | crisv10_prepare_memaddr(dc, t[0], size);
|
1088 | 40e9eddd | Edgar E. Iglesias | gen_load(dc, env_btarget, t[0], 4, 0); |
1089 | 40e9eddd | Edgar E. Iglesias | insn_len += crisv10_post_memaddr(dc, size); |
1090 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
1091 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch--; /* v10 has no dslot here. */
|
1092 | 40e9eddd | Edgar E. Iglesias | tcg_temp_free(t[0]);
|
1093 | 40e9eddd | Edgar E. Iglesias | } |
1094 | 40e9eddd | Edgar E. Iglesias | break;
|
1095 | 40e9eddd | Edgar E. Iglesias | |
1096 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVEM_R_M:
|
1097 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
|
1098 | 40e9eddd | Edgar E. Iglesias | dc->pc, dc->opcode, dc->dst, dc->src); |
1099 | 40e9eddd | Edgar E. Iglesias | dec10_movem_r_m(dc); |
1100 | 40e9eddd | Edgar E. Iglesias | break;
|
1101 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVEM_M_R:
|
1102 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
|
1103 | 40e9eddd | Edgar E. Iglesias | dec10_movem_m_r(dc); |
1104 | 40e9eddd | Edgar E. Iglesias | break;
|
1105 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_JUMP_R:
|
1106 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
|
1107 | 40e9eddd | Edgar E. Iglesias | dc->pc, dc->opcode, dc->dst, dc->src); |
1108 | 40e9eddd | Edgar E. Iglesias | tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); |
1109 | 40e9eddd | Edgar E. Iglesias | t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); |
1110 | 40e9eddd | Edgar E. Iglesias | cris_prepare_jmp(dc, JMP_INDIRECT); |
1111 | 40e9eddd | Edgar E. Iglesias | dc->delayed_branch--; /* v10 has no dslot here. */
|
1112 | 40e9eddd | Edgar E. Iglesias | break;
|
1113 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_MOVX:
|
1114 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_MOVE); |
1115 | 40e9eddd | Edgar E. Iglesias | break;
|
1116 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_ADDX:
|
1117 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_ADD); |
1118 | 40e9eddd | Edgar E. Iglesias | break;
|
1119 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_SUBX:
|
1120 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_SUB); |
1121 | 40e9eddd | Edgar E. Iglesias | break;
|
1122 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_CMPX:
|
1123 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_alux_m(dc, CC_OP_CMP); |
1124 | 40e9eddd | Edgar E. Iglesias | break;
|
1125 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_DIP:
|
1126 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_dip(dc); |
1127 | 40e9eddd | Edgar E. Iglesias | break;
|
1128 | 40e9eddd | Edgar E. Iglesias | case CRISV10_IND_BCC_M:
|
1129 | 40e9eddd | Edgar E. Iglesias | |
1130 | 40e9eddd | Edgar E. Iglesias | cris_cc_mask(dc, 0);
|
1131 | 40e9eddd | Edgar E. Iglesias | imm = ldsw_code(dc->pc + 2);
|
1132 | 40e9eddd | Edgar E. Iglesias | simm = (int16_t)imm; |
1133 | 40e9eddd | Edgar E. Iglesias | simm += 4;
|
1134 | 40e9eddd | Edgar E. Iglesias | |
1135 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
|
1136 | 40e9eddd | Edgar E. Iglesias | cris_prepare_cc_branch(dc, simm, dc->cond); |
1137 | 40e9eddd | Edgar E. Iglesias | insn_len = 4;
|
1138 | 40e9eddd | Edgar E. Iglesias | break;
|
1139 | 40e9eddd | Edgar E. Iglesias | default:
|
1140 | 40e9eddd | Edgar E. Iglesias | LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
|
1141 | 43dc2a64 | Blue Swirl | cpu_abort(dc->env, "Unhandled opcode");
|
1142 | 40e9eddd | Edgar E. Iglesias | break;
|
1143 | 40e9eddd | Edgar E. Iglesias | } |
1144 | 40e9eddd | Edgar E. Iglesias | |
1145 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
1146 | 40e9eddd | Edgar E. Iglesias | } |
1147 | 40e9eddd | Edgar E. Iglesias | |
1148 | 40e9eddd | Edgar E. Iglesias | static unsigned int crisv10_decoder(DisasContext *dc) |
1149 | 40e9eddd | Edgar E. Iglesias | { |
1150 | 40e9eddd | Edgar E. Iglesias | unsigned int insn_len = 2; |
1151 | 40e9eddd | Edgar E. Iglesias | |
1152 | 40e9eddd | Edgar E. Iglesias | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1153 | 40e9eddd | Edgar E. Iglesias | tcg_gen_debug_insn_start(dc->pc); |
1154 | 40e9eddd | Edgar E. Iglesias | |
1155 | 40e9eddd | Edgar E. Iglesias | /* Load a halfword onto the instruction register. */
|
1156 | 40e9eddd | Edgar E. Iglesias | dc->ir = lduw_code(dc->pc); |
1157 | 40e9eddd | Edgar E. Iglesias | |
1158 | 40e9eddd | Edgar E. Iglesias | /* Now decode it. */
|
1159 | 40e9eddd | Edgar E. Iglesias | dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9); |
1160 | 40e9eddd | Edgar E. Iglesias | dc->mode = EXTRACT_FIELD(dc->ir, 10, 11); |
1161 | 40e9eddd | Edgar E. Iglesias | dc->src = EXTRACT_FIELD(dc->ir, 0, 3); |
1162 | 40e9eddd | Edgar E. Iglesias | dc->size = EXTRACT_FIELD(dc->ir, 4, 5); |
1163 | 40e9eddd | Edgar E. Iglesias | dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15); |
1164 | 40e9eddd | Edgar E. Iglesias | dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); |
1165 | 40e9eddd | Edgar E. Iglesias | |
1166 | 40e9eddd | Edgar E. Iglesias | dc->clear_prefix = 1;
|
1167 | 40e9eddd | Edgar E. Iglesias | |
1168 | 40e9eddd | Edgar E. Iglesias | /* FIXME: What if this insn insn't 2 in length?? */
|
1169 | 40e9eddd | Edgar E. Iglesias | if (dc->src == 15 || dc->dst == 15) |
1170 | 40e9eddd | Edgar E. Iglesias | tcg_gen_movi_tl(cpu_R[15], dc->pc + 2); |
1171 | 40e9eddd | Edgar E. Iglesias | |
1172 | 40e9eddd | Edgar E. Iglesias | switch (dc->mode) {
|
1173 | 40e9eddd | Edgar E. Iglesias | case CRISV10_MODE_QIMMEDIATE:
|
1174 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_quick_imm(dc); |
1175 | 40e9eddd | Edgar E. Iglesias | break;
|
1176 | 40e9eddd | Edgar E. Iglesias | case CRISV10_MODE_REG:
|
1177 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_reg(dc); |
1178 | 40e9eddd | Edgar E. Iglesias | break;
|
1179 | 40e9eddd | Edgar E. Iglesias | case CRISV10_MODE_AUTOINC:
|
1180 | 40e9eddd | Edgar E. Iglesias | case CRISV10_MODE_INDIRECT:
|
1181 | 40e9eddd | Edgar E. Iglesias | insn_len = dec10_ind(dc); |
1182 | 40e9eddd | Edgar E. Iglesias | break;
|
1183 | 40e9eddd | Edgar E. Iglesias | } |
1184 | 40e9eddd | Edgar E. Iglesias | |
1185 | 40e9eddd | Edgar E. Iglesias | if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
|
1186 | 40e9eddd | Edgar E. Iglesias | dc->tb_flags &= ~PFIX_FLAG; |
1187 | 40e9eddd | Edgar E. Iglesias | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG); |
1188 | 40e9eddd | Edgar E. Iglesias | dc->cpustate_changed = 1;
|
1189 | 40e9eddd | Edgar E. Iglesias | } |
1190 | 40e9eddd | Edgar E. Iglesias | |
1191 | 4ffb9ae2 | Edgar E. Iglesias | /* CRISv10 locks out interrupts on dslots. */
|
1192 | 4ffb9ae2 | Edgar E. Iglesias | if (dc->delayed_branch == 2) { |
1193 | 4ffb9ae2 | Edgar E. Iglesias | cris_lock_irq(dc); |
1194 | 4ffb9ae2 | Edgar E. Iglesias | } |
1195 | 40e9eddd | Edgar E. Iglesias | return insn_len;
|
1196 | 40e9eddd | Edgar E. Iglesias | } |
1197 | 40e9eddd | Edgar E. Iglesias | |
1198 | 40e9eddd | Edgar E. Iglesias | static CPUCRISState *cpu_crisv10_init (CPUState *env)
|
1199 | 40e9eddd | Edgar E. Iglesias | { |
1200 | 40e9eddd | Edgar E. Iglesias | int i;
|
1201 | 40e9eddd | Edgar E. Iglesias | |
1202 | 40e9eddd | Edgar E. Iglesias | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
1203 | 40e9eddd | Edgar E. Iglesias | cc_x = tcg_global_mem_new(TCG_AREG0, |
1204 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_x), "cc_x");
|
1205 | 40e9eddd | Edgar E. Iglesias | cc_src = tcg_global_mem_new(TCG_AREG0, |
1206 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_src), "cc_src");
|
1207 | 40e9eddd | Edgar E. Iglesias | cc_dest = tcg_global_mem_new(TCG_AREG0, |
1208 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_dest), |
1209 | 40e9eddd | Edgar E. Iglesias | "cc_dest");
|
1210 | 40e9eddd | Edgar E. Iglesias | cc_result = tcg_global_mem_new(TCG_AREG0, |
1211 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_result), |
1212 | 40e9eddd | Edgar E. Iglesias | "cc_result");
|
1213 | 40e9eddd | Edgar E. Iglesias | cc_op = tcg_global_mem_new(TCG_AREG0, |
1214 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_op), "cc_op");
|
1215 | 40e9eddd | Edgar E. Iglesias | cc_size = tcg_global_mem_new(TCG_AREG0, |
1216 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_size), |
1217 | 40e9eddd | Edgar E. Iglesias | "cc_size");
|
1218 | 40e9eddd | Edgar E. Iglesias | cc_mask = tcg_global_mem_new(TCG_AREG0, |
1219 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, cc_mask), |
1220 | 40e9eddd | Edgar E. Iglesias | "cc_mask");
|
1221 | 40e9eddd | Edgar E. Iglesias | |
1222 | 40e9eddd | Edgar E. Iglesias | env_pc = tcg_global_mem_new(TCG_AREG0, |
1223 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, pc), |
1224 | 40e9eddd | Edgar E. Iglesias | "pc");
|
1225 | 40e9eddd | Edgar E. Iglesias | env_btarget = tcg_global_mem_new(TCG_AREG0, |
1226 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, btarget), |
1227 | 40e9eddd | Edgar E. Iglesias | "btarget");
|
1228 | 40e9eddd | Edgar E. Iglesias | env_btaken = tcg_global_mem_new(TCG_AREG0, |
1229 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, btaken), |
1230 | 40e9eddd | Edgar E. Iglesias | "btaken");
|
1231 | 40e9eddd | Edgar E. Iglesias | for (i = 0; i < 16; i++) { |
1232 | 40e9eddd | Edgar E. Iglesias | cpu_R[i] = tcg_global_mem_new(TCG_AREG0, |
1233 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, regs[i]), |
1234 | 40e9eddd | Edgar E. Iglesias | regnames_v10[i]); |
1235 | 40e9eddd | Edgar E. Iglesias | } |
1236 | 40e9eddd | Edgar E. Iglesias | for (i = 0; i < 16; i++) { |
1237 | 40e9eddd | Edgar E. Iglesias | cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, |
1238 | 40e9eddd | Edgar E. Iglesias | offsetof(CPUState, pregs[i]), |
1239 | 40e9eddd | Edgar E. Iglesias | pregnames_v10[i]); |
1240 | 40e9eddd | Edgar E. Iglesias | } |
1241 | 40e9eddd | Edgar E. Iglesias | |
1242 | 40e9eddd | Edgar E. Iglesias | return env;
|
1243 | 40e9eddd | Edgar E. Iglesias | } |