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/*
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 *  CRIS mmu emulation.
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 *
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 *  Copyright (c) 2007 AXIS Communications AB
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 *  Written by Edgar E. Iglesias.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef CONFIG_USER_ONLY
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "config.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "exec-all.h"
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#ifdef DEBUG
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#define D(x) x
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#define D_LOG(...) qemu_log(__VA__ARGS__)
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#else
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#define D(x)
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#define D_LOG(...) do { } while (0)
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#endif
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void cris_mmu_init(CPUState *env)
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{
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        env->mmu_rand_lfsr = 0xcccc;
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}
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#define SR_POLYNOM 0x8805
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static inline unsigned int compute_polynom(unsigned int sr)
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{
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        unsigned int i;
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        unsigned int f;
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        f = 0;
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        for (i = 0; i < 16; i++)
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                f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
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        return f;
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}
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static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
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{
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        return (rw_gc_cfg & 12) != 0;
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}
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static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
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{
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        return (1 << seg) & rw_mm_cfg;
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}
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static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
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{
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        uint32_t base;
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        int i;
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        if (seg < 8)
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                base = env->sregs[SFR_RW_MM_KBASE_LO];
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        else
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                base = env->sregs[SFR_RW_MM_KBASE_HI];
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        i = seg & 7;
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        base >>= i * 4;
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        base &= 15;
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        base <<= 28;
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        return base;
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}
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/* Used by the tlb decoder.  */
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#define EXTRACT_FIELD(src, start, end) \
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            (((src) >> start) & ((1 << (end - start + 1)) - 1))
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static inline void set_field(uint32_t *dst, unsigned int val, 
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                             unsigned int offset, unsigned int width)
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{
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        uint32_t mask;
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        mask = (1 << width) - 1;
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        mask <<= offset;
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        val <<= offset;
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        val &= mask;
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        *dst &= ~(mask);
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        *dst |= val;
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}
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#ifdef DEBUG
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static void dump_tlb(CPUState *env, int mmu)
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{
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        int set;
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        int idx;
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        uint32_t hi, lo, tlb_vpn, tlb_pfn;
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        for (set = 0; set < 4; set++) {
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                for (idx = 0; idx < 16; idx++) {
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                        lo = env->tlbsets[mmu][set][idx].lo;
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                        hi = env->tlbsets[mmu][set][idx].hi;
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                        tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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                        tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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                        printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
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                                        set, idx, hi, lo, tlb_vpn, tlb_pfn);
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                }
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        }
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}
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#endif
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/* rw 0 = read, 1 = write, 2 = exec.  */
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static int cris_mmu_translate_page(struct cris_mmu_result *res,
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                                   CPUState *env, uint32_t vaddr,
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                                   int rw, int usermode)
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{
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        unsigned int vpage;
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        unsigned int idx;
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        uint32_t pid, lo, hi;
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        uint32_t tlb_vpn, tlb_pfn = 0;
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        int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
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        int cfg_v, cfg_k, cfg_w, cfg_x;        
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        int set, match = 0;
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        uint32_t r_cause;
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        uint32_t r_cfg;
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        int rwcause;
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        int mmu = 1; /* Data mmu is default.  */
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        int vect_base;
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        r_cause = env->sregs[SFR_R_MM_CAUSE];
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        r_cfg = env->sregs[SFR_RW_MM_CFG];
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        pid = env->pregs[PR_PID] & 0xff;
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        switch (rw) {
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                case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
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                case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
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                default:
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                case 0: rwcause = CRIS_MMU_ERR_READ; break;
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        }
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        /* I exception vectors 4 - 7, D 8 - 11.  */
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        vect_base = (mmu + 1) * 4;
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        vpage = vaddr >> 13;
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        /* We know the index which to check on each set.
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           Scan both I and D.  */
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#if 0
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        for (set = 0; set < 4; set++) {
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                for (idx = 0; idx < 16; idx++) {
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                        lo = env->tlbsets[mmu][set][idx].lo;
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                        hi = env->tlbsets[mmu][set][idx].hi;
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                        tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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                        tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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                        printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
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                                        set, idx, hi, lo, tlb_vpn, tlb_pfn);
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                }
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        }
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#endif
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        idx = vpage & 15;
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        for (set = 0; set < 4; set++)
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        {
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                lo = env->tlbsets[mmu][set][idx].lo;
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                hi = env->tlbsets[mmu][set][idx].hi;
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                tlb_vpn = hi >> 13;
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                tlb_pid = EXTRACT_FIELD(hi, 0, 7);
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                tlb_g  = EXTRACT_FIELD(lo, 4, 4);
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                D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", 
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                         mmu, set, idx, tlb_vpn, vpage, lo, hi);
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                if ((tlb_g || (tlb_pid == pid))
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                    && tlb_vpn == vpage) {
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                        match = 1;
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                        break;
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                }
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        }
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        res->bf_vec = vect_base;
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        if (match) {
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                cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
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                cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
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                cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
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                cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);
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                tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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                tlb_v = EXTRACT_FIELD(lo, 3, 3);
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                tlb_k = EXTRACT_FIELD(lo, 2, 2);
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                tlb_w = EXTRACT_FIELD(lo, 1, 1);
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                tlb_x = EXTRACT_FIELD(lo, 0, 0);
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                /*
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                set_exception_vector(0x04, i_mmu_refill);
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                set_exception_vector(0x05, i_mmu_invalid);
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                set_exception_vector(0x06, i_mmu_access);
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                set_exception_vector(0x07, i_mmu_execute);
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                set_exception_vector(0x08, d_mmu_refill);
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                set_exception_vector(0x09, d_mmu_invalid);
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                set_exception_vector(0x0a, d_mmu_access);
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                set_exception_vector(0x0b, d_mmu_write);
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                */
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                if (cfg_k && tlb_k && usermode) {
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                        D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
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                                  vaddr, lo, env->pc));
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                        match = 0;
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                        res->bf_vec = vect_base + 2;
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                } else if (rw == 1 && cfg_w && !tlb_w) {
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                        D(printf ("tlb: write protected %x lo=%x pc=%x\n", 
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                                  vaddr, lo, env->pc));
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                        match = 0;
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                        /* write accesses never go through the I mmu.  */
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                        res->bf_vec = vect_base + 3;
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                } else if (rw == 2 && cfg_x && !tlb_x) {
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                        D(printf ("tlb: exec protected %x lo=%x pc=%x\n", 
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                                 vaddr, lo, env->pc));
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                        match = 0;
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                        res->bf_vec = vect_base + 3;
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                } else if (cfg_v && !tlb_v) {
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                        D(printf ("tlb: invalid %x\n", vaddr));
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                        match = 0;
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                        res->bf_vec = vect_base + 1;
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                }
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                res->prot = 0;
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                if (match) {
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                        res->prot |= PAGE_READ;
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                        if (tlb_w)
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                                res->prot |= PAGE_WRITE;
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                        if (tlb_x)
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                                res->prot |= PAGE_EXEC;
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                }
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                else
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                        D(dump_tlb(env, mmu));
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        } else {
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                /* If refill, provide a randomized set.  */
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                set = env->mmu_rand_lfsr & 3;
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        }
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        if (!match) {
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                unsigned int f;
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                /* Update lfsr at every fault.  */
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                f = compute_polynom(env->mmu_rand_lfsr);
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                env->mmu_rand_lfsr >>= 1;
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                env->mmu_rand_lfsr |= (f << 15);
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                env->mmu_rand_lfsr &= 0xffff;
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                /* Compute index.  */
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                idx = vpage & 15;
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                /* Update RW_MM_TLB_SEL.  */
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                env->sregs[SFR_RW_MM_TLB_SEL] = 0;
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                set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
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                set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
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                /* Update RW_MM_CAUSE.  */
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                set_field(&r_cause, rwcause, 8, 2);
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                set_field(&r_cause, vpage, 13, 19);
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                set_field(&r_cause, pid, 0, 8);
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                env->sregs[SFR_R_MM_CAUSE] = r_cause;
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                D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
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        }
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        D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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                  " %x cause=%x sel=%x sp=%x %x %x\n",
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                  __func__, rw, match, env->pc,
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                  vaddr, vpage,
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                  tlb_vpn, tlb_pfn, tlb_pid, 
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                  pid,
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                  r_cause,
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                  env->sregs[SFR_RW_MM_TLB_SEL],
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                  env->regs[R_SP], env->pregs[PR_USP], env->ksp));
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        res->phy = tlb_pfn << TARGET_PAGE_BITS;
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        return !match;
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}
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void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
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{
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        target_ulong vaddr;
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        unsigned int idx;
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        uint32_t lo, hi;
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        uint32_t tlb_vpn;
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        int tlb_pid, tlb_g, tlb_v;
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        unsigned int set;
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        unsigned int mmu;
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        pid &= 0xff;
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        for (mmu = 0; mmu < 2; mmu++) {
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                for (set = 0; set < 4; set++)
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                {
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                        for (idx = 0; idx < 16; idx++) {
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                                lo = env->tlbsets[mmu][set][idx].lo;
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                                hi = env->tlbsets[mmu][set][idx].hi;
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                                tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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                                tlb_pid = EXTRACT_FIELD(hi, 0, 7);
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                                tlb_g  = EXTRACT_FIELD(lo, 4, 4);
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                                tlb_v = EXTRACT_FIELD(lo, 3, 3);
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                                if (tlb_v && !tlb_g && (tlb_pid == pid)) {
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                                        vaddr = tlb_vpn << TARGET_PAGE_BITS;
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                                        D_LOG("flush pid=%x vaddr=%x\n", 
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                                                  pid, vaddr);
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                                        tlb_flush_page(env, vaddr);
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                                }
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                        }
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                }
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        }
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}
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int cris_mmu_translate(struct cris_mmu_result *res,
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                       CPUState *env, uint32_t vaddr,
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                       int rw, int mmu_idx)
329
{
330
        int seg;
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        int miss = 0;
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        int is_user = mmu_idx == MMU_USER_IDX;
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        uint32_t old_srs;
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        old_srs= env->pregs[PR_SRS];
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        /* rw == 2 means exec, map the access to the insn mmu.  */
338
        env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
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340
        if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
341
                res->phy = vaddr;
342
                res->prot = PAGE_BITS;
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                goto done;
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        }
345

    
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        seg = vaddr >> 28;
347
        if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
348
        {
349
                uint32_t base;
350

    
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                miss = 0;
352
                base = cris_mmu_translate_seg(env, seg);
353
                res->phy = base | (0x0fffffff & vaddr);
354
                res->prot = PAGE_BITS;
355
        }
356
        else
357
                miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
358
  done:
359
        env->pregs[PR_SRS] = old_srs;
360
        return miss;
361
}
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#endif