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/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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//#define HARD_DEBUG_PPC_IO
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//#define DEBUG_PPC_IO
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1 |
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#define BIOS_FILENAME "ppc_rom.bin" |
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#define KERNEL_LOAD_ADDR 0x01000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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extern int loglevel; |
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extern FILE *logfile;
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#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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#define DEBUG_PPC_IO
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#endif
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#if defined (HARD_DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_IOPORT) { \
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fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
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} else { \
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printf("%s : " fmt, __func__ , ##args); \ |
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} \ |
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} while (0) |
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#elif defined (DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_IOPORT) { \
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fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
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} \ |
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} while (0) |
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#else
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#define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
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#endif
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
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static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
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static const int ide_irq[2] = { 13, 13 }; |
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|
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#define NE2000_NB_MAX 6 |
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
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//static PITState *pit;
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000 |
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|
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/* Speaker port 0x61 */
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int speaker_data_on;
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int dummy_refresh_clock;
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static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
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{
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#if 0
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speaker_data_on = (val >> 1) & 1;
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pit_set_gate(pit, 2, val & 1);
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#endif
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} |
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static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
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{
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#if 0
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int out;
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out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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dummy_refresh_clock ^= 1;
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return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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(dummy_refresh_clock << 4);
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#endif
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return 0; |
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} |
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|
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/* PCI intack register */
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/* Read-only register (?) */
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static void _PPC_intack_write (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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// printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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} |
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static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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if (addr == 0xBFFFFFF0) |
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retval = pic_intack_read(isa_pic); |
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// printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
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return retval;
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} |
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static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
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{
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return _PPC_intack_read(addr);
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} |
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static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap16(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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} |
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static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap32(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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} |
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static CPUWriteMemoryFunc *PPC_intack_write[] = {
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&_PPC_intack_write, |
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&_PPC_intack_write, |
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&_PPC_intack_write, |
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}; |
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static CPUReadMemoryFunc *PPC_intack_read[] = {
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&PPC_intack_readb, |
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&PPC_intack_readw, |
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&PPC_intack_readl, |
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}; |
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
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}
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static void PPC_XCSR_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
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} |
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static void PPC_XCSR_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value); |
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#endif
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printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
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} |
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static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
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{
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uint32_t retval = 0;
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printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
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return retval;
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} |
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static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
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{
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uint32_t retval = 0;
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printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap16(retval); |
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#endif
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return retval;
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} |
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static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
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{
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uint32_t retval = 0;
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printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap32(retval); |
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#endif
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return retval;
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} |
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static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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&PPC_XCSR_writeb, |
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&PPC_XCSR_writew, |
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&PPC_XCSR_writel, |
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}; |
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static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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&PPC_XCSR_readb, |
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&PPC_XCSR_readw, |
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&PPC_XCSR_readl, |
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}; |
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#endif
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|
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t { |
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qemu_irq reset_irq; |
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m48t59_t *nvram; |
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uint8_t state; |
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uint8_t syscontrol; |
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uint8_t fake_io[2];
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int contiguous_map;
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int endian;
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} sysctrl_t; |
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enum {
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STATE_HARDFILE = 0x01,
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}; |
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static sysctrl_t *sysctrl;
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static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
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{
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
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sysctrl->fake_io[addr - 0x0398] = val;
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} |
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static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
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{
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, |
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sysctrl->fake_io[addr - 0x0398]);
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return sysctrl->fake_io[addr - 0x0398]; |
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} |
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|
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
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{
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sysctrl_t *sysctrl = opaque; |
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|
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PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
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switch (addr) {
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case 0x0092: |
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) { |
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qemu_irq_raise(sysctrl->reset_irq); |
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} else {
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qemu_irq_lower(sysctrl->reset_irq); |
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} |
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/* Check LE mode */
|
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if (val & 0x02) { |
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sysctrl->endian = 1;
|
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} else {
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sysctrl->endian = 0;
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} |
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break;
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case 0x0800: |
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802: |
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803: |
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/* Motorola base module status register : read-only */
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break;
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case 0x0808: |
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/* Hardfile light register */
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if (val & 1) |
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sysctrl->state |= STATE_HARDFILE; |
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else
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sysctrl->state &= ~STATE_HARDFILE; |
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break;
|
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case 0x0810: |
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL) |
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m48t59_toggle_lock(sysctrl->nvram, 1);
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break;
|
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case 0x0812: |
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL) |
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m48t59_toggle_lock(sysctrl->nvram, 2);
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break;
|
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case 0x0814: |
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/* L2 invalidate register */
|
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C: |
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
|
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case 0x0850: |
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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break;
|
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default:
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printf("ERROR: unaffected IO port write: %04lx => %02x\n",
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(long)addr, val);
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break;
|
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} |
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} |
| 352 |
|
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
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{
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sysctrl_t *sysctrl = opaque; |
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uint32_t retval = 0xFF;
|
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|
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switch (addr) {
|
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case 0x0092: |
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/* Special port 92 */
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retval = 0x00;
|
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break;
|
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case 0x0800: |
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/* Motorola CPU configuration register */
|
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retval = 0xEF; /* MPC750 */ |
| 366 |
break;
|
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case 0x0802: |
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/* Motorola Base module feature register */
|
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
| 370 |
break;
|
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case 0x0803: |
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/* Motorola base module status register */
|
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retval = 0xE0; /* Standard MPC750 */ |
| 374 |
break;
|
| 375 |
case 0x080C: |
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/* Equipment present register:
|
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* no L2 cache
|
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* no upgrade processor
|
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* no cards in PCI slots
|
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* SCSI fuse is bad
|
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*/
|
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retval = 0x3C;
|
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break;
|
| 384 |
case 0x0810: |
| 385 |
/* Motorola base module extended feature register */
|
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
| 387 |
break;
|
| 388 |
case 0x0814: |
| 389 |
/* L2 invalidate: don't care */
|
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break;
|
| 391 |
case 0x0818: |
| 392 |
/* Keylock */
|
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retval = 0x00;
|
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break;
|
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case 0x081C: |
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/* system control register
|
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* 7 - 6 / 1 - 0: L2 cache enable
|
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*/
|
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retval = sysctrl->syscontrol; |
| 400 |
break;
|
| 401 |
case 0x0823: |
| 402 |
/* */
|
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retval = 0x03; /* no L2 cache */ |
| 404 |
break;
|
| 405 |
case 0x0850: |
| 406 |
/* I/O map type register */
|
| 407 |
retval = sysctrl->contiguous_map; |
| 408 |
break;
|
| 409 |
default:
|
| 410 |
printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); |
| 411 |
break;
|
| 412 |
} |
| 413 |
PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval); |
| 414 |
|
| 415 |
return retval;
|
| 416 |
} |
| 417 |
|
| 418 |
static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
|
| 419 |
target_phys_addr_t |
| 420 |
addr) |
| 421 |
{
|
| 422 |
if (sysctrl->contiguous_map == 0) { |
| 423 |
/* 64 KB contiguous space for IOs */
|
| 424 |
addr &= 0xFFFF;
|
| 425 |
} else {
|
| 426 |
/* 8 MB non-contiguous space for IOs */
|
| 427 |
addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
| 428 |
} |
| 429 |
|
| 430 |
return addr;
|
| 431 |
} |
| 432 |
|
| 433 |
static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
| 434 |
uint32_t value) |
| 435 |
{
|
| 436 |
sysctrl_t *sysctrl = opaque; |
| 437 |
|
| 438 |
addr = prep_IO_address(sysctrl, addr); |
| 439 |
cpu_outb(NULL, addr, value);
|
| 440 |
} |
| 441 |
|
| 442 |
static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
| 443 |
{
|
| 444 |
sysctrl_t *sysctrl = opaque; |
| 445 |
uint32_t ret; |
| 446 |
|
| 447 |
addr = prep_IO_address(sysctrl, addr); |
| 448 |
ret = cpu_inb(NULL, addr);
|
| 449 |
|
| 450 |
return ret;
|
| 451 |
} |
| 452 |
|
| 453 |
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
| 454 |
uint32_t value) |
| 455 |
{
|
| 456 |
sysctrl_t *sysctrl = opaque; |
| 457 |
|
| 458 |
addr = prep_IO_address(sysctrl, addr); |
| 459 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 460 |
value = bswap16(value); |
| 461 |
#endif
|
| 462 |
PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); |
| 463 |
cpu_outw(NULL, addr, value);
|
| 464 |
} |
| 465 |
|
| 466 |
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
| 467 |
{
|
| 468 |
sysctrl_t *sysctrl = opaque; |
| 469 |
uint32_t ret; |
| 470 |
|
| 471 |
addr = prep_IO_address(sysctrl, addr); |
| 472 |
ret = cpu_inw(NULL, addr);
|
| 473 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 474 |
ret = bswap16(ret); |
| 475 |
#endif
|
| 476 |
PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); |
| 477 |
|
| 478 |
return ret;
|
| 479 |
} |
| 480 |
|
| 481 |
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
| 482 |
uint32_t value) |
| 483 |
{
|
| 484 |
sysctrl_t *sysctrl = opaque; |
| 485 |
|
| 486 |
addr = prep_IO_address(sysctrl, addr); |
| 487 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 488 |
value = bswap32(value); |
| 489 |
#endif
|
| 490 |
PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); |
| 491 |
cpu_outl(NULL, addr, value);
|
| 492 |
} |
| 493 |
|
| 494 |
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
| 495 |
{
|
| 496 |
sysctrl_t *sysctrl = opaque; |
| 497 |
uint32_t ret; |
| 498 |
|
| 499 |
addr = prep_IO_address(sysctrl, addr); |
| 500 |
ret = cpu_inl(NULL, addr);
|
| 501 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 502 |
ret = bswap32(ret); |
| 503 |
#endif
|
| 504 |
PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); |
| 505 |
|
| 506 |
return ret;
|
| 507 |
} |
| 508 |
|
| 509 |
CPUWriteMemoryFunc *PPC_prep_io_write[] = {
|
| 510 |
&PPC_prep_io_writeb, |
| 511 |
&PPC_prep_io_writew, |
| 512 |
&PPC_prep_io_writel, |
| 513 |
}; |
| 514 |
|
| 515 |
CPUReadMemoryFunc *PPC_prep_io_read[] = {
|
| 516 |
&PPC_prep_io_readb, |
| 517 |
&PPC_prep_io_readw, |
| 518 |
&PPC_prep_io_readl, |
| 519 |
}; |
| 520 |
|
| 521 |
#define NVRAM_SIZE 0x2000 |
| 522 |
|
| 523 |
/* PowerPC PREP hardware initialisation */
|
| 524 |
static void ppc_prep_init (int ram_size, int vga_ram_size, |
| 525 |
const char *boot_device, |
| 526 |
DisplayState *ds, const char **fd_filename, |
| 527 |
int snapshot, const char *kernel_filename, |
| 528 |
const char *kernel_cmdline, |
| 529 |
const char *initrd_filename, |
| 530 |
const char *cpu_model) |
| 531 |
{
|
| 532 |
CPUState *env = NULL, *envs[MAX_CPUS];
|
| 533 |
char buf[1024]; |
| 534 |
nvram_t nvram; |
| 535 |
m48t59_t *m48t59; |
| 536 |
int PPC_io_memory;
|
| 537 |
int linux_boot, i, nb_nics1, bios_size;
|
| 538 |
unsigned long bios_offset; |
| 539 |
uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
| 540 |
PCIBus *pci_bus; |
| 541 |
qemu_irq *i8259; |
| 542 |
int ppc_boot_device;
|
| 543 |
|
| 544 |
sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
| 545 |
if (sysctrl == NULL) |
| 546 |
return;
|
| 547 |
|
| 548 |
linux_boot = (kernel_filename != NULL);
|
| 549 |
|
| 550 |
/* init CPUs */
|
| 551 |
if (cpu_model == NULL) |
| 552 |
cpu_model = "default";
|
| 553 |
for (i = 0; i < smp_cpus; i++) { |
| 554 |
env = cpu_init(cpu_model); |
| 555 |
if (!env) {
|
| 556 |
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
| 557 |
exit(1);
|
| 558 |
} |
| 559 |
/* Set time-base frequency to 100 Mhz */
|
| 560 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 561 |
qemu_register_reset(&cpu_ppc_reset, env); |
| 562 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
| 563 |
envs[i] = env; |
| 564 |
} |
| 565 |
|
| 566 |
/* allocate RAM */
|
| 567 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
| 568 |
|
| 569 |
/* allocate and load BIOS */
|
| 570 |
bios_offset = ram_size + vga_ram_size; |
| 571 |
if (bios_name == NULL) |
| 572 |
bios_name = BIOS_FILENAME; |
| 573 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
| 574 |
bios_size = load_image(buf, phys_ram_base + bios_offset); |
| 575 |
if (bios_size < 0 || bios_size > BIOS_SIZE) { |
| 576 |
cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
| 577 |
exit(1);
|
| 578 |
} |
| 579 |
if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
| 580 |
cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
|
| 581 |
} |
| 582 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 583 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
| 584 |
bios_size, bios_offset | IO_MEM_ROM); |
| 585 |
|
| 586 |
if (linux_boot) {
|
| 587 |
kernel_base = KERNEL_LOAD_ADDR; |
| 588 |
/* now we can load the kernel */
|
| 589 |
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
| 590 |
if (kernel_size < 0) { |
| 591 |
cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
| 592 |
kernel_filename); |
| 593 |
exit(1);
|
| 594 |
} |
| 595 |
/* load initrd */
|
| 596 |
if (initrd_filename) {
|
| 597 |
initrd_base = INITRD_LOAD_ADDR; |
| 598 |
initrd_size = load_image(initrd_filename, |
| 599 |
phys_ram_base + initrd_base); |
| 600 |
if (initrd_size < 0) { |
| 601 |
cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
| 602 |
initrd_filename); |
| 603 |
exit(1);
|
| 604 |
} |
| 605 |
} else {
|
| 606 |
initrd_base = 0;
|
| 607 |
initrd_size = 0;
|
| 608 |
} |
| 609 |
ppc_boot_device = 'm';
|
| 610 |
} else {
|
| 611 |
kernel_base = 0;
|
| 612 |
kernel_size = 0;
|
| 613 |
initrd_base = 0;
|
| 614 |
initrd_size = 0;
|
| 615 |
ppc_boot_device = '\0';
|
| 616 |
/* For now, OHW cannot boot from the network. */
|
| 617 |
for (i = 0; boot_device[i] != '\0'; i++) { |
| 618 |
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
| 619 |
ppc_boot_device = boot_device[i]; |
| 620 |
break;
|
| 621 |
} |
| 622 |
} |
| 623 |
if (ppc_boot_device == '\0') { |
| 624 |
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
| 625 |
exit(1);
|
| 626 |
} |
| 627 |
} |
| 628 |
|
| 629 |
isa_mem_base = 0xc0000000;
|
| 630 |
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
| 631 |
cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
|
| 632 |
exit(1);
|
| 633 |
} |
| 634 |
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
| 635 |
pci_bus = pci_prep_init(i8259); |
| 636 |
// pci_bus = i440fx_init();
|
| 637 |
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
| 638 |
PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
|
| 639 |
PPC_prep_io_write, sysctrl); |
| 640 |
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
| 641 |
|
| 642 |
/* init basic PC hardware */
|
| 643 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
| 644 |
vga_ram_size, 0, 0); |
| 645 |
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
| 646 |
// pit = pit_init(0x40, i8259[0]);
|
| 647 |
rtc_init(0x70, i8259[8]); |
| 648 |
|
| 649 |
serial_init(0x3f8, i8259[4], serial_hds[0]); |
| 650 |
nb_nics1 = nb_nics; |
| 651 |
if (nb_nics1 > NE2000_NB_MAX)
|
| 652 |
nb_nics1 = NE2000_NB_MAX; |
| 653 |
for(i = 0; i < nb_nics1; i++) { |
| 654 |
if (nd_table[i].model == NULL |
| 655 |
|| strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
| 656 |
isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
| 657 |
} else {
|
| 658 |
pci_nic_init(pci_bus, &nd_table[i], -1);
|
| 659 |
} |
| 660 |
} |
| 661 |
|
| 662 |
for(i = 0; i < 2; i++) { |
| 663 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
| 664 |
bs_table[2 * i], bs_table[2 * i + 1]); |
| 665 |
} |
| 666 |
i8042_init(i8259[1], i8259[12], 0x60); |
| 667 |
DMA_init(1);
|
| 668 |
// AUD_init();
|
| 669 |
// SB16_init();
|
| 670 |
|
| 671 |
fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); |
| 672 |
|
| 673 |
/* Register speaker port */
|
| 674 |
register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
| 675 |
register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
| 676 |
/* Register fake IO ports for PREP */
|
| 677 |
sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
| 678 |
register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
| 679 |
register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
| 680 |
/* System control ports */
|
| 681 |
register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
| 682 |
register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
| 683 |
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
| 684 |
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
| 685 |
/* PCI intack location */
|
| 686 |
PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
| 687 |
PPC_intack_write, NULL);
|
| 688 |
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
| 689 |
/* PowerPC control and status register group */
|
| 690 |
#if 0
|
| 691 |
PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
|
| 692 |
NULL);
|
| 693 |
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
| 694 |
#endif
|
| 695 |
|
| 696 |
if (usb_enabled) {
|
| 697 |
usb_ohci_init_pci(pci_bus, 3, -1); |
| 698 |
} |
| 699 |
|
| 700 |
m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
| 701 |
if (m48t59 == NULL) |
| 702 |
return;
|
| 703 |
sysctrl->nvram = m48t59; |
| 704 |
|
| 705 |
/* Initialise NVRAM */
|
| 706 |
nvram.opaque = m48t59; |
| 707 |
nvram.read_fn = &m48t59_read; |
| 708 |
nvram.write_fn = &m48t59_write; |
| 709 |
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
| 710 |
kernel_base, kernel_size, |
| 711 |
kernel_cmdline, |
| 712 |
initrd_base, initrd_size, |
| 713 |
/* XXX: need an option to load a NVRAM image */
|
| 714 |
0,
|
| 715 |
graphic_width, graphic_height, graphic_depth); |
| 716 |
|
| 717 |
/* Special port to get debug messages from Open-Firmware */
|
| 718 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
| 719 |
} |
| 720 |
|
| 721 |
QEMUMachine prep_machine = {
|
| 722 |
"prep",
|
| 723 |
"PowerPC PREP platform",
|
| 724 |
ppc_prep_init, |
| 725 |
}; |