Revision 0db1b20e
| b/target-ppc/translate.c | ||
|---|---|---|
| 478 | 478 |
PPC_DCRUX = 0x0000040000000000ULL, |
| 479 | 479 |
/* New floating-point extensions (PowerPC 2.0x) */ |
| 480 | 480 |
PPC_FLOAT_EXT = 0x0000080000000000ULL, |
| 481 |
/* New wait instruction (PowerPC 2.0x) */ |
|
| 482 |
PPC_WAIT = 0x0000100000000000ULL, |
|
| 481 | 483 |
}; |
| 482 | 484 |
|
| 483 | 485 |
/*****************************************************************************/ |
| ... | ... | |
| 2463 | 2465 |
|
| 2464 | 2466 |
/*** Memory synchronisation ***/ |
| 2465 | 2467 |
/* eieio */ |
| 2466 |
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM_EIEIO)
|
|
| 2468 |
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
|
|
| 2467 | 2469 |
{
|
| 2468 | 2470 |
} |
| 2469 | 2471 |
|
| 2470 | 2472 |
/* isync */ |
| 2471 |
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FF0801, PPC_MEM)
|
|
| 2473 |
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
|
|
| 2472 | 2474 |
{
|
| 2473 | 2475 |
GEN_STOP(ctx); |
| 2474 | 2476 |
} |
| ... | ... | |
| 2610 | 2612 |
#endif /* defined(TARGET_PPC64) */ |
| 2611 | 2613 |
|
| 2612 | 2614 |
/* sync */ |
| 2613 |
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03CF0801, PPC_MEM_SYNC)
|
|
| 2615 |
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03BFF801, PPC_MEM_SYNC)
|
|
| 2614 | 2616 |
{
|
| 2615 | 2617 |
} |
| 2616 | 2618 |
|
| 2619 |
/* wait */ |
|
| 2620 |
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT) |
|
| 2621 |
{
|
|
| 2622 |
/* Stop translation, as the CPU is supposed to sleep from now */ |
|
| 2623 |
/* XXX: TODO: handle this idle CPU case */ |
|
| 2624 |
GEN_STOP(ctx); |
|
| 2625 |
} |
|
| 2626 |
|
|
| 2617 | 2627 |
/*** Floating-point load ***/ |
| 2618 | 2628 |
#define GEN_LDF(width, opc, type) \ |
| 2619 | 2629 |
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
| ... | ... | |
| 3328 | 3338 |
* We just have to flush tb while invalidating instruction cache lines... |
| 3329 | 3339 |
*/ |
| 3330 | 3340 |
/* dcbf */ |
| 3331 |
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
|
|
| 3341 |
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
|
|
| 3332 | 3342 |
{
|
| 3333 | 3343 |
gen_addr_reg_index(ctx); |
| 3334 | 3344 |
op_ldst(lbz); |
| ... | ... | |
| 3360 | 3370 |
} |
| 3361 | 3371 |
|
| 3362 | 3372 |
/* dcbt */ |
| 3363 |
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
|
|
| 3373 |
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
|
|
| 3364 | 3374 |
{
|
| 3375 |
/* interpreted as no-op */ |
|
| 3365 | 3376 |
/* XXX: specification say this is treated as a load by the MMU |
| 3366 | 3377 |
* but does not generate any exception |
| 3367 | 3378 |
*/ |
| 3368 | 3379 |
} |
| 3369 | 3380 |
|
| 3370 | 3381 |
/* dcbtst */ |
| 3371 |
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
|
|
| 3382 |
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
|
|
| 3372 | 3383 |
{
|
| 3384 |
/* interpreted as no-op */ |
|
| 3373 | 3385 |
/* XXX: specification say this is treated as a load by the MMU |
| 3374 | 3386 |
* but does not generate any exception |
| 3375 | 3387 |
*/ |
| ... | ... | |
| 3468 | 3480 |
/* dcba */ |
| 3469 | 3481 |
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA) |
| 3470 | 3482 |
{
|
| 3483 |
/* interpreted as no-op */ |
|
| 3484 |
/* XXX: specification say this is treated as a store by the MMU |
|
| 3485 |
* but does not generate any exception |
|
| 3486 |
*/ |
|
| 3471 | 3487 |
} |
| 3472 | 3488 |
|
| 3473 | 3489 |
/*** Segment register manipulation ***/ |
| ... | ... | |
| 5012 | 5028 |
} |
| 5013 | 5029 |
|
| 5014 | 5030 |
/* msync replaces sync on 440 */ |
| 5015 |
GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_BOOKE)
|
|
| 5031 |
GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
|
|
| 5016 | 5032 |
{
|
| 5017 | 5033 |
/* interpreted as no-op */ |
| 5018 | 5034 |
} |
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