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1 | 9df217a3 | bellard | /*
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2 | 9df217a3 | bellard | * KQEMU support
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3 | 9df217a3 | bellard | *
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4 | 9df217a3 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 9df217a3 | bellard | *
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6 | 9df217a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | 9df217a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 9df217a3 | bellard | * License as published by the Free Software Foundation; either
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9 | 9df217a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 9df217a3 | bellard | *
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11 | 9df217a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 9df217a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9df217a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 9df217a3 | bellard | * Lesser General Public License for more details.
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15 | 9df217a3 | bellard | *
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16 | 9df217a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 9df217a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | 9df217a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 9df217a3 | bellard | */
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20 | 9df217a3 | bellard | #include "config.h" |
21 | 9df217a3 | bellard | #ifdef _WIN32
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22 | 9df217a3 | bellard | #include <windows.h> |
23 | 6e4255f6 | bellard | #include <winioctl.h> |
24 | 9df217a3 | bellard | #else
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25 | 9df217a3 | bellard | #include <sys/types.h> |
26 | 9df217a3 | bellard | #include <sys/mman.h> |
27 | 6e4255f6 | bellard | #include <sys/ioctl.h> |
28 | 9df217a3 | bellard | #endif
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29 | 9df217a3 | bellard | #include <stdlib.h> |
30 | 9df217a3 | bellard | #include <stdio.h> |
31 | 9df217a3 | bellard | #include <stdarg.h> |
32 | 9df217a3 | bellard | #include <string.h> |
33 | 9df217a3 | bellard | #include <errno.h> |
34 | 9df217a3 | bellard | #include <unistd.h> |
35 | 9df217a3 | bellard | #include <inttypes.h> |
36 | 9df217a3 | bellard | |
37 | 9df217a3 | bellard | #include "cpu.h" |
38 | 9df217a3 | bellard | #include "exec-all.h" |
39 | 9df217a3 | bellard | |
40 | 9df217a3 | bellard | #ifdef USE_KQEMU
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41 | 9df217a3 | bellard | |
42 | 9df217a3 | bellard | #define DEBUG
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43 | aa062973 | bellard | //#define PROFILE
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44 | 9df217a3 | bellard | |
45 | 9df217a3 | bellard | #include <unistd.h> |
46 | 9df217a3 | bellard | #include <fcntl.h> |
47 | b88a3832 | bellard | #include "kqemu.h" |
48 | 9df217a3 | bellard | |
49 | c28e951f | bellard | /* compatibility stuff */
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50 | c28e951f | bellard | #ifndef KQEMU_RET_SYSCALL
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51 | c28e951f | bellard | #define KQEMU_RET_SYSCALL 0x0300 /* syscall insn */ |
52 | c28e951f | bellard | #endif
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53 | aa062973 | bellard | #ifndef KQEMU_MAX_RAM_PAGES_TO_UPDATE
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54 | aa062973 | bellard | #define KQEMU_MAX_RAM_PAGES_TO_UPDATE 512 |
55 | aa062973 | bellard | #define KQEMU_RAM_PAGES_UPDATE_ALL (KQEMU_MAX_RAM_PAGES_TO_UPDATE + 1) |
56 | aa062973 | bellard | #endif
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57 | f32fc648 | bellard | #ifndef KQEMU_MAX_MODIFIED_RAM_PAGES
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58 | f32fc648 | bellard | #define KQEMU_MAX_MODIFIED_RAM_PAGES 512 |
59 | f32fc648 | bellard | #endif
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60 | c28e951f | bellard | |
61 | 6e4255f6 | bellard | #ifdef _WIN32
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62 | 6e4255f6 | bellard | #define KQEMU_DEVICE "\\\\.\\kqemu" |
63 | 6e4255f6 | bellard | #else
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64 | 9df217a3 | bellard | #define KQEMU_DEVICE "/dev/kqemu" |
65 | 6e4255f6 | bellard | #endif
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66 | 6e4255f6 | bellard | |
67 | 6e4255f6 | bellard | #ifdef _WIN32
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68 | 6e4255f6 | bellard | #define KQEMU_INVALID_FD INVALID_HANDLE_VALUE
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69 | 6e4255f6 | bellard | HANDLE kqemu_fd = KQEMU_INVALID_FD; |
70 | 6e4255f6 | bellard | #define kqemu_closefd(x) CloseHandle(x)
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71 | 6e4255f6 | bellard | #else
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72 | 6e4255f6 | bellard | #define KQEMU_INVALID_FD -1 |
73 | 6e4255f6 | bellard | int kqemu_fd = KQEMU_INVALID_FD;
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74 | 6e4255f6 | bellard | #define kqemu_closefd(x) close(x)
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75 | 6e4255f6 | bellard | #endif
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76 | 9df217a3 | bellard | |
77 | f32fc648 | bellard | /* 0 = not allowed
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78 | f32fc648 | bellard | 1 = user kqemu
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79 | f32fc648 | bellard | 2 = kernel kqemu
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80 | f32fc648 | bellard | */
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81 | 9df217a3 | bellard | int kqemu_allowed = 1; |
82 | 9df217a3 | bellard | unsigned long *pages_to_flush; |
83 | 9df217a3 | bellard | unsigned int nb_pages_to_flush; |
84 | aa062973 | bellard | unsigned long *ram_pages_to_update; |
85 | aa062973 | bellard | unsigned int nb_ram_pages_to_update; |
86 | f32fc648 | bellard | unsigned long *modified_ram_pages; |
87 | f32fc648 | bellard | unsigned int nb_modified_ram_pages; |
88 | f32fc648 | bellard | uint8_t *modified_ram_pages_table; |
89 | 9df217a3 | bellard | extern uint32_t **l1_phys_map;
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90 | 9df217a3 | bellard | |
91 | 9df217a3 | bellard | #define cpuid(index, eax, ebx, ecx, edx) \
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92 | 9df217a3 | bellard | asm volatile ("cpuid" \ |
93 | 9df217a3 | bellard | : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ |
94 | 9df217a3 | bellard | : "0" (index))
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95 | 9df217a3 | bellard | |
96 | c28e951f | bellard | #ifdef __x86_64__
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97 | c28e951f | bellard | static int is_cpuid_supported(void) |
98 | c28e951f | bellard | { |
99 | c28e951f | bellard | return 1; |
100 | c28e951f | bellard | } |
101 | c28e951f | bellard | #else
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102 | 9df217a3 | bellard | static int is_cpuid_supported(void) |
103 | 9df217a3 | bellard | { |
104 | 9df217a3 | bellard | int v0, v1;
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105 | 9df217a3 | bellard | asm volatile ("pushf\n" |
106 | 9df217a3 | bellard | "popl %0\n"
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107 | 9df217a3 | bellard | "movl %0, %1\n"
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108 | 9df217a3 | bellard | "xorl $0x00200000, %0\n"
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109 | 9df217a3 | bellard | "pushl %0\n"
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110 | 9df217a3 | bellard | "popf\n"
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111 | 9df217a3 | bellard | "pushf\n"
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112 | 9df217a3 | bellard | "popl %0\n"
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113 | 9df217a3 | bellard | : "=a" (v0), "=d" (v1) |
114 | 9df217a3 | bellard | : |
115 | 9df217a3 | bellard | : "cc");
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116 | 9df217a3 | bellard | return (v0 != v1);
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117 | 9df217a3 | bellard | } |
118 | c28e951f | bellard | #endif
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119 | 9df217a3 | bellard | |
120 | 9df217a3 | bellard | static void kqemu_update_cpuid(CPUState *env) |
121 | 9df217a3 | bellard | { |
122 | 0de6bb73 | bellard | int critical_features_mask, features, ext_features, ext_features_mask;
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123 | 9df217a3 | bellard | uint32_t eax, ebx, ecx, edx; |
124 | 9df217a3 | bellard | |
125 | 9df217a3 | bellard | /* the following features are kept identical on the host and
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126 | 9df217a3 | bellard | target cpus because they are important for user code. Strictly
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127 | 9df217a3 | bellard | speaking, only SSE really matters because the OS must support
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128 | 9df217a3 | bellard | it if the user code uses it. */
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129 | 9df217a3 | bellard | critical_features_mask = |
130 | 9df217a3 | bellard | CPUID_CMOV | CPUID_CX8 | |
131 | 9df217a3 | bellard | CPUID_FXSR | CPUID_MMX | CPUID_SSE | |
132 | ca0d1734 | bellard | CPUID_SSE2 | CPUID_SEP; |
133 | 0de6bb73 | bellard | ext_features_mask = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR; |
134 | 9df217a3 | bellard | if (!is_cpuid_supported()) {
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135 | 9df217a3 | bellard | features = 0;
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136 | 0de6bb73 | bellard | ext_features = 0;
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137 | 9df217a3 | bellard | } else {
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138 | 9df217a3 | bellard | cpuid(1, eax, ebx, ecx, edx);
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139 | 9df217a3 | bellard | features = edx; |
140 | 0de6bb73 | bellard | ext_features = ecx; |
141 | 9df217a3 | bellard | } |
142 | ca0d1734 | bellard | #ifdef __x86_64__
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143 | ca0d1734 | bellard | /* NOTE: on x86_64 CPUs, SYSENTER is not supported in
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144 | ca0d1734 | bellard | compatibility mode, so in order to have the best performances
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145 | ca0d1734 | bellard | it is better not to use it */
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146 | ca0d1734 | bellard | features &= ~CPUID_SEP; |
147 | ca0d1734 | bellard | #endif
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148 | 9df217a3 | bellard | env->cpuid_features = (env->cpuid_features & ~critical_features_mask) | |
149 | 9df217a3 | bellard | (features & critical_features_mask); |
150 | 0de6bb73 | bellard | env->cpuid_ext_features = (env->cpuid_ext_features & ~ext_features_mask) | |
151 | 0de6bb73 | bellard | (ext_features & ext_features_mask); |
152 | 9df217a3 | bellard | /* XXX: we could update more of the target CPUID state so that the
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153 | 9df217a3 | bellard | non accelerated code sees exactly the same CPU features as the
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154 | 9df217a3 | bellard | accelerated code */
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155 | 9df217a3 | bellard | } |
156 | 9df217a3 | bellard | |
157 | 9df217a3 | bellard | int kqemu_init(CPUState *env)
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158 | 9df217a3 | bellard | { |
159 | 9df217a3 | bellard | struct kqemu_init init;
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160 | 9df217a3 | bellard | int ret, version;
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161 | 6e4255f6 | bellard | #ifdef _WIN32
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162 | 6e4255f6 | bellard | DWORD temp; |
163 | 6e4255f6 | bellard | #endif
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164 | 9df217a3 | bellard | |
165 | 9df217a3 | bellard | if (!kqemu_allowed)
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166 | 9df217a3 | bellard | return -1; |
167 | 9df217a3 | bellard | |
168 | 6e4255f6 | bellard | #ifdef _WIN32
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169 | 6e4255f6 | bellard | kqemu_fd = CreateFile(KQEMU_DEVICE, GENERIC_WRITE | GENERIC_READ, |
170 | 6e4255f6 | bellard | FILE_SHARE_READ | FILE_SHARE_WRITE, |
171 | 6e4255f6 | bellard | NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL,
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172 | 6e4255f6 | bellard | NULL);
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173 | 6e4255f6 | bellard | #else
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174 | 9df217a3 | bellard | kqemu_fd = open(KQEMU_DEVICE, O_RDWR); |
175 | 6e4255f6 | bellard | #endif
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176 | 6e4255f6 | bellard | if (kqemu_fd == KQEMU_INVALID_FD) {
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177 | 9df217a3 | bellard | fprintf(stderr, "Could not open '%s' - QEMU acceleration layer not activated\n", KQEMU_DEVICE);
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178 | 9df217a3 | bellard | return -1; |
179 | 9df217a3 | bellard | } |
180 | 9df217a3 | bellard | version = 0;
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181 | 6e4255f6 | bellard | #ifdef _WIN32
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182 | 6e4255f6 | bellard | DeviceIoControl(kqemu_fd, KQEMU_GET_VERSION, NULL, 0, |
183 | 6e4255f6 | bellard | &version, sizeof(version), &temp, NULL); |
184 | 6e4255f6 | bellard | #else
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185 | 9df217a3 | bellard | ioctl(kqemu_fd, KQEMU_GET_VERSION, &version); |
186 | 6e4255f6 | bellard | #endif
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187 | 9df217a3 | bellard | if (version != KQEMU_VERSION) {
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188 | 9df217a3 | bellard | fprintf(stderr, "Version mismatch between kqemu module and qemu (%08x %08x) - disabling kqemu use\n",
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189 | 9df217a3 | bellard | version, KQEMU_VERSION); |
190 | 9df217a3 | bellard | goto fail;
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191 | 9df217a3 | bellard | } |
192 | 9df217a3 | bellard | |
193 | 9df217a3 | bellard | pages_to_flush = qemu_vmalloc(KQEMU_MAX_PAGES_TO_FLUSH * |
194 | 9df217a3 | bellard | sizeof(unsigned long)); |
195 | 9df217a3 | bellard | if (!pages_to_flush)
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196 | 9df217a3 | bellard | goto fail;
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197 | 9df217a3 | bellard | |
198 | aa062973 | bellard | ram_pages_to_update = qemu_vmalloc(KQEMU_MAX_RAM_PAGES_TO_UPDATE * |
199 | aa062973 | bellard | sizeof(unsigned long)); |
200 | aa062973 | bellard | if (!ram_pages_to_update)
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201 | aa062973 | bellard | goto fail;
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202 | aa062973 | bellard | |
203 | f32fc648 | bellard | modified_ram_pages = qemu_vmalloc(KQEMU_MAX_MODIFIED_RAM_PAGES * |
204 | f32fc648 | bellard | sizeof(unsigned long)); |
205 | f32fc648 | bellard | if (!modified_ram_pages)
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206 | f32fc648 | bellard | goto fail;
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207 | f32fc648 | bellard | modified_ram_pages_table = qemu_mallocz(phys_ram_size >> TARGET_PAGE_BITS); |
208 | f32fc648 | bellard | if (!modified_ram_pages_table)
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209 | f32fc648 | bellard | goto fail;
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210 | f32fc648 | bellard | |
211 | 9df217a3 | bellard | init.ram_base = phys_ram_base; |
212 | 9df217a3 | bellard | init.ram_size = phys_ram_size; |
213 | 9df217a3 | bellard | init.ram_dirty = phys_ram_dirty; |
214 | 9df217a3 | bellard | init.phys_to_ram_map = l1_phys_map; |
215 | 9df217a3 | bellard | init.pages_to_flush = pages_to_flush; |
216 | aa062973 | bellard | #if KQEMU_VERSION >= 0x010200 |
217 | aa062973 | bellard | init.ram_pages_to_update = ram_pages_to_update; |
218 | aa062973 | bellard | #endif
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219 | f32fc648 | bellard | #if KQEMU_VERSION >= 0x010300 |
220 | f32fc648 | bellard | init.modified_ram_pages = modified_ram_pages; |
221 | f32fc648 | bellard | #endif
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222 | 6e4255f6 | bellard | #ifdef _WIN32
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223 | 6e4255f6 | bellard | ret = DeviceIoControl(kqemu_fd, KQEMU_INIT, &init, sizeof(init),
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224 | 6e4255f6 | bellard | NULL, 0, &temp, NULL) == TRUE ? 0 : -1; |
225 | 6e4255f6 | bellard | #else
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226 | 9df217a3 | bellard | ret = ioctl(kqemu_fd, KQEMU_INIT, &init); |
227 | 6e4255f6 | bellard | #endif
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228 | 9df217a3 | bellard | if (ret < 0) { |
229 | 9df217a3 | bellard | fprintf(stderr, "Error %d while initializing QEMU acceleration layer - disabling it for now\n", ret);
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230 | 9df217a3 | bellard | fail:
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231 | 6e4255f6 | bellard | kqemu_closefd(kqemu_fd); |
232 | 6e4255f6 | bellard | kqemu_fd = KQEMU_INVALID_FD; |
233 | 9df217a3 | bellard | return -1; |
234 | 9df217a3 | bellard | } |
235 | 9df217a3 | bellard | kqemu_update_cpuid(env); |
236 | f32fc648 | bellard | env->kqemu_enabled = kqemu_allowed; |
237 | 9df217a3 | bellard | nb_pages_to_flush = 0;
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238 | aa062973 | bellard | nb_ram_pages_to_update = 0;
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239 | 9df217a3 | bellard | return 0; |
240 | 9df217a3 | bellard | } |
241 | 9df217a3 | bellard | |
242 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr)
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243 | 9df217a3 | bellard | { |
244 | f32fc648 | bellard | #if defined(DEBUG)
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245 | 9df217a3 | bellard | if (loglevel & CPU_LOG_INT) {
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246 | 9df217a3 | bellard | fprintf(logfile, "kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr); |
247 | 9df217a3 | bellard | } |
248 | 9df217a3 | bellard | #endif
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249 | 9df217a3 | bellard | if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH)
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250 | 9df217a3 | bellard | nb_pages_to_flush = KQEMU_FLUSH_ALL; |
251 | 9df217a3 | bellard | else
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252 | 9df217a3 | bellard | pages_to_flush[nb_pages_to_flush++] = addr; |
253 | 9df217a3 | bellard | } |
254 | 9df217a3 | bellard | |
255 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global) |
256 | 9df217a3 | bellard | { |
257 | 9df217a3 | bellard | #ifdef DEBUG
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258 | 9df217a3 | bellard | if (loglevel & CPU_LOG_INT) {
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259 | 9df217a3 | bellard | fprintf(logfile, "kqemu_flush:\n");
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260 | 9df217a3 | bellard | } |
261 | 9df217a3 | bellard | #endif
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262 | 9df217a3 | bellard | nb_pages_to_flush = KQEMU_FLUSH_ALL; |
263 | 9df217a3 | bellard | } |
264 | 9df217a3 | bellard | |
265 | aa062973 | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr)
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266 | aa062973 | bellard | { |
267 | aa062973 | bellard | #ifdef DEBUG
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268 | aa062973 | bellard | if (loglevel & CPU_LOG_INT) {
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269 | aa062973 | bellard | fprintf(logfile, "kqemu_set_notdirty: addr=%08lx\n", ram_addr);
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270 | aa062973 | bellard | } |
271 | aa062973 | bellard | #endif
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272 | fc8dc060 | bellard | /* we only track transitions to dirty state */
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273 | fc8dc060 | bellard | if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff) |
274 | fc8dc060 | bellard | return;
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275 | aa062973 | bellard | if (nb_ram_pages_to_update >= KQEMU_MAX_RAM_PAGES_TO_UPDATE)
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276 | aa062973 | bellard | nb_ram_pages_to_update = KQEMU_RAM_PAGES_UPDATE_ALL; |
277 | aa062973 | bellard | else
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278 | aa062973 | bellard | ram_pages_to_update[nb_ram_pages_to_update++] = ram_addr; |
279 | aa062973 | bellard | } |
280 | aa062973 | bellard | |
281 | f32fc648 | bellard | static void kqemu_reset_modified_ram_pages(void) |
282 | f32fc648 | bellard | { |
283 | f32fc648 | bellard | int i;
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284 | f32fc648 | bellard | unsigned long page_index; |
285 | f32fc648 | bellard | |
286 | f32fc648 | bellard | for(i = 0; i < nb_modified_ram_pages; i++) { |
287 | f32fc648 | bellard | page_index = modified_ram_pages[i] >> TARGET_PAGE_BITS; |
288 | f32fc648 | bellard | modified_ram_pages_table[page_index] = 0;
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289 | f32fc648 | bellard | } |
290 | f32fc648 | bellard | nb_modified_ram_pages = 0;
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291 | f32fc648 | bellard | } |
292 | f32fc648 | bellard | |
293 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr)
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294 | f32fc648 | bellard | { |
295 | f32fc648 | bellard | unsigned long page_index; |
296 | f32fc648 | bellard | int ret;
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297 | f32fc648 | bellard | #ifdef _WIN32
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298 | f32fc648 | bellard | DWORD temp; |
299 | f32fc648 | bellard | #endif
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300 | f32fc648 | bellard | |
301 | f32fc648 | bellard | page_index = ram_addr >> TARGET_PAGE_BITS; |
302 | f32fc648 | bellard | if (!modified_ram_pages_table[page_index]) {
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303 | f32fc648 | bellard | #if 0
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304 | f32fc648 | bellard | printf("%d: modify_page=%08lx\n", nb_modified_ram_pages, ram_addr);
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305 | f32fc648 | bellard | #endif
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306 | f32fc648 | bellard | modified_ram_pages_table[page_index] = 1;
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307 | f32fc648 | bellard | modified_ram_pages[nb_modified_ram_pages++] = ram_addr; |
308 | f32fc648 | bellard | if (nb_modified_ram_pages >= KQEMU_MAX_MODIFIED_RAM_PAGES) {
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309 | f32fc648 | bellard | /* flush */
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310 | f32fc648 | bellard | #ifdef _WIN32
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311 | f32fc648 | bellard | ret = DeviceIoControl(kqemu_fd, KQEMU_MODIFY_RAM_PAGES, |
312 | f32fc648 | bellard | &nb_modified_ram_pages, |
313 | f32fc648 | bellard | sizeof(nb_modified_ram_pages),
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314 | f32fc648 | bellard | NULL, 0, &temp, NULL); |
315 | f32fc648 | bellard | #else
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316 | f32fc648 | bellard | ret = ioctl(kqemu_fd, KQEMU_MODIFY_RAM_PAGES, |
317 | f32fc648 | bellard | &nb_modified_ram_pages); |
318 | f32fc648 | bellard | #endif
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319 | f32fc648 | bellard | kqemu_reset_modified_ram_pages(); |
320 | f32fc648 | bellard | } |
321 | f32fc648 | bellard | } |
322 | f32fc648 | bellard | } |
323 | f32fc648 | bellard | |
324 | 9df217a3 | bellard | struct fpstate {
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325 | 9df217a3 | bellard | uint16_t fpuc; |
326 | 9df217a3 | bellard | uint16_t dummy1; |
327 | 9df217a3 | bellard | uint16_t fpus; |
328 | 9df217a3 | bellard | uint16_t dummy2; |
329 | 9df217a3 | bellard | uint16_t fptag; |
330 | 9df217a3 | bellard | uint16_t dummy3; |
331 | 9df217a3 | bellard | |
332 | 9df217a3 | bellard | uint32_t fpip; |
333 | 9df217a3 | bellard | uint32_t fpcs; |
334 | 9df217a3 | bellard | uint32_t fpoo; |
335 | 9df217a3 | bellard | uint32_t fpos; |
336 | 9df217a3 | bellard | uint8_t fpregs1[8 * 10]; |
337 | 9df217a3 | bellard | }; |
338 | 9df217a3 | bellard | |
339 | 9df217a3 | bellard | struct fpxstate {
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340 | 9df217a3 | bellard | uint16_t fpuc; |
341 | 9df217a3 | bellard | uint16_t fpus; |
342 | 9df217a3 | bellard | uint16_t fptag; |
343 | 9df217a3 | bellard | uint16_t fop; |
344 | 9df217a3 | bellard | uint32_t fpuip; |
345 | 9df217a3 | bellard | uint16_t cs_sel; |
346 | 9df217a3 | bellard | uint16_t dummy0; |
347 | 9df217a3 | bellard | uint32_t fpudp; |
348 | 9df217a3 | bellard | uint16_t ds_sel; |
349 | 9df217a3 | bellard | uint16_t dummy1; |
350 | 9df217a3 | bellard | uint32_t mxcsr; |
351 | 9df217a3 | bellard | uint32_t mxcsr_mask; |
352 | 9df217a3 | bellard | uint8_t fpregs1[8 * 16]; |
353 | c28e951f | bellard | uint8_t xmm_regs[16 * 16]; |
354 | c28e951f | bellard | uint8_t dummy2[96];
|
355 | 9df217a3 | bellard | }; |
356 | 9df217a3 | bellard | |
357 | 9df217a3 | bellard | static struct fpxstate fpx1 __attribute__((aligned(16))); |
358 | 9df217a3 | bellard | |
359 | 9df217a3 | bellard | static void restore_native_fp_frstor(CPUState *env) |
360 | 9df217a3 | bellard | { |
361 | 9df217a3 | bellard | int fptag, i, j;
|
362 | 9df217a3 | bellard | struct fpstate fp1, *fp = &fp1;
|
363 | 9df217a3 | bellard | |
364 | 9df217a3 | bellard | fp->fpuc = env->fpuc; |
365 | 9df217a3 | bellard | fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
366 | 9df217a3 | bellard | fptag = 0;
|
367 | 9df217a3 | bellard | for (i=7; i>=0; i--) { |
368 | 9df217a3 | bellard | fptag <<= 2;
|
369 | 9df217a3 | bellard | if (env->fptags[i]) {
|
370 | 9df217a3 | bellard | fptag |= 3;
|
371 | 9df217a3 | bellard | } else {
|
372 | 9df217a3 | bellard | /* the FPU automatically computes it */
|
373 | 9df217a3 | bellard | } |
374 | 9df217a3 | bellard | } |
375 | 9df217a3 | bellard | fp->fptag = fptag; |
376 | 9df217a3 | bellard | j = env->fpstt; |
377 | 9df217a3 | bellard | for(i = 0;i < 8; i++) { |
378 | 9df217a3 | bellard | memcpy(&fp->fpregs1[i * 10], &env->fpregs[j].d, 10); |
379 | 9df217a3 | bellard | j = (j + 1) & 7; |
380 | 9df217a3 | bellard | } |
381 | 9df217a3 | bellard | asm volatile ("frstor %0" : "=m" (*fp)); |
382 | 9df217a3 | bellard | } |
383 | 9df217a3 | bellard | |
384 | 9df217a3 | bellard | static void save_native_fp_fsave(CPUState *env) |
385 | 9df217a3 | bellard | { |
386 | 9df217a3 | bellard | int fptag, i, j;
|
387 | 9df217a3 | bellard | uint16_t fpuc; |
388 | 9df217a3 | bellard | struct fpstate fp1, *fp = &fp1;
|
389 | 9df217a3 | bellard | |
390 | 9df217a3 | bellard | asm volatile ("fsave %0" : : "m" (*fp)); |
391 | 9df217a3 | bellard | env->fpuc = fp->fpuc; |
392 | 9df217a3 | bellard | env->fpstt = (fp->fpus >> 11) & 7; |
393 | 9df217a3 | bellard | env->fpus = fp->fpus & ~0x3800;
|
394 | 9df217a3 | bellard | fptag = fp->fptag; |
395 | 9df217a3 | bellard | for(i = 0;i < 8; i++) { |
396 | 9df217a3 | bellard | env->fptags[i] = ((fptag & 3) == 3); |
397 | 9df217a3 | bellard | fptag >>= 2;
|
398 | 9df217a3 | bellard | } |
399 | 9df217a3 | bellard | j = env->fpstt; |
400 | 9df217a3 | bellard | for(i = 0;i < 8; i++) { |
401 | 9df217a3 | bellard | memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 10], 10); |
402 | 9df217a3 | bellard | j = (j + 1) & 7; |
403 | 9df217a3 | bellard | } |
404 | 9df217a3 | bellard | /* we must restore the default rounding state */
|
405 | 9df217a3 | bellard | fpuc = 0x037f | (env->fpuc & (3 << 10)); |
406 | 9df217a3 | bellard | asm volatile("fldcw %0" : : "m" (fpuc)); |
407 | 9df217a3 | bellard | } |
408 | 9df217a3 | bellard | |
409 | 9df217a3 | bellard | static void restore_native_fp_fxrstor(CPUState *env) |
410 | 9df217a3 | bellard | { |
411 | 9df217a3 | bellard | struct fpxstate *fp = &fpx1;
|
412 | 9df217a3 | bellard | int i, j, fptag;
|
413 | 9df217a3 | bellard | |
414 | 9df217a3 | bellard | fp->fpuc = env->fpuc; |
415 | 9df217a3 | bellard | fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
416 | 9df217a3 | bellard | fptag = 0;
|
417 | 9df217a3 | bellard | for(i = 0; i < 8; i++) |
418 | 9df217a3 | bellard | fptag |= (env->fptags[i] << i); |
419 | 9df217a3 | bellard | fp->fptag = fptag ^ 0xff;
|
420 | 9df217a3 | bellard | |
421 | 9df217a3 | bellard | j = env->fpstt; |
422 | 9df217a3 | bellard | for(i = 0;i < 8; i++) { |
423 | 9df217a3 | bellard | memcpy(&fp->fpregs1[i * 16], &env->fpregs[j].d, 10); |
424 | 9df217a3 | bellard | j = (j + 1) & 7; |
425 | 9df217a3 | bellard | } |
426 | 9df217a3 | bellard | if (env->cpuid_features & CPUID_SSE) {
|
427 | 9df217a3 | bellard | fp->mxcsr = env->mxcsr; |
428 | 9df217a3 | bellard | /* XXX: check if DAZ is not available */
|
429 | 9df217a3 | bellard | fp->mxcsr_mask = 0xffff;
|
430 | c28e951f | bellard | memcpy(fp->xmm_regs, env->xmm_regs, CPU_NB_REGS * 16);
|
431 | 9df217a3 | bellard | } |
432 | 9df217a3 | bellard | asm volatile ("fxrstor %0" : "=m" (*fp)); |
433 | 9df217a3 | bellard | } |
434 | 9df217a3 | bellard | |
435 | 9df217a3 | bellard | static void save_native_fp_fxsave(CPUState *env) |
436 | 9df217a3 | bellard | { |
437 | 9df217a3 | bellard | struct fpxstate *fp = &fpx1;
|
438 | 9df217a3 | bellard | int fptag, i, j;
|
439 | 9df217a3 | bellard | uint16_t fpuc; |
440 | 9df217a3 | bellard | |
441 | 9df217a3 | bellard | asm volatile ("fxsave %0" : : "m" (*fp)); |
442 | 9df217a3 | bellard | env->fpuc = fp->fpuc; |
443 | 9df217a3 | bellard | env->fpstt = (fp->fpus >> 11) & 7; |
444 | 9df217a3 | bellard | env->fpus = fp->fpus & ~0x3800;
|
445 | 9df217a3 | bellard | fptag = fp->fptag ^ 0xff;
|
446 | 9df217a3 | bellard | for(i = 0;i < 8; i++) { |
447 | 9df217a3 | bellard | env->fptags[i] = (fptag >> i) & 1;
|
448 | 9df217a3 | bellard | } |
449 | 9df217a3 | bellard | j = env->fpstt; |
450 | 9df217a3 | bellard | for(i = 0;i < 8; i++) { |
451 | 9df217a3 | bellard | memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 16], 10); |
452 | 9df217a3 | bellard | j = (j + 1) & 7; |
453 | 9df217a3 | bellard | } |
454 | 9df217a3 | bellard | if (env->cpuid_features & CPUID_SSE) {
|
455 | 9df217a3 | bellard | env->mxcsr = fp->mxcsr; |
456 | c28e951f | bellard | memcpy(env->xmm_regs, fp->xmm_regs, CPU_NB_REGS * 16);
|
457 | 9df217a3 | bellard | } |
458 | 9df217a3 | bellard | |
459 | 9df217a3 | bellard | /* we must restore the default rounding state */
|
460 | 9df217a3 | bellard | asm volatile ("fninit"); |
461 | 9df217a3 | bellard | fpuc = 0x037f | (env->fpuc & (3 << 10)); |
462 | 9df217a3 | bellard | asm volatile("fldcw %0" : : "m" (fpuc)); |
463 | 9df217a3 | bellard | } |
464 | 9df217a3 | bellard | |
465 | c28e951f | bellard | static int do_syscall(CPUState *env, |
466 | c28e951f | bellard | struct kqemu_cpu_state *kenv)
|
467 | c28e951f | bellard | { |
468 | c28e951f | bellard | int selector;
|
469 | c28e951f | bellard | |
470 | c28e951f | bellard | selector = (env->star >> 32) & 0xffff; |
471 | c28e951f | bellard | #ifdef __x86_64__
|
472 | c28e951f | bellard | if (env->hflags & HF_LMA_MASK) {
|
473 | c28e951f | bellard | env->regs[R_ECX] = kenv->next_eip; |
474 | c28e951f | bellard | env->regs[11] = env->eflags;
|
475 | c28e951f | bellard | |
476 | c28e951f | bellard | cpu_x86_set_cpl(env, 0);
|
477 | c28e951f | bellard | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
478 | c28e951f | bellard | 0, 0xffffffff, |
479 | c28e951f | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
480 | c28e951f | bellard | DESC_S_MASK | |
481 | c28e951f | bellard | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK); |
482 | c28e951f | bellard | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
483 | c28e951f | bellard | 0, 0xffffffff, |
484 | c28e951f | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
485 | c28e951f | bellard | DESC_S_MASK | |
486 | c28e951f | bellard | DESC_W_MASK | DESC_A_MASK); |
487 | c28e951f | bellard | env->eflags &= ~env->fmask; |
488 | c28e951f | bellard | if (env->hflags & HF_CS64_MASK)
|
489 | c28e951f | bellard | env->eip = env->lstar; |
490 | c28e951f | bellard | else
|
491 | c28e951f | bellard | env->eip = env->cstar; |
492 | c28e951f | bellard | } else
|
493 | c28e951f | bellard | #endif
|
494 | c28e951f | bellard | { |
495 | c28e951f | bellard | env->regs[R_ECX] = (uint32_t)kenv->next_eip; |
496 | c28e951f | bellard | |
497 | c28e951f | bellard | cpu_x86_set_cpl(env, 0);
|
498 | c28e951f | bellard | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
499 | c28e951f | bellard | 0, 0xffffffff, |
500 | c28e951f | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
501 | c28e951f | bellard | DESC_S_MASK | |
502 | c28e951f | bellard | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
503 | c28e951f | bellard | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
504 | c28e951f | bellard | 0, 0xffffffff, |
505 | c28e951f | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
506 | c28e951f | bellard | DESC_S_MASK | |
507 | c28e951f | bellard | DESC_W_MASK | DESC_A_MASK); |
508 | c28e951f | bellard | env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); |
509 | c28e951f | bellard | env->eip = (uint32_t)env->star; |
510 | c28e951f | bellard | } |
511 | c28e951f | bellard | return 2; |
512 | c28e951f | bellard | } |
513 | c28e951f | bellard | |
514 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
515 | aa062973 | bellard | |
516 | aa062973 | bellard | #define PC_REC_SIZE 1 |
517 | aa062973 | bellard | #define PC_REC_HASH_BITS 16 |
518 | aa062973 | bellard | #define PC_REC_HASH_SIZE (1 << PC_REC_HASH_BITS) |
519 | aa062973 | bellard | |
520 | aa062973 | bellard | typedef struct PCRecord { |
521 | aa062973 | bellard | unsigned long pc; |
522 | aa062973 | bellard | int64_t count; |
523 | aa062973 | bellard | struct PCRecord *next;
|
524 | aa062973 | bellard | } PCRecord; |
525 | aa062973 | bellard | |
526 | f32fc648 | bellard | static PCRecord *pc_rec_hash[PC_REC_HASH_SIZE];
|
527 | f32fc648 | bellard | static int nb_pc_records; |
528 | aa062973 | bellard | |
529 | f32fc648 | bellard | static void kqemu_record_pc(unsigned long pc) |
530 | aa062973 | bellard | { |
531 | aa062973 | bellard | unsigned long h; |
532 | aa062973 | bellard | PCRecord **pr, *r; |
533 | aa062973 | bellard | |
534 | aa062973 | bellard | h = pc / PC_REC_SIZE; |
535 | aa062973 | bellard | h = h ^ (h >> PC_REC_HASH_BITS); |
536 | aa062973 | bellard | h &= (PC_REC_HASH_SIZE - 1);
|
537 | aa062973 | bellard | pr = &pc_rec_hash[h]; |
538 | aa062973 | bellard | for(;;) {
|
539 | aa062973 | bellard | r = *pr; |
540 | aa062973 | bellard | if (r == NULL) |
541 | aa062973 | bellard | break;
|
542 | aa062973 | bellard | if (r->pc == pc) {
|
543 | aa062973 | bellard | r->count++; |
544 | aa062973 | bellard | return;
|
545 | aa062973 | bellard | } |
546 | aa062973 | bellard | pr = &r->next; |
547 | aa062973 | bellard | } |
548 | aa062973 | bellard | r = malloc(sizeof(PCRecord));
|
549 | aa062973 | bellard | r->count = 1;
|
550 | aa062973 | bellard | r->pc = pc; |
551 | aa062973 | bellard | r->next = NULL;
|
552 | aa062973 | bellard | *pr = r; |
553 | aa062973 | bellard | nb_pc_records++; |
554 | aa062973 | bellard | } |
555 | aa062973 | bellard | |
556 | f32fc648 | bellard | static int pc_rec_cmp(const void *p1, const void *p2) |
557 | aa062973 | bellard | { |
558 | aa062973 | bellard | PCRecord *r1 = *(PCRecord **)p1; |
559 | aa062973 | bellard | PCRecord *r2 = *(PCRecord **)p2; |
560 | aa062973 | bellard | if (r1->count < r2->count)
|
561 | aa062973 | bellard | return 1; |
562 | aa062973 | bellard | else if (r1->count == r2->count) |
563 | aa062973 | bellard | return 0; |
564 | aa062973 | bellard | else
|
565 | aa062973 | bellard | return -1; |
566 | aa062973 | bellard | } |
567 | aa062973 | bellard | |
568 | f32fc648 | bellard | static void kqemu_record_flush(void) |
569 | f32fc648 | bellard | { |
570 | f32fc648 | bellard | PCRecord *r, *r_next; |
571 | f32fc648 | bellard | int h;
|
572 | f32fc648 | bellard | |
573 | f32fc648 | bellard | for(h = 0; h < PC_REC_HASH_SIZE; h++) { |
574 | f32fc648 | bellard | for(r = pc_rec_hash[h]; r != NULL; r = r_next) { |
575 | f32fc648 | bellard | r_next = r->next; |
576 | f32fc648 | bellard | free(r); |
577 | f32fc648 | bellard | } |
578 | f32fc648 | bellard | pc_rec_hash[h] = NULL;
|
579 | f32fc648 | bellard | } |
580 | f32fc648 | bellard | nb_pc_records = 0;
|
581 | f32fc648 | bellard | } |
582 | f32fc648 | bellard | |
583 | aa062973 | bellard | void kqemu_record_dump(void) |
584 | aa062973 | bellard | { |
585 | aa062973 | bellard | PCRecord **pr, *r; |
586 | aa062973 | bellard | int i, h;
|
587 | aa062973 | bellard | FILE *f; |
588 | aa062973 | bellard | int64_t total, sum; |
589 | aa062973 | bellard | |
590 | aa062973 | bellard | pr = malloc(sizeof(PCRecord *) * nb_pc_records);
|
591 | aa062973 | bellard | i = 0;
|
592 | aa062973 | bellard | total = 0;
|
593 | aa062973 | bellard | for(h = 0; h < PC_REC_HASH_SIZE; h++) { |
594 | aa062973 | bellard | for(r = pc_rec_hash[h]; r != NULL; r = r->next) { |
595 | aa062973 | bellard | pr[i++] = r; |
596 | aa062973 | bellard | total += r->count; |
597 | aa062973 | bellard | } |
598 | aa062973 | bellard | } |
599 | aa062973 | bellard | qsort(pr, nb_pc_records, sizeof(PCRecord *), pc_rec_cmp);
|
600 | aa062973 | bellard | |
601 | aa062973 | bellard | f = fopen("/tmp/kqemu.stats", "w"); |
602 | aa062973 | bellard | if (!f) {
|
603 | aa062973 | bellard | perror("/tmp/kqemu.stats");
|
604 | aa062973 | bellard | exit(1);
|
605 | aa062973 | bellard | } |
606 | 26a76461 | bellard | fprintf(f, "total: %" PRId64 "\n", total); |
607 | aa062973 | bellard | sum = 0;
|
608 | aa062973 | bellard | for(i = 0; i < nb_pc_records; i++) { |
609 | aa062973 | bellard | r = pr[i]; |
610 | aa062973 | bellard | sum += r->count; |
611 | 26a76461 | bellard | fprintf(f, "%08lx: %" PRId64 " %0.2f%% %0.2f%%\n", |
612 | aa062973 | bellard | r->pc, |
613 | aa062973 | bellard | r->count, |
614 | aa062973 | bellard | (double)r->count / (double)total * 100.0, |
615 | aa062973 | bellard | (double)sum / (double)total * 100.0); |
616 | aa062973 | bellard | } |
617 | aa062973 | bellard | fclose(f); |
618 | aa062973 | bellard | free(pr); |
619 | f32fc648 | bellard | |
620 | f32fc648 | bellard | kqemu_record_flush(); |
621 | aa062973 | bellard | } |
622 | aa062973 | bellard | #endif
|
623 | aa062973 | bellard | |
624 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env)
|
625 | 9df217a3 | bellard | { |
626 | 9df217a3 | bellard | struct kqemu_cpu_state kcpu_state, *kenv = &kcpu_state;
|
627 | f32fc648 | bellard | int ret, cpl, i;
|
628 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
629 | f32fc648 | bellard | int64_t ti; |
630 | f32fc648 | bellard | #endif
|
631 | f32fc648 | bellard | |
632 | 6e4255f6 | bellard | #ifdef _WIN32
|
633 | 6e4255f6 | bellard | DWORD temp; |
634 | 6e4255f6 | bellard | #endif
|
635 | 9df217a3 | bellard | |
636 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
637 | f32fc648 | bellard | ti = profile_getclock(); |
638 | f32fc648 | bellard | #endif
|
639 | 9df217a3 | bellard | #ifdef DEBUG
|
640 | 9df217a3 | bellard | if (loglevel & CPU_LOG_INT) {
|
641 | 9df217a3 | bellard | fprintf(logfile, "kqemu: cpu_exec: enter\n");
|
642 | 9df217a3 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
643 | 9df217a3 | bellard | } |
644 | 9df217a3 | bellard | #endif
|
645 | 9df217a3 | bellard | memcpy(kenv->regs, env->regs, sizeof(kenv->regs));
|
646 | 9df217a3 | bellard | kenv->eip = env->eip; |
647 | 9df217a3 | bellard | kenv->eflags = env->eflags; |
648 | 9df217a3 | bellard | memcpy(&kenv->segs, &env->segs, sizeof(env->segs));
|
649 | 9df217a3 | bellard | memcpy(&kenv->ldt, &env->ldt, sizeof(env->ldt));
|
650 | 9df217a3 | bellard | memcpy(&kenv->tr, &env->tr, sizeof(env->tr));
|
651 | 9df217a3 | bellard | memcpy(&kenv->gdt, &env->gdt, sizeof(env->gdt));
|
652 | 9df217a3 | bellard | memcpy(&kenv->idt, &env->idt, sizeof(env->idt));
|
653 | 9df217a3 | bellard | kenv->cr0 = env->cr[0];
|
654 | 9df217a3 | bellard | kenv->cr2 = env->cr[2];
|
655 | 9df217a3 | bellard | kenv->cr3 = env->cr[3];
|
656 | 9df217a3 | bellard | kenv->cr4 = env->cr[4];
|
657 | 9df217a3 | bellard | kenv->a20_mask = env->a20_mask; |
658 | c45b3c0e | bellard | #if KQEMU_VERSION >= 0x010100 |
659 | c28e951f | bellard | kenv->efer = env->efer; |
660 | c28e951f | bellard | #endif
|
661 | f32fc648 | bellard | #if KQEMU_VERSION >= 0x010300 |
662 | f32fc648 | bellard | kenv->tsc_offset = 0;
|
663 | f32fc648 | bellard | kenv->star = env->star; |
664 | f32fc648 | bellard | kenv->sysenter_cs = env->sysenter_cs; |
665 | f32fc648 | bellard | kenv->sysenter_esp = env->sysenter_esp; |
666 | f32fc648 | bellard | kenv->sysenter_eip = env->sysenter_eip; |
667 | f32fc648 | bellard | #ifdef __x86_64__
|
668 | f32fc648 | bellard | kenv->lstar = env->lstar; |
669 | f32fc648 | bellard | kenv->cstar = env->cstar; |
670 | f32fc648 | bellard | kenv->fmask = env->fmask; |
671 | f32fc648 | bellard | kenv->kernelgsbase = env->kernelgsbase; |
672 | f32fc648 | bellard | #endif
|
673 | f32fc648 | bellard | #endif
|
674 | 9df217a3 | bellard | if (env->dr[7] & 0xff) { |
675 | 9df217a3 | bellard | kenv->dr7 = env->dr[7];
|
676 | 9df217a3 | bellard | kenv->dr0 = env->dr[0];
|
677 | 9df217a3 | bellard | kenv->dr1 = env->dr[1];
|
678 | 9df217a3 | bellard | kenv->dr2 = env->dr[2];
|
679 | 9df217a3 | bellard | kenv->dr3 = env->dr[3];
|
680 | 9df217a3 | bellard | } else {
|
681 | 9df217a3 | bellard | kenv->dr7 = 0;
|
682 | 9df217a3 | bellard | } |
683 | 9df217a3 | bellard | kenv->dr6 = env->dr[6];
|
684 | f32fc648 | bellard | cpl = (env->hflags & HF_CPL_MASK); |
685 | f32fc648 | bellard | kenv->cpl = cpl; |
686 | 9df217a3 | bellard | kenv->nb_pages_to_flush = nb_pages_to_flush; |
687 | aa062973 | bellard | #if KQEMU_VERSION >= 0x010200 |
688 | f32fc648 | bellard | kenv->user_only = (env->kqemu_enabled == 1);
|
689 | aa062973 | bellard | kenv->nb_ram_pages_to_update = nb_ram_pages_to_update; |
690 | aa062973 | bellard | #endif
|
691 | aa062973 | bellard | nb_ram_pages_to_update = 0;
|
692 | 9df217a3 | bellard | |
693 | f32fc648 | bellard | #if KQEMU_VERSION >= 0x010300 |
694 | f32fc648 | bellard | kenv->nb_modified_ram_pages = nb_modified_ram_pages; |
695 | f32fc648 | bellard | #endif
|
696 | f32fc648 | bellard | kqemu_reset_modified_ram_pages(); |
697 | f32fc648 | bellard | |
698 | f32fc648 | bellard | if (env->cpuid_features & CPUID_FXSR)
|
699 | f32fc648 | bellard | restore_native_fp_fxrstor(env); |
700 | f32fc648 | bellard | else
|
701 | f32fc648 | bellard | restore_native_fp_frstor(env); |
702 | 9df217a3 | bellard | |
703 | 6e4255f6 | bellard | #ifdef _WIN32
|
704 | a332e112 | bellard | if (DeviceIoControl(kqemu_fd, KQEMU_EXEC,
|
705 | a332e112 | bellard | kenv, sizeof(struct kqemu_cpu_state), |
706 | a332e112 | bellard | kenv, sizeof(struct kqemu_cpu_state), |
707 | a332e112 | bellard | &temp, NULL)) {
|
708 | a332e112 | bellard | ret = kenv->retval; |
709 | a332e112 | bellard | } else {
|
710 | a332e112 | bellard | ret = -1;
|
711 | a332e112 | bellard | } |
712 | 6e4255f6 | bellard | #else
|
713 | 6e4255f6 | bellard | #if KQEMU_VERSION >= 0x010100 |
714 | 6e4255f6 | bellard | ioctl(kqemu_fd, KQEMU_EXEC, kenv); |
715 | 6e4255f6 | bellard | ret = kenv->retval; |
716 | 6e4255f6 | bellard | #else
|
717 | 9df217a3 | bellard | ret = ioctl(kqemu_fd, KQEMU_EXEC, kenv); |
718 | 6e4255f6 | bellard | #endif
|
719 | 6e4255f6 | bellard | #endif
|
720 | f32fc648 | bellard | if (env->cpuid_features & CPUID_FXSR)
|
721 | f32fc648 | bellard | save_native_fp_fxsave(env); |
722 | f32fc648 | bellard | else
|
723 | f32fc648 | bellard | save_native_fp_fsave(env); |
724 | 9df217a3 | bellard | |
725 | 9df217a3 | bellard | memcpy(env->regs, kenv->regs, sizeof(env->regs));
|
726 | 9df217a3 | bellard | env->eip = kenv->eip; |
727 | 9df217a3 | bellard | env->eflags = kenv->eflags; |
728 | 9df217a3 | bellard | memcpy(env->segs, kenv->segs, sizeof(env->segs));
|
729 | f32fc648 | bellard | cpu_x86_set_cpl(env, kenv->cpl); |
730 | f32fc648 | bellard | memcpy(&env->ldt, &kenv->ldt, sizeof(env->ldt));
|
731 | 9df217a3 | bellard | #if 0
|
732 | 9df217a3 | bellard | /* no need to restore that */
|
733 | 9df217a3 | bellard | memcpy(env->tr, kenv->tr, sizeof(env->tr));
|
734 | 9df217a3 | bellard | memcpy(env->gdt, kenv->gdt, sizeof(env->gdt));
|
735 | 9df217a3 | bellard | memcpy(env->idt, kenv->idt, sizeof(env->idt));
|
736 | 9df217a3 | bellard | env->a20_mask = kenv->a20_mask;
|
737 | 9df217a3 | bellard | #endif
|
738 | f32fc648 | bellard | env->cr[0] = kenv->cr0;
|
739 | f32fc648 | bellard | env->cr[4] = kenv->cr4;
|
740 | f32fc648 | bellard | env->cr[3] = kenv->cr3;
|
741 | 9df217a3 | bellard | env->cr[2] = kenv->cr2;
|
742 | 9df217a3 | bellard | env->dr[6] = kenv->dr6;
|
743 | f32fc648 | bellard | #if KQEMU_VERSION >= 0x010300 |
744 | f32fc648 | bellard | #ifdef __x86_64__
|
745 | f32fc648 | bellard | env->kernelgsbase = kenv->kernelgsbase; |
746 | f32fc648 | bellard | #endif
|
747 | f32fc648 | bellard | #endif
|
748 | f32fc648 | bellard | |
749 | f32fc648 | bellard | /* flush pages as indicated by kqemu */
|
750 | f32fc648 | bellard | if (kenv->nb_pages_to_flush >= KQEMU_FLUSH_ALL) {
|
751 | f32fc648 | bellard | tlb_flush(env, 1);
|
752 | f32fc648 | bellard | } else {
|
753 | f32fc648 | bellard | for(i = 0; i < kenv->nb_pages_to_flush; i++) { |
754 | f32fc648 | bellard | tlb_flush_page(env, pages_to_flush[i]); |
755 | f32fc648 | bellard | } |
756 | f32fc648 | bellard | } |
757 | f32fc648 | bellard | nb_pages_to_flush = 0;
|
758 | f32fc648 | bellard | |
759 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
760 | f32fc648 | bellard | kqemu_time += profile_getclock() - ti; |
761 | f32fc648 | bellard | kqemu_exec_count++; |
762 | f32fc648 | bellard | #endif
|
763 | 9df217a3 | bellard | |
764 | aa062973 | bellard | #if KQEMU_VERSION >= 0x010200 |
765 | aa062973 | bellard | if (kenv->nb_ram_pages_to_update > 0) { |
766 | aa062973 | bellard | cpu_tlb_update_dirty(env); |
767 | aa062973 | bellard | } |
768 | aa062973 | bellard | #endif
|
769 | aa062973 | bellard | |
770 | f32fc648 | bellard | #if KQEMU_VERSION >= 0x010300 |
771 | f32fc648 | bellard | if (kenv->nb_modified_ram_pages > 0) { |
772 | f32fc648 | bellard | for(i = 0; i < kenv->nb_modified_ram_pages; i++) { |
773 | f32fc648 | bellard | unsigned long addr; |
774 | f32fc648 | bellard | addr = modified_ram_pages[i]; |
775 | f32fc648 | bellard | tb_invalidate_phys_page_range(addr, addr + TARGET_PAGE_SIZE, 0);
|
776 | f32fc648 | bellard | } |
777 | f32fc648 | bellard | } |
778 | f32fc648 | bellard | #endif
|
779 | f32fc648 | bellard | |
780 | aa062973 | bellard | /* restore the hidden flags */
|
781 | aa062973 | bellard | { |
782 | aa062973 | bellard | unsigned int new_hflags; |
783 | aa062973 | bellard | #ifdef TARGET_X86_64
|
784 | aa062973 | bellard | if ((env->hflags & HF_LMA_MASK) &&
|
785 | aa062973 | bellard | (env->segs[R_CS].flags & DESC_L_MASK)) { |
786 | aa062973 | bellard | /* long mode */
|
787 | aa062973 | bellard | new_hflags = HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
788 | aa062973 | bellard | } else
|
789 | aa062973 | bellard | #endif
|
790 | aa062973 | bellard | { |
791 | aa062973 | bellard | /* legacy / compatibility case */
|
792 | aa062973 | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
793 | aa062973 | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
794 | aa062973 | bellard | new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK) |
795 | aa062973 | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
796 | aa062973 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || |
797 | aa062973 | bellard | (env->eflags & VM_MASK) || |
798 | aa062973 | bellard | !(env->hflags & HF_CS32_MASK)) { |
799 | aa062973 | bellard | /* XXX: try to avoid this test. The problem comes from the
|
800 | aa062973 | bellard | fact that is real mode or vm86 mode we only modify the
|
801 | aa062973 | bellard | 'base' and 'selector' fields of the segment cache to go
|
802 | aa062973 | bellard | faster. A solution may be to force addseg to one in
|
803 | aa062973 | bellard | translate-i386.c. */
|
804 | aa062973 | bellard | new_hflags |= HF_ADDSEG_MASK; |
805 | aa062973 | bellard | } else {
|
806 | aa062973 | bellard | new_hflags |= ((env->segs[R_DS].base | |
807 | aa062973 | bellard | env->segs[R_ES].base | |
808 | aa062973 | bellard | env->segs[R_SS].base) != 0) <<
|
809 | aa062973 | bellard | HF_ADDSEG_SHIFT; |
810 | aa062973 | bellard | } |
811 | aa062973 | bellard | } |
812 | aa062973 | bellard | env->hflags = (env->hflags & |
813 | aa062973 | bellard | ~(HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)) | |
814 | aa062973 | bellard | new_hflags; |
815 | aa062973 | bellard | } |
816 | f32fc648 | bellard | /* update FPU flags */
|
817 | f32fc648 | bellard | env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) | |
818 | f32fc648 | bellard | ((env->cr[0] << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)); |
819 | f32fc648 | bellard | if (env->cr[4] & CR4_OSFXSR_MASK) |
820 | f32fc648 | bellard | env->hflags |= HF_OSFXSR_MASK; |
821 | f32fc648 | bellard | else
|
822 | f32fc648 | bellard | env->hflags &= ~HF_OSFXSR_MASK; |
823 | f32fc648 | bellard | |
824 | 9df217a3 | bellard | #ifdef DEBUG
|
825 | 9df217a3 | bellard | if (loglevel & CPU_LOG_INT) {
|
826 | 9df217a3 | bellard | fprintf(logfile, "kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
|
827 | 9df217a3 | bellard | } |
828 | 9df217a3 | bellard | #endif
|
829 | c28e951f | bellard | if (ret == KQEMU_RET_SYSCALL) {
|
830 | c28e951f | bellard | /* syscall instruction */
|
831 | c28e951f | bellard | return do_syscall(env, kenv);
|
832 | c28e951f | bellard | } else
|
833 | 9df217a3 | bellard | if ((ret & 0xff00) == KQEMU_RET_INT) { |
834 | 9df217a3 | bellard | env->exception_index = ret & 0xff;
|
835 | 9df217a3 | bellard | env->error_code = 0;
|
836 | 9df217a3 | bellard | env->exception_is_int = 1;
|
837 | 9df217a3 | bellard | env->exception_next_eip = kenv->next_eip; |
838 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
839 | f32fc648 | bellard | kqemu_ret_int_count++; |
840 | f32fc648 | bellard | #endif
|
841 | 9df217a3 | bellard | #ifdef DEBUG
|
842 | c28e951f | bellard | if (loglevel & CPU_LOG_INT) {
|
843 | c28e951f | bellard | fprintf(logfile, "kqemu: interrupt v=%02x:\n",
|
844 | c28e951f | bellard | env->exception_index); |
845 | c28e951f | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
846 | c28e951f | bellard | } |
847 | 9df217a3 | bellard | #endif
|
848 | 9df217a3 | bellard | return 1; |
849 | 9df217a3 | bellard | } else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) { |
850 | 9df217a3 | bellard | env->exception_index = ret & 0xff;
|
851 | 9df217a3 | bellard | env->error_code = kenv->error_code; |
852 | 9df217a3 | bellard | env->exception_is_int = 0;
|
853 | 9df217a3 | bellard | env->exception_next_eip = 0;
|
854 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
855 | f32fc648 | bellard | kqemu_ret_excp_count++; |
856 | f32fc648 | bellard | #endif
|
857 | 9df217a3 | bellard | #ifdef DEBUG
|
858 | 9df217a3 | bellard | if (loglevel & CPU_LOG_INT) {
|
859 | 9df217a3 | bellard | fprintf(logfile, "kqemu: exception v=%02x e=%04x:\n",
|
860 | 9df217a3 | bellard | env->exception_index, env->error_code); |
861 | 9df217a3 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
862 | 9df217a3 | bellard | } |
863 | 9df217a3 | bellard | #endif
|
864 | 9df217a3 | bellard | return 1; |
865 | 9df217a3 | bellard | } else if (ret == KQEMU_RET_INTR) { |
866 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
867 | f32fc648 | bellard | kqemu_ret_intr_count++; |
868 | f32fc648 | bellard | #endif
|
869 | c45b3c0e | bellard | #ifdef DEBUG
|
870 | c45b3c0e | bellard | if (loglevel & CPU_LOG_INT) {
|
871 | c45b3c0e | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
872 | c45b3c0e | bellard | } |
873 | c45b3c0e | bellard | #endif
|
874 | 9df217a3 | bellard | return 0; |
875 | 9df217a3 | bellard | } else if (ret == KQEMU_RET_SOFTMMU) { |
876 | f32fc648 | bellard | #ifdef CONFIG_PROFILER
|
877 | f32fc648 | bellard | { |
878 | f32fc648 | bellard | unsigned long pc = env->eip + env->segs[R_CS].base; |
879 | f32fc648 | bellard | kqemu_record_pc(pc); |
880 | f32fc648 | bellard | } |
881 | aa062973 | bellard | #endif
|
882 | aa062973 | bellard | #ifdef DEBUG
|
883 | aa062973 | bellard | if (loglevel & CPU_LOG_INT) {
|
884 | aa062973 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
885 | aa062973 | bellard | } |
886 | aa062973 | bellard | #endif
|
887 | 9df217a3 | bellard | return 2; |
888 | 9df217a3 | bellard | } else {
|
889 | 9df217a3 | bellard | cpu_dump_state(env, stderr, fprintf, 0);
|
890 | 9df217a3 | bellard | fprintf(stderr, "Unsupported return value: 0x%x\n", ret);
|
891 | 9df217a3 | bellard | exit(1);
|
892 | 9df217a3 | bellard | } |
893 | 9df217a3 | bellard | return 0; |
894 | 9df217a3 | bellard | } |
895 | 9df217a3 | bellard | |
896 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env)
|
897 | a332e112 | bellard | { |
898 | a332e112 | bellard | #if defined(_WIN32) && KQEMU_VERSION >= 0x010101 |
899 | a332e112 | bellard | /* cancelling the I/O request causes KQEMU to finish executing the
|
900 | a332e112 | bellard | current block and successfully returning. */
|
901 | a332e112 | bellard | CancelIo(kqemu_fd); |
902 | a332e112 | bellard | #endif
|
903 | a332e112 | bellard | } |
904 | a332e112 | bellard | |
905 | 9df217a3 | bellard | #endif |