Revision 0e26b7b8 hw/pc.c
| b/hw/pc.c | ||
|---|---|---|
| 754 | 754 |
return env->cpu_index == 0; |
| 755 | 755 |
} |
| 756 | 756 |
|
| 757 |
APICState *cpu_get_current_apic(void) |
|
| 758 |
{
|
|
| 759 |
if (cpu_single_env) {
|
|
| 760 |
return cpu_single_env->apic_state; |
|
| 761 |
} else {
|
|
| 762 |
return NULL; |
|
| 763 |
} |
|
| 764 |
} |
|
| 765 |
|
|
| 757 | 766 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
| 758 | 767 |
BIOS will read it and start S3 resume at POST Entry */ |
| 759 | 768 |
void pc_cmos_set_s3_resume(void *opaque, int irq, int level) |
| ... | ... | |
| 774 | 783 |
} |
| 775 | 784 |
} |
| 776 | 785 |
|
| 786 |
static void bsp_cpu_reset(void *opaque) |
|
| 787 |
{
|
|
| 788 |
CPUState *env = opaque; |
|
| 789 |
|
|
| 790 |
cpu_reset(env); |
|
| 791 |
env->halted = 0; |
|
| 792 |
} |
|
| 793 |
|
|
| 794 |
static void ap_cpu_reset(void *opaque) |
|
| 795 |
{
|
|
| 796 |
CPUState *env = opaque; |
|
| 797 |
|
|
| 798 |
cpu_reset(env); |
|
| 799 |
env->halted = 1; |
|
| 800 |
} |
|
| 801 |
|
|
| 777 | 802 |
static CPUState *pc_new_cpu(const char *cpu_model) |
| 778 | 803 |
{
|
| 779 | 804 |
CPUState *env; |
| ... | ... | |
| 786 | 811 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
|
| 787 | 812 |
env->cpuid_apic_id = env->cpu_index; |
| 788 | 813 |
/* APIC reset callback resets cpu */ |
| 789 |
apic_init(env); |
|
| 814 |
env->apic_state = apic_init(env, env->cpuid_apic_id); |
|
| 815 |
} |
|
| 816 |
if (cpu_is_bsp(env)) {
|
|
| 817 |
qemu_register_reset(bsp_cpu_reset, env); |
|
| 818 |
env->halted = 0; |
|
| 790 | 819 |
} else {
|
| 791 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, env); |
|
| 820 |
qemu_register_reset(ap_cpu_reset, env); |
|
| 821 |
env->halted = 1; |
|
| 792 | 822 |
} |
| 793 | 823 |
return env; |
| 794 | 824 |
} |
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