Revision 0eaef5aa target-mips/helper.c
| b/target-mips/helper.c | ||
|---|---|---|
| 206 | 206 |
return ret; |
| 207 | 207 |
} |
| 208 | 208 |
|
| 209 |
#if defined(CONFIG_USER_ONLY) |
|
| 210 | 209 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 211 | 210 |
{
|
| 212 |
return addr; |
|
| 213 |
} |
|
| 214 |
#else |
|
| 215 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
| 216 |
{
|
|
| 217 |
target_ulong phys_addr; |
|
| 218 |
int prot; |
|
| 211 |
if (env->user_mode_only) |
|
| 212 |
return addr; |
|
| 213 |
else {
|
|
| 214 |
target_ulong phys_addr; |
|
| 215 |
int prot; |
|
| 219 | 216 |
|
| 220 |
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
|
| 221 |
return -1; |
|
| 222 |
return phys_addr; |
|
| 217 |
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
|
| 218 |
return -1; |
|
| 219 |
return phys_addr; |
|
| 220 |
} |
|
| 223 | 221 |
} |
| 224 | 222 |
|
| 225 | 223 |
void cpu_mips_init_mmu (CPUState *env) |
| 226 | 224 |
{
|
| 227 | 225 |
} |
| 228 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
| 229 | 226 |
|
| 230 | 227 |
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 231 | 228 |
int mmu_idx, int is_softmmu) |
| ... | ... | |
| 318 | 315 |
return ret; |
| 319 | 316 |
} |
| 320 | 317 |
|
| 321 |
#if !defined(CONFIG_USER_ONLY) |
|
| 322 | 318 |
static const char * const excp_names[EXCP_LAST + 1] = {
|
| 323 | 319 |
[EXCP_RESET] = "reset", |
| 324 | 320 |
[EXCP_SRESET] = "soft reset", |
| ... | ... | |
| 354 | 350 |
[EXCP_C2E] = "precise coprocessor 2", |
| 355 | 351 |
[EXCP_CACHE] = "cache error", |
| 356 | 352 |
}; |
| 357 |
#endif |
|
| 358 | 353 |
|
| 359 | 354 |
void do_interrupt (CPUState *env) |
| 360 | 355 |
{
|
| 361 |
#if !defined(CONFIG_USER_ONLY) |
|
| 362 |
target_ulong offset; |
|
| 363 |
int cause = -1; |
|
| 364 |
const char *name; |
|
| 365 |
|
|
| 366 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
|
| 367 |
if (env->exception_index < 0 || env->exception_index > EXCP_LAST) |
|
| 368 |
name = "unknown"; |
|
| 369 |
else |
|
| 370 |
name = excp_names[env->exception_index]; |
|
| 371 |
|
|
| 372 |
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
|
| 373 |
__func__, env->active_tc.PC, env->CP0_EPC, name); |
|
| 374 |
} |
|
| 375 |
if (env->exception_index == EXCP_EXT_INTERRUPT && |
|
| 376 |
(env->hflags & MIPS_HFLAG_DM)) |
|
| 377 |
env->exception_index = EXCP_DINT; |
|
| 378 |
offset = 0x180; |
|
| 379 |
switch (env->exception_index) {
|
|
| 380 |
case EXCP_DSS: |
|
| 381 |
env->CP0_Debug |= 1 << CP0DB_DSS; |
|
| 382 |
/* Debug single step cannot be raised inside a delay slot and |
|
| 383 |
* resume will always occur on the next instruction |
|
| 384 |
* (but we assume the pc has always been updated during |
|
| 385 |
* code translation). |
|
| 386 |
*/ |
|
| 387 |
env->CP0_DEPC = env->active_tc.PC; |
|
| 388 |
goto enter_debug_mode; |
|
| 389 |
case EXCP_DINT: |
|
| 390 |
env->CP0_Debug |= 1 << CP0DB_DINT; |
|
| 391 |
goto set_DEPC; |
|
| 392 |
case EXCP_DIB: |
|
| 393 |
env->CP0_Debug |= 1 << CP0DB_DIB; |
|
| 394 |
goto set_DEPC; |
|
| 395 |
case EXCP_DBp: |
|
| 396 |
env->CP0_Debug |= 1 << CP0DB_DBp; |
|
| 397 |
goto set_DEPC; |
|
| 398 |
case EXCP_DDBS: |
|
| 399 |
env->CP0_Debug |= 1 << CP0DB_DDBS; |
|
| 400 |
goto set_DEPC; |
|
| 401 |
case EXCP_DDBL: |
|
| 402 |
env->CP0_Debug |= 1 << CP0DB_DDBL; |
|
| 403 |
set_DEPC: |
|
| 404 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 405 |
/* If the exception was raised from a delay slot, |
|
| 406 |
come back to the jump. */ |
|
| 407 |
env->CP0_DEPC = env->active_tc.PC - 4; |
|
| 408 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 409 |
} else {
|
|
| 410 |
env->CP0_DEPC = env->active_tc.PC; |
|
| 411 |
} |
|
| 412 |
enter_debug_mode: |
|
| 413 |
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
|
| 414 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
|
| 415 |
/* EJTAG probe trap enable is not implemented... */ |
|
| 416 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
|
| 417 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
|
| 418 |
env->active_tc.PC = (int32_t)0xBFC00480; |
|
| 419 |
break; |
|
| 420 |
case EXCP_RESET: |
|
| 421 |
cpu_reset(env); |
|
| 422 |
break; |
|
| 423 |
case EXCP_SRESET: |
|
| 424 |
env->CP0_Status |= (1 << CP0St_SR); |
|
| 425 |
memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
|
| 426 |
goto set_error_EPC; |
|
| 427 |
case EXCP_NMI: |
|
| 428 |
env->CP0_Status |= (1 << CP0St_NMI); |
|
| 429 |
set_error_EPC: |
|
| 430 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 431 |
/* If the exception was raised from a delay slot, |
|
| 432 |
come back to the jump. */ |
|
| 433 |
env->CP0_ErrorEPC = env->active_tc.PC - 4; |
|
| 434 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 435 |
} else {
|
|
| 436 |
env->CP0_ErrorEPC = env->active_tc.PC; |
|
| 437 |
} |
|
| 438 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
|
| 439 |
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
|
| 440 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
|
| 441 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
|
| 442 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
|
| 443 |
env->active_tc.PC = (int32_t)0xBFC00000; |
|
| 444 |
break; |
|
| 445 |
case EXCP_EXT_INTERRUPT: |
|
| 446 |
cause = 0; |
|
| 447 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
|
| 448 |
offset = 0x200; |
|
| 449 |
goto set_EPC; |
|
| 450 |
case EXCP_LTLBL: |
|
| 451 |
cause = 1; |
|
| 452 |
goto set_EPC; |
|
| 453 |
case EXCP_TLBL: |
|
| 454 |
cause = 2; |
|
| 455 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
| 456 |
#if defined(TARGET_MIPS64) |
|
| 457 |
int R = env->CP0_BadVAddr >> 62; |
|
| 458 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
|
| 459 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
|
| 460 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
|
| 356 |
if (!env->user_mode_only) {
|
|
| 357 |
target_ulong offset; |
|
| 358 |
int cause = -1; |
|
| 359 |
const char *name; |
|
| 461 | 360 |
|
| 462 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
|
| 463 |
offset = 0x080; |
|
| 361 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
|
| 362 |
if (env->exception_index < 0 || env->exception_index > EXCP_LAST) |
|
| 363 |
name = "unknown"; |
|
| 464 | 364 |
else |
| 465 |
#endif |
|
| 466 |
offset = 0x000; |
|
| 467 |
} |
|
| 468 |
goto set_EPC; |
|
| 469 |
case EXCP_TLBS: |
|
| 470 |
cause = 3; |
|
| 471 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
| 472 |
#if defined(TARGET_MIPS64) |
|
| 473 |
int R = env->CP0_BadVAddr >> 62; |
|
| 474 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
|
| 475 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
|
| 476 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
|
| 365 |
name = excp_names[env->exception_index]; |
|
| 477 | 366 |
|
| 478 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
|
| 479 |
offset = 0x080; |
|
| 480 |
else |
|
| 481 |
#endif |
|
| 482 |
offset = 0x000; |
|
| 483 |
} |
|
| 484 |
goto set_EPC; |
|
| 485 |
case EXCP_AdEL: |
|
| 486 |
cause = 4; |
|
| 487 |
goto set_EPC; |
|
| 488 |
case EXCP_AdES: |
|
| 489 |
cause = 5; |
|
| 490 |
goto set_EPC; |
|
| 491 |
case EXCP_IBE: |
|
| 492 |
cause = 6; |
|
| 493 |
goto set_EPC; |
|
| 494 |
case EXCP_DBE: |
|
| 495 |
cause = 7; |
|
| 496 |
goto set_EPC; |
|
| 497 |
case EXCP_SYSCALL: |
|
| 498 |
cause = 8; |
|
| 499 |
goto set_EPC; |
|
| 500 |
case EXCP_BREAK: |
|
| 501 |
cause = 9; |
|
| 502 |
goto set_EPC; |
|
| 503 |
case EXCP_RI: |
|
| 504 |
cause = 10; |
|
| 505 |
goto set_EPC; |
|
| 506 |
case EXCP_CpU: |
|
| 507 |
cause = 11; |
|
| 508 |
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
|
| 509 |
(env->error_code << CP0Ca_CE); |
|
| 510 |
goto set_EPC; |
|
| 511 |
case EXCP_OVERFLOW: |
|
| 512 |
cause = 12; |
|
| 513 |
goto set_EPC; |
|
| 514 |
case EXCP_TRAP: |
|
| 515 |
cause = 13; |
|
| 516 |
goto set_EPC; |
|
| 517 |
case EXCP_FPE: |
|
| 518 |
cause = 15; |
|
| 519 |
goto set_EPC; |
|
| 520 |
case EXCP_C2E: |
|
| 521 |
cause = 18; |
|
| 522 |
goto set_EPC; |
|
| 523 |
case EXCP_MDMX: |
|
| 524 |
cause = 22; |
|
| 525 |
goto set_EPC; |
|
| 526 |
case EXCP_DWATCH: |
|
| 527 |
cause = 23; |
|
| 528 |
/* XXX: TODO: manage defered watch exceptions */ |
|
| 529 |
goto set_EPC; |
|
| 530 |
case EXCP_MCHECK: |
|
| 531 |
cause = 24; |
|
| 532 |
goto set_EPC; |
|
| 533 |
case EXCP_THREAD: |
|
| 534 |
cause = 25; |
|
| 535 |
goto set_EPC; |
|
| 536 |
case EXCP_CACHE: |
|
| 537 |
cause = 30; |
|
| 538 |
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
| 539 |
offset = 0x100; |
|
| 540 |
} else {
|
|
| 541 |
offset = 0x20000100; |
|
| 367 |
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
|
| 368 |
__func__, env->active_tc.PC, env->CP0_EPC, name); |
|
| 542 | 369 |
} |
| 543 |
set_EPC: |
|
| 544 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
| 370 |
if (env->exception_index == EXCP_EXT_INTERRUPT && |
|
| 371 |
(env->hflags & MIPS_HFLAG_DM)) |
|
| 372 |
env->exception_index = EXCP_DINT; |
|
| 373 |
offset = 0x180; |
|
| 374 |
switch (env->exception_index) {
|
|
| 375 |
case EXCP_DSS: |
|
| 376 |
env->CP0_Debug |= 1 << CP0DB_DSS; |
|
| 377 |
/* Debug single step cannot be raised inside a delay slot and |
|
| 378 |
resume will always occur on the next instruction |
|
| 379 |
(but we assume the pc has always been updated during |
|
| 380 |
code translation). */ |
|
| 381 |
env->CP0_DEPC = env->active_tc.PC; |
|
| 382 |
goto enter_debug_mode; |
|
| 383 |
case EXCP_DINT: |
|
| 384 |
env->CP0_Debug |= 1 << CP0DB_DINT; |
|
| 385 |
goto set_DEPC; |
|
| 386 |
case EXCP_DIB: |
|
| 387 |
env->CP0_Debug |= 1 << CP0DB_DIB; |
|
| 388 |
goto set_DEPC; |
|
| 389 |
case EXCP_DBp: |
|
| 390 |
env->CP0_Debug |= 1 << CP0DB_DBp; |
|
| 391 |
goto set_DEPC; |
|
| 392 |
case EXCP_DDBS: |
|
| 393 |
env->CP0_Debug |= 1 << CP0DB_DDBS; |
|
| 394 |
goto set_DEPC; |
|
| 395 |
case EXCP_DDBL: |
|
| 396 |
env->CP0_Debug |= 1 << CP0DB_DDBL; |
|
| 397 |
set_DEPC: |
|
| 545 | 398 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 546 | 399 |
/* If the exception was raised from a delay slot, |
| 547 | 400 |
come back to the jump. */ |
| 548 |
env->CP0_EPC = env->active_tc.PC - 4; |
|
| 549 |
env->CP0_Cause |= (1 << CP0Ca_BD);
|
|
| 401 |
env->CP0_DEPC = env->active_tc.PC - 4;
|
|
| 402 |
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
| 550 | 403 |
} else {
|
| 551 |
env->CP0_EPC = env->active_tc.PC; |
|
| 404 |
env->CP0_DEPC = env->active_tc.PC; |
|
| 405 |
} |
|
| 406 |
enter_debug_mode: |
|
| 407 |
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
|
| 408 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
|
| 409 |
/* EJTAG probe trap enable is not implemented... */ |
|
| 410 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
|
| 552 | 411 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
| 412 |
env->active_tc.PC = (int32_t)0xBFC00480; |
|
| 413 |
break; |
|
| 414 |
case EXCP_RESET: |
|
| 415 |
cpu_reset(env); |
|
| 416 |
break; |
|
| 417 |
case EXCP_SRESET: |
|
| 418 |
env->CP0_Status |= (1 << CP0St_SR); |
|
| 419 |
memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
|
| 420 |
goto set_error_EPC; |
|
| 421 |
case EXCP_NMI: |
|
| 422 |
env->CP0_Status |= (1 << CP0St_NMI); |
|
| 423 |
set_error_EPC: |
|
| 424 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 425 |
/* If the exception was raised from a delay slot, |
|
| 426 |
come back to the jump. */ |
|
| 427 |
env->CP0_ErrorEPC = env->active_tc.PC - 4; |
|
| 428 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 429 |
} else {
|
|
| 430 |
env->CP0_ErrorEPC = env->active_tc.PC; |
|
| 553 | 431 |
} |
| 554 |
env->CP0_Status |= (1 << CP0St_EXL);
|
|
| 432 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
|
|
| 555 | 433 |
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
| 556 | 434 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
| 435 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
|
| 436 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
|
| 437 |
env->active_tc.PC = (int32_t)0xBFC00000; |
|
| 438 |
break; |
|
| 439 |
case EXCP_EXT_INTERRUPT: |
|
| 440 |
cause = 0; |
|
| 441 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
|
| 442 |
offset = 0x200; |
|
| 443 |
goto set_EPC; |
|
| 444 |
case EXCP_LTLBL: |
|
| 445 |
cause = 1; |
|
| 446 |
goto set_EPC; |
|
| 447 |
case EXCP_TLBL: |
|
| 448 |
cause = 2; |
|
| 449 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
| 450 |
#if defined(TARGET_MIPS64) |
|
| 451 |
int R = env->CP0_BadVAddr >> 62; |
|
| 452 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
|
| 453 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
|
| 454 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
|
| 455 |
|
|
| 456 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
|
| 457 |
offset = 0x080; |
|
| 458 |
else |
|
| 459 |
#endif |
|
| 460 |
offset = 0x000; |
|
| 461 |
} |
|
| 462 |
goto set_EPC; |
|
| 463 |
case EXCP_TLBS: |
|
| 464 |
cause = 3; |
|
| 465 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
| 466 |
#if defined(TARGET_MIPS64) |
|
| 467 |
int R = env->CP0_BadVAddr >> 62; |
|
| 468 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
|
| 469 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
|
| 470 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
|
| 471 |
|
|
| 472 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
|
| 473 |
offset = 0x080; |
|
| 474 |
else |
|
| 475 |
#endif |
|
| 476 |
offset = 0x000; |
|
| 477 |
} |
|
| 478 |
goto set_EPC; |
|
| 479 |
case EXCP_AdEL: |
|
| 480 |
cause = 4; |
|
| 481 |
goto set_EPC; |
|
| 482 |
case EXCP_AdES: |
|
| 483 |
cause = 5; |
|
| 484 |
goto set_EPC; |
|
| 485 |
case EXCP_IBE: |
|
| 486 |
cause = 6; |
|
| 487 |
goto set_EPC; |
|
| 488 |
case EXCP_DBE: |
|
| 489 |
cause = 7; |
|
| 490 |
goto set_EPC; |
|
| 491 |
case EXCP_SYSCALL: |
|
| 492 |
cause = 8; |
|
| 493 |
goto set_EPC; |
|
| 494 |
case EXCP_BREAK: |
|
| 495 |
cause = 9; |
|
| 496 |
goto set_EPC; |
|
| 497 |
case EXCP_RI: |
|
| 498 |
cause = 10; |
|
| 499 |
goto set_EPC; |
|
| 500 |
case EXCP_CpU: |
|
| 501 |
cause = 11; |
|
| 502 |
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
|
| 503 |
(env->error_code << CP0Ca_CE); |
|
| 504 |
goto set_EPC; |
|
| 505 |
case EXCP_OVERFLOW: |
|
| 506 |
cause = 12; |
|
| 507 |
goto set_EPC; |
|
| 508 |
case EXCP_TRAP: |
|
| 509 |
cause = 13; |
|
| 510 |
goto set_EPC; |
|
| 511 |
case EXCP_FPE: |
|
| 512 |
cause = 15; |
|
| 513 |
goto set_EPC; |
|
| 514 |
case EXCP_C2E: |
|
| 515 |
cause = 18; |
|
| 516 |
goto set_EPC; |
|
| 517 |
case EXCP_MDMX: |
|
| 518 |
cause = 22; |
|
| 519 |
goto set_EPC; |
|
| 520 |
case EXCP_DWATCH: |
|
| 521 |
cause = 23; |
|
| 522 |
/* XXX: TODO: manage defered watch exceptions */ |
|
| 523 |
goto set_EPC; |
|
| 524 |
case EXCP_MCHECK: |
|
| 525 |
cause = 24; |
|
| 526 |
goto set_EPC; |
|
| 527 |
case EXCP_THREAD: |
|
| 528 |
cause = 25; |
|
| 529 |
goto set_EPC; |
|
| 530 |
case EXCP_CACHE: |
|
| 531 |
cause = 30; |
|
| 532 |
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
| 533 |
offset = 0x100; |
|
| 534 |
} else {
|
|
| 535 |
offset = 0x20000100; |
|
| 536 |
} |
|
| 537 |
set_EPC: |
|
| 538 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
| 539 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 540 |
/* If the exception was raised from a delay slot, |
|
| 541 |
come back to the jump. */ |
|
| 542 |
env->CP0_EPC = env->active_tc.PC - 4; |
|
| 543 |
env->CP0_Cause |= (1 << CP0Ca_BD); |
|
| 544 |
} else {
|
|
| 545 |
env->CP0_EPC = env->active_tc.PC; |
|
| 546 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
|
| 547 |
} |
|
| 548 |
env->CP0_Status |= (1 << CP0St_EXL); |
|
| 549 |
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
|
| 550 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
|
| 551 |
} |
|
| 552 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 553 |
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
| 554 |
env->active_tc.PC = (int32_t)0xBFC00200; |
|
| 555 |
} else {
|
|
| 556 |
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); |
|
| 557 |
} |
|
| 558 |
env->active_tc.PC += offset; |
|
| 559 |
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
|
| 560 |
break; |
|
| 561 |
default: |
|
| 562 |
if (logfile) {
|
|
| 563 |
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n", |
|
| 564 |
env->exception_index); |
|
| 565 |
} |
|
| 566 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
|
| 567 |
exit(1); |
|
| 557 | 568 |
} |
| 558 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 559 |
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
| 560 |
env->active_tc.PC = (int32_t)0xBFC00200; |
|
| 561 |
} else {
|
|
| 562 |
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); |
|
| 563 |
} |
|
| 564 |
env->active_tc.PC += offset; |
|
| 565 |
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
|
| 566 |
break; |
|
| 567 |
default: |
|
| 568 |
if (logfile) {
|
|
| 569 |
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n", |
|
| 570 |
env->exception_index); |
|
| 569 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
|
| 570 |
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
|
| 571 |
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
|
| 572 |
__func__, env->active_tc.PC, env->CP0_EPC, cause, |
|
| 573 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
|
| 574 |
env->CP0_DEPC); |
|
| 571 | 575 |
} |
| 572 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
|
| 573 |
exit(1); |
|
| 574 |
} |
|
| 575 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
|
| 576 |
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
|
| 577 |
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
|
| 578 |
__func__, env->active_tc.PC, env->CP0_EPC, cause, |
|
| 579 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
|
| 580 |
env->CP0_DEPC); |
|
| 581 | 576 |
} |
| 582 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
| 583 | 577 |
env->exception_index = EXCP_NONE; |
| 584 | 578 |
} |
| 585 | 579 |
|
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