Revision 0eaef5aa target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
|---|---|---|
| 439 | 439 |
} |
| 440 | 440 |
} |
| 441 | 441 |
|
| 442 |
#ifndef CONFIG_USER_ONLY |
|
| 443 | 442 |
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
| 444 | 443 |
{
|
| 445 | 444 |
env->tlb->nb_tlb = 1; |
| ... | ... | |
| 485 | 484 |
env->CP0_Random = env->tlb->nb_tlb - 1; |
| 486 | 485 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
| 487 | 486 |
} |
| 488 |
#endif /* CONFIG_USER_ONLY */ |
|
| 489 | 487 |
|
| 490 | 488 |
static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
| 491 | 489 |
{
|
| 492 | 490 |
env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext)); |
| 493 | 491 |
|
| 494 | 492 |
env->fpu->fcr0 = def->CP1_fcr0; |
| 495 |
#ifdef CONFIG_USER_ONLY
|
|
| 496 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
|
| 497 |
env->hflags |= MIPS_HFLAG_FPU; |
|
| 493 |
if (env->user_mode_only) {
|
|
| 494 |
if (env->CP0_Config1 & (1 << CP0C1_FP))
|
|
| 495 |
env->hflags |= MIPS_HFLAG_FPU;
|
|
| 498 | 496 |
#ifdef TARGET_MIPS64 |
| 499 |
if (env->fpu->fcr0 & (1 << FCR0_F64)) |
|
| 500 |
env->hflags |= MIPS_HFLAG_F64; |
|
| 501 |
#endif |
|
| 497 |
if (env->fpu->fcr0 & (1 << FCR0_F64)) |
|
| 498 |
env->hflags |= MIPS_HFLAG_F64; |
|
| 502 | 499 |
#endif |
| 500 |
} |
|
| 503 | 501 |
} |
| 504 | 502 |
|
| 505 | 503 |
static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
| ... | ... | |
| 512 | 510 |
implemented, 5 TCs implemented. */ |
| 513 | 511 |
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
| 514 | 512 |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
| 515 |
#ifndef CONFIG_USER_ONLY |
|
| 516 |
/* Usermode has no TLB support */ |
|
| 517 |
(env->tlb->nb_tlb << CP0MVPC0_PTLBE) | |
|
| 518 |
#endif |
|
| 519 | 513 |
// TODO: actually do 2 VPEs. |
| 520 | 514 |
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | |
| 521 | 515 |
// (0x04 << CP0MVPC0_PTC); |
| 522 | 516 |
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
| 523 | 517 |
(0x04 << CP0MVPC0_PTC); |
| 518 |
/* Usermode has no TLB support */ |
|
| 519 |
if (!env->user_mode_only) |
|
| 520 |
env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
|
| 521 |
|
|
| 524 | 522 |
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
| 525 | 523 |
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
| 526 | 524 |
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
| ... | ... | |
| 568 | 566 |
env->CP0_SRSConf4 = def->CP0_SRSConf4; |
| 569 | 567 |
env->insn_flags = def->insn_flags; |
| 570 | 568 |
|
| 571 |
#ifndef CONFIG_USER_ONLY |
|
| 572 |
mmu_init(env, def); |
|
| 573 |
#endif |
|
| 569 |
if (!env->user_mode_only) |
|
| 570 |
mmu_init(env, def); |
|
| 574 | 571 |
fpu_init(env, def); |
| 575 | 572 |
mvp_init(env, def); |
| 576 | 573 |
return 0; |
Also available in: Unified diff