Revision 0ef849d7

b/hw/realview.c
16 16
#include "sysemu.h"
17 17
#include "boards.h"
18 18

  
19
#define SMP_BOOT_ADDR 0xe0000000
19 20
/* Board init.  */
20 21

  
21 22
static struct arm_boot_info realview_binfo = {
22
    .loader_start = 0x0,
23
    .smp_loader_start = 0x80000000,
24
    .board_id = 0x33b,
23
    .smp_loader_start = SMP_BOOT_ADDR,
25 24
};
26 25

  
27 26
static void secondary_cpu_reset(void *opaque)
......
32 31
  /* Set entry point for secondary CPUs.  This assumes we're using
33 32
     the init code from arm_boot.c.  Real hardware resets all CPUs
34 33
     the same.  */
35
  env->regs[15] = 0x80000000;
34
  env->regs[15] = SMP_BOOT_ADDR;
36 35
}
37 36

  
38 37
enum realview_board_type {
39 38
    BOARD_EB,
40
    BOARD_EB_MPCORE
39
    BOARD_EB_MPCORE,
40
    BOARD_PB_A8
41 41
};
42 42

  
43 43
static void realview_init(ram_addr_t ram_size,
......
55 55
    PCIBus *pci_bus;
56 56
    NICInfo *nd;
57 57
    int n;
58
    int done_smc = 0;
58
    int done_nic = 0;
59 59
    qemu_irq cpu_irq[4];
60 60
    int is_mpcore = (board_type == BOARD_EB_MPCORE);
61
    int is_pb = (board_type == BOARD_PB_A8);
61 62
    uint32_t proc_id = 0;
63
    uint32_t sys_id;
64
    ram_addr_t low_ram_size;
62 65

  
63 66
    for (n = 0; n < smp_cpus; n++) {
64 67
        env = cpu_init(cpu_model);
......
83 86
    }
84 87

  
85 88
    ram_offset = qemu_ram_alloc(ram_size);
89
    low_ram_size = ram_size;
90
    if (low_ram_size > 0x10000000)
91
      low_ram_size = 0x10000000;
86 92
    /* ??? RAM should repeat to fill physical memory space.  */
87 93
    /* SDRAM at address zero.  */
88
    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
94
    cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
95
    if (is_pb) {
96
        /* And again at a high address.  */
97
        cpu_register_physical_memory(0x70000000, ram_size,
98
                                     ram_offset | IO_MEM_RAM);
99
    } else {
100
        ram_size = low_ram_size;
101
    }
89 102

  
90
    arm_sysctl_init(0x10000000, 0xc1400400, proc_id);
103
    sys_id = is_pb ? 0x01780500 : 0xc1400400;
104
    arm_sysctl_init(0x10000000, sys_id, proc_id);
91 105

  
92 106
    if (is_mpcore) {
93 107
        dev = qdev_create(NULL, "realview_mpcore");
......
98 112
            sysbus_connect_irq(busdev, n, cpu_irq[n]);
99 113
        }
100 114
    } else {
101
        dev = sysbus_create_simple("realview_gic", 0x10040000, cpu_irq[0]);
115
        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
116
        /* For now just create the nIRQ GIC, and ignore the others.  */
117
        dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
102 118
    }
103 119
    for (n = 0; n < 64; n++) {
104 120
        pic[n] = qdev_get_gpio_in(dev, n);
......
124 140

  
125 141
    sysbus_create_simple("pl031", 0x10017000, pic[10]);
126 142

  
127
    dev = sysbus_create_varargs("realview_pci", 0x60000000,
128
                                pic[48], pic[49], pic[50], pic[51], NULL);
129
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
130
    if (usb_enabled) {
131
        usb_ohci_init_pci(pci_bus, -1);
132
    }
133
    n = drive_get_max_bus(IF_SCSI);
134
    while (n >= 0) {
135
        pci_create_simple(pci_bus, -1, "lsi53c895a");
136
        n--;
143
    if (!is_pb) {
144
        dev = sysbus_create_varargs("realview_pci", 0x60000000,
145
                                    pic[48], pic[49], pic[50], pic[51], NULL);
146
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
147
        if (usb_enabled) {
148
            usb_ohci_init_pci(pci_bus, -1);
149
        }
150
        n = drive_get_max_bus(IF_SCSI);
151
        while (n >= 0) {
152
            pci_create_simple(pci_bus, -1, "lsi53c895a");
153
            n--;
154
        }
137 155
    }
138 156
    for(n = 0; n < nb_nics; n++) {
139 157
        nd = &nd_table[n];
140 158

  
141
        if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) {
142
            smc91c111_init(nd, 0x4e000000, pic[28]);
143
            done_smc = 1;
159
        if ((!nd->model && !done_nic)
160
            || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
161
            if (is_pb) {
162
                lan9118_init(nd, 0x4e000000, pic[28]);
163
            } else {
164
                smc91c111_init(nd, 0x4e000000, pic[28]);
165
            }
166
            done_nic = 1;
144 167
        } else {
145 168
            pci_nic_init_nofail(nd, "rtl8139", NULL);
146 169
        }
......
155 178
    /*  0x10005000 MCI.  */
156 179
    /* 0x10006000 KMI0.  */
157 180
    /* 0x10007000 KMI1.  */
158
    /*  0x10008000 Character LCD.  */
181
    /*  0x10008000 Character LCD. (EB) */
159 182
    /* 0x10009000 UART0.  */
160 183
    /* 0x1000a000 UART1.  */
161 184
    /* 0x1000b000 UART2.  */
......
169 192
    /*  0x10013000 GPIO 0.  */
170 193
    /*  0x10014000 GPIO 1.  */
171 194
    /*  0x10015000 GPIO 2.  */
172
    /* 0x10016000 Reserved.  */
195
    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
173 196
    /* 0x10017000 RTC.  */
174 197
    /*  0x10018000 DMC.  */
175 198
    /*  0x10019000 PCI controller config.  */
176 199
    /*  0x10020000 CLCD.  */
177 200
    /* 0x10030000 DMA Controller.  */
178
    /* 0x10040000 GIC1.  */
179
    /* 0x10050000 GIC2.  */
180
    /* 0x10060000 GIC3.  */
181
    /* 0x10070000 GIC4.  */
201
    /* 0x10040000 GIC1. (EB) */
202
    /*  0x10050000 GIC2. (EB) */
203
    /*  0x10060000 GIC3. (EB) */
204
    /*  0x10070000 GIC4. (EB) */
182 205
    /*  0x10080000 SMC.  */
206
    /* 0x1e000000 GIC1. (PB) */
207
    /*  0x1e001000 GIC2. (PB) */
208
    /*  0x1e002000 GIC3. (PB) */
209
    /*  0x1e003000 GIC4. (PB) */
183 210
    /*  0x40000000 NOR flash.  */
184 211
    /*  0x44000000 DoC flash.  */
185 212
    /*  0x48000000 SRAM.  */
......
203 230
       BootROM happens to be in ROM/flash or in memory that isn't clobbered
204 231
       until after Linux boots the secondary CPUs.  */
205 232
    ram_offset = qemu_ram_alloc(0x1000);
206
    cpu_register_physical_memory(0x80000000, 0x1000, ram_offset | IO_MEM_RAM);
233
    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
234
                                 ram_offset | IO_MEM_RAM);
207 235

  
208 236
    realview_binfo.ram_size = ram_size;
209 237
    realview_binfo.kernel_filename = kernel_filename;
210 238
    realview_binfo.kernel_cmdline = kernel_cmdline;
211 239
    realview_binfo.initrd_filename = initrd_filename;
212 240
    realview_binfo.nb_cpus = smp_cpus;
241
    realview_binfo.board_id = is_pb ? 0x769 : 0x33b;
242
    realview_binfo.loader_start = is_pb ? 0x70000000 : 0;
213 243
    arm_load_kernel(first_cpu, &realview_binfo);
214 244
}
215 245

  
......
237 267
                  initrd_filename, cpu_model, BOARD_EB_MPCORE);
238 268
}
239 269

  
270
static void realview_pb_a8_init(ram_addr_t ram_size,
271
                     const char *boot_device,
272
                     const char *kernel_filename, const char *kernel_cmdline,
273
                     const char *initrd_filename, const char *cpu_model)
274
{
275
    if (!cpu_model) {
276
        cpu_model = "cortex-a8";
277
    }
278
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
279
                  initrd_filename, cpu_model, BOARD_PB_A8);
280
}
281

  
240 282
static QEMUMachine realview_eb_machine = {
241 283
    .name = "realview-eb",
242 284
    .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
......
252 294
    .max_cpus = 4,
253 295
};
254 296

  
297
static QEMUMachine realview_pb_a8_machine = {
298
    .name = "realview-pb-a8",
299
    .desc = "ARM RealView Platform Baseboard for Cortex-A8",
300
    .init = realview_pb_a8_init,
301
    .use_scsi = 1,
302
};
303

  
255 304
static void realview_machine_init(void)
256 305
{
257 306
    qemu_register_machine(&realview_eb_machine);
258 307
    qemu_register_machine(&realview_eb_mpcore_machine);
308
    qemu_register_machine(&realview_pb_a8_machine);
259 309
}
260 310

  
261 311
machine_init(realview_machine_init);
b/qemu-doc.texi
80 80
@item MIPS Magnum (64-bit MIPS processor)
81 81
@item ARM Integrator/CP (ARM)
82 82
@item ARM Versatile baseboard (ARM)
83
@item ARM RealView Emulation baseboard (ARM)
83
@item ARM RealView Emulation/Platform baseboard (ARM)
84 84
@item Spitz, Akita, Borzoi, Terrier and Tosa PDAs (PXA270 processor)
85 85
@item Luminary Micro LM3S811EVB (ARM Cortex-M3)
86 86
@item Luminary Micro LM3S6965EVB (ARM Cortex-M3)
......
1659 1659
PL181 MultiMedia Card Interface with SD card.
1660 1660
@end itemize
1661 1661

  
1662
The ARM RealView Emulation baseboard is emulated with the following devices:
1662
The ARM RealView Emulation/Platform baseboard is emulated with the following
1663
devices:
1663 1664

  
1664 1665
@itemize @minus
1665 1666
@item
......
1669 1670
@item
1670 1671
Four PL011 UARTs
1671 1672
@item
1672
SMC 91c111 Ethernet adapter
1673
SMC 91c111 or SMSC LAN9118 Ethernet adapter
1673 1674
@item
1674 1675
PL110 LCD controller
1675 1676
@item

Also available in: Unified diff