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/*
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 * ARM RealView Baseboard System emulation.
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 *
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 * Copyright (c) 2006-2007 CodeSourcery.
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 * Written by Paul Brook
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 *
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 * This code is licenced under the GPL.
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 */
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "primecell.h"
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#include "devices.h"
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#include "pci.h"
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#include "net.h"
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#include "sysemu.h"
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#include "boards.h"
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#define SMP_BOOT_ADDR 0xe0000000
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/* Board init.  */
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static struct arm_boot_info realview_binfo = {
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    .smp_loader_start = SMP_BOOT_ADDR,
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};
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static void secondary_cpu_reset(void *opaque)
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{
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  CPUState *env = opaque;
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  cpu_reset(env);
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  /* Set entry point for secondary CPUs.  This assumes we're using
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     the init code from arm_boot.c.  Real hardware resets all CPUs
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     the same.  */
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  env->regs[15] = SMP_BOOT_ADDR;
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}
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enum realview_board_type {
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    BOARD_EB,
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    BOARD_EB_MPCORE,
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    BOARD_PB_A8
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};
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static void realview_init(ram_addr_t ram_size,
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                     const char *boot_device,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model,
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                     enum realview_board_type board_type)
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{
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    CPUState *env = NULL;
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    ram_addr_t ram_offset;
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    DeviceState *dev;
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    SysBusDevice *busdev;
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    qemu_irq *irqp;
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    qemu_irq pic[64];
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    PCIBus *pci_bus;
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    NICInfo *nd;
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    int n;
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    int done_nic = 0;
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    qemu_irq cpu_irq[4];
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    int is_mpcore = (board_type == BOARD_EB_MPCORE);
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    int is_pb = (board_type == BOARD_PB_A8);
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    uint32_t proc_id = 0;
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    uint32_t sys_id;
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    ram_addr_t low_ram_size;
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    for (n = 0; n < smp_cpus; n++) {
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        env = cpu_init(cpu_model);
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        if (!env) {
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            fprintf(stderr, "Unable to find CPU definition\n");
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            exit(1);
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        }
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        irqp = arm_pic_init_cpu(env);
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        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
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        if (n > 0) {
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            qemu_register_reset(secondary_cpu_reset, env);
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        }
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    }
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    if (arm_feature(env, ARM_FEATURE_V7)) {
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        proc_id = 0x0e000000;
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    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
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        proc_id = 0x06000000;
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    } else if (arm_feature(env, ARM_FEATURE_V6)) {
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        proc_id = 0x04000000;
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    } else {
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        proc_id = 0x02000000;
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    }
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    ram_offset = qemu_ram_alloc(ram_size);
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    low_ram_size = ram_size;
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    if (low_ram_size > 0x10000000)
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      low_ram_size = 0x10000000;
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    /* ??? RAM should repeat to fill physical memory space.  */
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    /* SDRAM at address zero.  */
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    cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
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    if (is_pb) {
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        /* And again at a high address.  */
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        cpu_register_physical_memory(0x70000000, ram_size,
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                                     ram_offset | IO_MEM_RAM);
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    } else {
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        ram_size = low_ram_size;
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    }
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    sys_id = is_pb ? 0x01780500 : 0xc1400400;
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    arm_sysctl_init(0x10000000, sys_id, proc_id);
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    if (is_mpcore) {
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        dev = qdev_create(NULL, "realview_mpcore");
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        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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        qdev_init_nofail(dev);
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        busdev = sysbus_from_qdev(dev);
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        for (n = 0; n < smp_cpus; n++) {
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            sysbus_connect_irq(busdev, n, cpu_irq[n]);
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        }
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    } else {
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        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
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        /* For now just create the nIRQ GIC, and ignore the others.  */
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        dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
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    }
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    for (n = 0; n < 64; n++) {
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        pic[n] = qdev_get_gpio_in(dev, n);
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    }
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    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
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    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
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    sysbus_create_simple("pl011", 0x10009000, pic[12]);
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    sysbus_create_simple("pl011", 0x1000a000, pic[13]);
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    sysbus_create_simple("pl011", 0x1000b000, pic[14]);
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    sysbus_create_simple("pl011", 0x1000c000, pic[15]);
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    /* DMA controller is optional, apparently.  */
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    sysbus_create_simple("pl081", 0x10030000, pic[24]);
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    sysbus_create_simple("sp804", 0x10011000, pic[4]);
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    sysbus_create_simple("sp804", 0x10012000, pic[5]);
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    sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
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    sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
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    sysbus_create_simple("pl031", 0x10017000, pic[10]);
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    if (!is_pb) {
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        dev = sysbus_create_varargs("realview_pci", 0x60000000,
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                                    pic[48], pic[49], pic[50], pic[51], NULL);
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        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
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        if (usb_enabled) {
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            usb_ohci_init_pci(pci_bus, -1);
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        }
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        n = drive_get_max_bus(IF_SCSI);
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        while (n >= 0) {
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            pci_create_simple(pci_bus, -1, "lsi53c895a");
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            n--;
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        }
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    }
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    for(n = 0; n < nb_nics; n++) {
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        nd = &nd_table[n];
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        if ((!nd->model && !done_nic)
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            || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
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            if (is_pb) {
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                lan9118_init(nd, 0x4e000000, pic[28]);
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            } else {
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                smc91c111_init(nd, 0x4e000000, pic[28]);
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            }
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            done_nic = 1;
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        } else {
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            pci_nic_init_nofail(nd, "rtl8139", NULL);
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        }
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    }
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    /* Memory map for RealView Emulation Baseboard:  */
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    /* 0x10000000 System registers.  */
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    /*  0x10001000 System controller.  */
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    /*  0x10002000 Two-Wire Serial Bus.  */
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    /* 0x10003000 Reserved.  */
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    /*  0x10004000 AACI.  */
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    /*  0x10005000 MCI.  */
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    /* 0x10006000 KMI0.  */
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    /* 0x10007000 KMI1.  */
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    /*  0x10008000 Character LCD. (EB) */
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    /* 0x10009000 UART0.  */
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    /* 0x1000a000 UART1.  */
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    /* 0x1000b000 UART2.  */
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    /* 0x1000c000 UART3.  */
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    /*  0x1000d000 SSPI.  */
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    /*  0x1000e000 SCI.  */
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    /* 0x1000f000 Reserved.  */
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    /*  0x10010000 Watchdog.  */
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    /* 0x10011000 Timer 0+1.  */
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    /* 0x10012000 Timer 2+3.  */
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    /*  0x10013000 GPIO 0.  */
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    /*  0x10014000 GPIO 1.  */
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    /*  0x10015000 GPIO 2.  */
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    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
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    /* 0x10017000 RTC.  */
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    /*  0x10018000 DMC.  */
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    /*  0x10019000 PCI controller config.  */
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    /*  0x10020000 CLCD.  */
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    /* 0x10030000 DMA Controller.  */
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    /* 0x10040000 GIC1. (EB) */
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    /*  0x10050000 GIC2. (EB) */
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    /*  0x10060000 GIC3. (EB) */
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    /*  0x10070000 GIC4. (EB) */
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    /*  0x10080000 SMC.  */
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    /* 0x1e000000 GIC1. (PB) */
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    /*  0x1e001000 GIC2. (PB) */
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    /*  0x1e002000 GIC3. (PB) */
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    /*  0x1e003000 GIC4. (PB) */
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    /*  0x40000000 NOR flash.  */
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    /*  0x44000000 DoC flash.  */
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    /*  0x48000000 SRAM.  */
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    /*  0x4c000000 Configuration flash.  */
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    /* 0x4e000000 Ethernet.  */
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    /*  0x4f000000 USB.  */
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    /*  0x50000000 PISMO.  */
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    /*  0x54000000 PISMO.  */
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    /*  0x58000000 PISMO.  */
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    /*  0x5c000000 PISMO.  */
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    /* 0x60000000 PCI.  */
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    /* 0x61000000 PCI Self Config.  */
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    /* 0x62000000 PCI Config.  */
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    /* 0x63000000 PCI IO.  */
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    /* 0x64000000 PCI mem 0.  */
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    /* 0x68000000 PCI mem 1.  */
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    /* 0x6c000000 PCI mem 2.  */
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    /* ??? Hack to map an additional page of ram for the secondary CPU
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       startup code.  I guess this works on real hardware because the
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       BootROM happens to be in ROM/flash or in memory that isn't clobbered
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       until after Linux boots the secondary CPUs.  */
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    ram_offset = qemu_ram_alloc(0x1000);
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    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
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                                 ram_offset | IO_MEM_RAM);
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    realview_binfo.ram_size = ram_size;
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    realview_binfo.kernel_filename = kernel_filename;
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    realview_binfo.kernel_cmdline = kernel_cmdline;
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    realview_binfo.initrd_filename = initrd_filename;
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    realview_binfo.nb_cpus = smp_cpus;
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    realview_binfo.board_id = is_pb ? 0x769 : 0x33b;
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    realview_binfo.loader_start = is_pb ? 0x70000000 : 0;
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    arm_load_kernel(first_cpu, &realview_binfo);
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}
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static void realview_eb_init(ram_addr_t ram_size,
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                     const char *boot_device,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model)
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{
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    if (!cpu_model) {
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        cpu_model = "arm926";
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    }
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    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
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                  initrd_filename, cpu_model, BOARD_EB);
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}
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static void realview_eb_mpcore_init(ram_addr_t ram_size,
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                     const char *boot_device,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model)
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{
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    if (!cpu_model) {
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        cpu_model = "arm11mpcore";
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    }
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    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
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                  initrd_filename, cpu_model, BOARD_EB_MPCORE);
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}
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static void realview_pb_a8_init(ram_addr_t ram_size,
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                     const char *boot_device,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model)
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{
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    if (!cpu_model) {
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        cpu_model = "cortex-a8";
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    }
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    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
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                  initrd_filename, cpu_model, BOARD_PB_A8);
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}
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static QEMUMachine realview_eb_machine = {
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    .name = "realview-eb",
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    .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
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    .init = realview_eb_init,
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    .use_scsi = 1,
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};
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static QEMUMachine realview_eb_mpcore_machine = {
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    .name = "realview-eb-mpcore",
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    .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
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    .init = realview_eb_mpcore_init,
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    .use_scsi = 1,
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    .max_cpus = 4,
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};
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static QEMUMachine realview_pb_a8_machine = {
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    .name = "realview-pb-a8",
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    .desc = "ARM RealView Platform Baseboard for Cortex-A8",
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    .init = realview_pb_a8_init,
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    .use_scsi = 1,
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};
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static void realview_machine_init(void)
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{
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    qemu_register_machine(&realview_eb_machine);
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    qemu_register_machine(&realview_eb_mpcore_machine);
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    qemu_register_machine(&realview_pb_a8_machine);
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}
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machine_init(realview_machine_init);