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tcg/arm: improve constant loading
Improve constant loading in two ways:- On all ARM versions, it's possible to load 0xffffff00 = 0x100 using the mvn rd, #0. Fix the conditions. On <= ARMv6 versions, where movw and movt are not available, load the constants using mov and orr with rotations depending on the constant...
tcg/arm: fix qemu_st64 for big endian targets
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word ofa 64 bit word before saving it. This patch fixes that.
Acked-by: Andrzej Zaborowski <balrogg@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: fix branch target change during code retranslation
QEMU uses code retranslation to restore the CPU state when an exceptionhappens. For it to work the retranslation must not modify the generatedcode. This is what is currently implemented in ARM TCG....
tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologueare unused outside of tcg.c.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64to perform the move at the proper width, which may elide a REX prefix.
Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data"...
tcg/arm: fix condition in zero/sign extension functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: remove conditional argument for qemu_ld/st
While it make sense to pass a conditional argument to tcg_out_*()functions as the ARM architecture allows that, it doesn't make sensefor qemu_ld/st functions. These functions use comparison instructions...
tcg/arm: use ext* ops in qemu_ld
tcg/arm: bswap arguments in qemu_ld/st if needed
On big endian targets, data arguments of qemu_ld/st ops have to bebyte swapped. Two temporary registers are needed for qemu_st to dothe bswap. r0 and r1 are used in system mode, do the same in usermode, which implies reworking the constraints....
tcg/arm: remove useless register tests in qemu_ld/st
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to theconstraints. Don't check if they equals these registers.
tcg/arm: fix argument alignment in qemu_st64
64-bit arguments should be aligned on an even register as specifiedby the "Procedure Call Standard for the ARM Architecture".
tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG armtarget matches the list of clobbered registers. This means that when anhelper is called, there is almost always clobbered registers that haveto be spilled....
tcg/arm: don't try to load constants using pc
There is statistically almost 0 chances to use this code, soremove it.
tcg/arm: sxtb and sxth are available starting with ARMv6
tcg/arm: use the blx instruction when possible
tcg/arm: add rotation ops
tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or twoshifts on previous ARM versions. In both cases the result use the samenumber or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they...
tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16instructions on ARMv6+ or shifts and logical operations on previousARM versions. In both cases the result use less instructions thanthe pure TCG version.
These ops are also needed by the qemu_ld/st functions....
tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to asubroutine. According to the "Procedure Call Standard for the ARMArchitecture", it is the job of the callee to save this register.Moreover, this register is already saved in the prologue/epilogue....
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that areclobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved....
tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Removethem.
tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediatevalues and register number. This makes the code difficult to read.
The patch below replaces all (if I haven't miss any ;-) integer values...
tcg/arm: add variables to define the allowed instructions set
Use a set of variables to define the allowed ARM instructions, dependingon the ARM_ARCH_* GCC defines.
tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860dc38e9c89e787c5210e8191800385edid not change all occurrences of INDEX_op_qemu_ld32ufor tcg/arm.
Please note that I could not test this patch(I have currently no arm system available)....
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the addressof the env structure and is not modified by GCC.
tcg/arm: fix load/store definitions for 32-bit targets
tcg/arm: use helpers for divu/remu
tcg/arm: implement andc op
tcg/arm: correctly save/restore registers in prologue/epilogue
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crasheson ARM hosts. This is not a bug of this commit, but a latent bugrevealed by this commit.
The TCG code is called through a procedure call using the prologue...
Remove TLB from userspace
Remove TLB from userspace CPU structure.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add a missing break
tcg/arm: implement setcond2
tcg/arm: implement setcond
tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skippedvalues.
ARM back-end: Use sxt[bh] instructions for ext{8, 6}s
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Suppress some variants of English in comments
Replace surpress, supress by suppress.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM back-end: Fix encode_imm
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
ARM back-end: Handle all possible immediates for ALU ops
this patch handles all possible constants for immediate operand of ALU ops.I'm not very satisfied by the implementation.
ARM back-end: Add TCG not
this patch:
- implements TCG not.
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A- implement add/sub/and/or/xor with immediate (only 8-bit)
Userspace guest address offsetting
Re-implement GUEST_BASE support.Offset guest ddress space by default if the guest binary containsregions below the host mmap_min_addr.Implement support for i386, x86-64 and arm hosts.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>...
ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.
tcg-arm: fix qemu_ld64
Emulating fldl on arm doesn't seem to work too well. It's the wayqemu_ld64 is translated to arm instructions.
tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);...
Fix 64-bit targets compilation on ARM host.
Only fix compilation, probably doesn't run.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162
arm: Don't potentially overwrite input registers in add2, sub2.
According to malc TCG will often genereate an add2/sub2/mul2 with lowhalf of the output in the same register as high half of one of theinputs, so account for that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
Don't rely on ARM tcg_out_goto() generating just a single insn.
Otherwise when tb_exit generates a jump beyond the pc-relative range,tcg_out_goto() spans two/three instructions and we load the tb returnvalue from a wrong address. This is #ifdefed out currently because...
Add some missing static and const qualifiers, reg_names only used if NDEBUG set
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Relax a constraint for qemu_ld64 on ARM host.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4567 c046a42c-6fe2-441c-8c8c-71466251a162
Fix a deadly typo, correct comments.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4566 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM host TLB.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162
Comment non-obvious calculation. Don't clobber r3 in qemu_st64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
A branch insn must not overwrite the branch target before relocation.
When a branch to label is translated it generates a reloc that is filled inwhen the label is translated. However, when handling an exception andsearching for the pc we abort the translation early and we sometimes...
Fix qemu_ld/st for mem_index > 0 on arm host.
offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0was larger than max immediate offset for ldr and str (12-bit) so insert anadditional insn to add the mem_index offset.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 8-bit signed load/store and a typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162
Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162