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tcg/arm: add rotation ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or twoshifts on previous ARM versions. In both cases the result use the samenumber or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they...
tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16instructions on ARMv6+ or shifts and logical operations on previousARM versions. In both cases the result use less instructions thanthe pure TCG version.
These ops are also needed by the qemu_ld/st functions....
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that areclobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved....
tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".
tcg: Allow target-specific implementation of NOR.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: use helpers for divu/remu
tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers fordiv/rem/divu/remu.
Create a #define for div2 so that targets can select betweendiv, div2 and helper implementation. Use the helper version if noneof the #define are present....
tcg/arm: implement andc op
tcg/arm: merge the two sets of #define for optional ops
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ARM back-end: Add TCG not
this patch:
- implements TCG not.
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A- implement add/sub/and/or/xor with immediate (only 8-bit)
Userspace guest address offsetting
Re-implement GUEST_BASE support.Offset guest ddress space by default if the guest binary containsregions below the host mmap_min_addr.Implement support for i386, x86-64 and arm hosts.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>...
ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
Prune unused TCG_AREGs
Remove definitions for TCG_AREGs corresponding to AREG definitionsremoved in r6778.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
Use libgcc __clear_cache to clean icache, when available.
Calling the clear cache syscall directly generates an illegal instructionon some (armv4) kernels.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
Define TCG_TARGET_CALL_STACK_OFFSET on arm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162