Revision 0f8a249a target-sparc/cpu.h

b/target-sparc/cpu.h
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#define TARGET_HAS_ICE 1
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#if !defined(TARGET_SPARC64)
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#define ELF_MACHINE	EM_SPARC
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#define ELF_MACHINE     EM_SPARC
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#else
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#define ELF_MACHINE	EM_SPARCV9
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#define ELF_MACHINE     EM_SPARCV9
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#endif
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/*#define EXCP_INTERRUPT 0x100*/
......
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#define FSR_FCC0  (1<<10)
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/* MMU */
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#define MMU_E	  (1<<0)
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#define MMU_NF	  (1<<1)
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#define MMU_E     (1<<0)
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#define MMU_NF    (1<<1)
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#define PTE_ENTRYTYPE_MASK 3
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#define PTE_ACCESS_MASK    0x1c
......
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#define PTE_PPN_SHIFT      7
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#define PTE_ADDR_MASK      0xffffff00
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#define PG_ACCESSED_BIT	5
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#define PG_MODIFIED_BIT	6
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#define PG_ACCESSED_BIT 5
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#define PG_MODIFIED_BIT 6
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#define PG_CACHE_BIT    7
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
......
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    uint64_t tnpc[MAXTL];
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    uint64_t tstate[MAXTL];
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    uint32_t tt[MAXTL];
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    uint32_t xcc;		/* Extended integer condition codes */
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    uint32_t xcc;               /* Extended integer condition codes */
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    uint32_t asi;
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    uint32_t pstate;
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    uint32_t tl;
......
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} CPUSPARCState;
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#if defined(TARGET_SPARC64)
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#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val;			\
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	env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);	\
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
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        env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
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    } while (0)
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#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
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#define PUT_FSR64(env, val) do { uint64_t _tmp = val;	\
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	env->fsr = _tmp & 0x3fcfc1c3ffULL;		\
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#define PUT_FSR64(env, val) do { uint64_t _tmp = val;   \
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        env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
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    } while (0)
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#else
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#define GET_FSR32(env) (env->fsr)
......
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int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
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#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
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		      (env->psref? PSR_EF : 0) |			\
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		      (env->psrpil << 8) |				\
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		      (env->psrs? PSR_S : 0) |				\
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		      (env->psrps? PSR_PS : 0) |			\
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		      (env->psret? PSR_ET : 0) | env->cwp)
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                      (env->psref? PSR_EF : 0) |                        \
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                      (env->psrpil << 8) |                              \
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                      (env->psrs? PSR_S : 0) |                          \
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                      (env->psrps? PSR_PS : 0) |                        \
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                      (env->psret? PSR_ET : 0) | env->cwp)
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#ifndef NO_CPU_IO_DEFS
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void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
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#endif
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#define PUT_PSR(env, val) do { int _tmp = val;				\
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	env->psr = _tmp & PSR_ICC;					\
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	env->psref = (_tmp & PSR_EF)? 1 : 0;				\
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	env->psrpil = (_tmp & PSR_PIL) >> 8;				\
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	env->psrs = (_tmp & PSR_S)? 1 : 0;				\
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	env->psrps = (_tmp & PSR_PS)? 1 : 0;				\
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	env->psret = (_tmp & PSR_ET)? 1 : 0;				\
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#define PUT_PSR(env, val) do { int _tmp = val;                          \
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        env->psr = _tmp & PSR_ICC;                                      \
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        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
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        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
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        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
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        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
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        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
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        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
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    } while (0)
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#ifdef TARGET_SPARC64
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#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
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#define PUT_CCR(env, val) do { int _tmp = val;				\
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	env->xcc = (_tmp >> 4) << 20;						\
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	env->psr = (_tmp & 0xf) << 20;					\
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#define PUT_CCR(env, val) do { int _tmp = val;                          \
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        env->xcc = (_tmp >> 4) << 20;                                           \
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        env->psr = (_tmp & 0xf) << 20;                                  \
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    } while (0)
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#define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
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#define PUT_CWP64(env, val) \

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