Revision 0f8a249a target-sparc/helper.c

b/target-sparc/helper.c
99 99
};
100 100

  
101 101
int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
102
			  int *access_index, target_ulong address, int rw,
103
			  int is_user)
102
                          int *access_index, target_ulong address, int rw,
103
                          int is_user)
104 104
{
105 105
    int access_perms = 0;
106 106
    target_phys_addr_t pde_ptr;
......
111 111

  
112 112
    virt_addr = address & TARGET_PAGE_MASK;
113 113
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
114
	*physical = address;
114
        *physical = address;
115 115
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
116 116
        return 0;
117 117
    }
......
128 128
    switch (pde & PTE_ENTRYTYPE_MASK) {
129 129
    default:
130 130
    case 0: /* Invalid */
131
	return 1 << 2;
131
        return 1 << 2;
132 132
    case 2: /* L0 PTE, maybe should not happen? */
133 133
    case 3: /* Reserved */
134 134
        return 4 << 2;
135 135
    case 1: /* L0 PDE */
136
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
136
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
137 137
        pde = ldl_phys(pde_ptr);
138 138

  
139
	switch (pde & PTE_ENTRYTYPE_MASK) {
140
	default:
141
	case 0: /* Invalid */
142
	    return (1 << 8) | (1 << 2);
143
	case 3: /* Reserved */
144
	    return (1 << 8) | (4 << 2);
145
	case 1: /* L1 PDE */
146
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
139
        switch (pde & PTE_ENTRYTYPE_MASK) {
140
        default:
141
        case 0: /* Invalid */
142
            return (1 << 8) | (1 << 2);
143
        case 3: /* Reserved */
144
            return (1 << 8) | (4 << 2);
145
        case 1: /* L1 PDE */
146
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
147 147
            pde = ldl_phys(pde_ptr);
148 148

  
149
	    switch (pde & PTE_ENTRYTYPE_MASK) {
150
	    default:
151
	    case 0: /* Invalid */
152
		return (2 << 8) | (1 << 2);
153
	    case 3: /* Reserved */
154
		return (2 << 8) | (4 << 2);
155
	    case 1: /* L2 PDE */
156
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
149
            switch (pde & PTE_ENTRYTYPE_MASK) {
150
            default:
151
            case 0: /* Invalid */
152
                return (2 << 8) | (1 << 2);
153
            case 3: /* Reserved */
154
                return (2 << 8) | (4 << 2);
155
            case 1: /* L2 PDE */
156
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
157 157
                pde = ldl_phys(pde_ptr);
158 158

  
159
		switch (pde & PTE_ENTRYTYPE_MASK) {
160
		default:
161
		case 0: /* Invalid */
162
		    return (3 << 8) | (1 << 2);
163
		case 1: /* PDE, should not happen */
164
		case 3: /* Reserved */
165
		    return (3 << 8) | (4 << 2);
166
		case 2: /* L3 PTE */
167
		    virt_addr = address & TARGET_PAGE_MASK;
168
		    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
169
		}
170
		break;
171
	    case 2: /* L2 PTE */
172
		virt_addr = address & ~0x3ffff;
173
		page_offset = address & 0x3ffff;
174
	    }
175
	    break;
176
	case 2: /* L1 PTE */
177
	    virt_addr = address & ~0xffffff;
178
	    page_offset = address & 0xffffff;
179
	}
159
                switch (pde & PTE_ENTRYTYPE_MASK) {
160
                default:
161
                case 0: /* Invalid */
162
                    return (3 << 8) | (1 << 2);
163
                case 1: /* PDE, should not happen */
164
                case 3: /* Reserved */
165
                    return (3 << 8) | (4 << 2);
166
                case 2: /* L3 PTE */
167
                    virt_addr = address & TARGET_PAGE_MASK;
168
                    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
169
                }
170
                break;
171
            case 2: /* L2 PTE */
172
                virt_addr = address & ~0x3ffff;
173
                page_offset = address & 0x3ffff;
174
            }
175
            break;
176
        case 2: /* L1 PTE */
177
            virt_addr = address & ~0xffffff;
178
            page_offset = address & 0xffffff;
179
        }
180 180
    }
181 181

  
182 182
    /* update page modified and dirty bits */
183 183
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
184 184
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
185
	pde |= PG_ACCESSED_MASK;
186
	if (is_dirty)
187
	    pde |= PG_MODIFIED_MASK;
185
        pde |= PG_ACCESSED_MASK;
186
        if (is_dirty)
187
            pde |= PG_MODIFIED_MASK;
188 188
        stl_phys_notdirty(pde_ptr, pde);
189 189
    }
190 190
    /* check access */
191 191
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
192 192
    error_code = access_table[*access_index][access_perms];
193 193
    if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
194
	return error_code;
194
        return error_code;
195 195

  
196 196
    /* the page can be put in the TLB */
197 197
    *prot = perm_table[is_user][access_perms];
......
217 217

  
218 218
    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
219 219
    if (error_code == 0) {
220
	vaddr = address & TARGET_PAGE_MASK;
221
	paddr &= TARGET_PAGE_MASK;
220
        vaddr = address & TARGET_PAGE_MASK;
221
        paddr &= TARGET_PAGE_MASK;
222 222
#ifdef DEBUG_MMU
223
	printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
223
        printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
224 224
               TARGET_FMT_lx "\n", address, paddr, vaddr);
225 225
#endif
226
	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
227
	return ret;
226
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
227
        return ret;
228 228
    }
229 229

  
230 230
    if (env->mmuregs[3]) /* Fault status register */
231
	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
231
        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
232 232
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
233 233
    env->mmuregs[4] = address; /* Fault address register */
234 234

  
......
237 237
        // permissions. If no mapping is available, redirect accesses to
238 238
        // neverland. Fake/overridden mappings will be flushed when
239 239
        // switching to normal mode.
240
	vaddr = address & TARGET_PAGE_MASK;
240
        vaddr = address & TARGET_PAGE_MASK;
241 241
        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
242 242
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
243
	return ret;
243
        return ret;
244 244
    } else {
245 245
        if (rw & 2)
246 246
            env->exception_index = TT_TFAULT;
......
265 265
    case 0: /* Invalid */
266 266
    case 2: /* PTE, maybe should not happen? */
267 267
    case 3: /* Reserved */
268
	return 0;
268
        return 0;
269 269
    case 1: /* L1 PDE */
270
	if (mmulev == 3)
271
	    return pde;
272
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
270
        if (mmulev == 3)
271
            return pde;
272
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
273 273
        pde = ldl_phys(pde_ptr);
274 274

  
275
	switch (pde & PTE_ENTRYTYPE_MASK) {
276
	default:
277
	case 0: /* Invalid */
278
	case 3: /* Reserved */
279
	    return 0;
280
	case 2: /* L1 PTE */
281
	    return pde;
282
	case 1: /* L2 PDE */
283
	    if (mmulev == 2)
284
		return pde;
285
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
275
        switch (pde & PTE_ENTRYTYPE_MASK) {
276
        default:
277
        case 0: /* Invalid */
278
        case 3: /* Reserved */
279
            return 0;
280
        case 2: /* L1 PTE */
281
            return pde;
282
        case 1: /* L2 PDE */
283
            if (mmulev == 2)
284
                return pde;
285
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
286 286
            pde = ldl_phys(pde_ptr);
287 287

  
288
	    switch (pde & PTE_ENTRYTYPE_MASK) {
289
	    default:
290
	    case 0: /* Invalid */
291
	    case 3: /* Reserved */
292
		return 0;
293
	    case 2: /* L2 PTE */
294
		return pde;
295
	    case 1: /* L3 PDE */
296
		if (mmulev == 1)
297
		    return pde;
298
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
288
            switch (pde & PTE_ENTRYTYPE_MASK) {
289
            default:
290
            case 0: /* Invalid */
291
            case 3: /* Reserved */
292
                return 0;
293
            case 2: /* L2 PTE */
294
                return pde;
295
            case 1: /* L3 PDE */
296
                if (mmulev == 1)
297
                    return pde;
298
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
299 299
                pde = ldl_phys(pde_ptr);
300 300

  
301
		switch (pde & PTE_ENTRYTYPE_MASK) {
302
		default:
303
		case 0: /* Invalid */
304
		case 1: /* PDE, should not happen */
305
		case 3: /* Reserved */
306
		    return 0;
307
		case 2: /* L3 PTE */
308
		    return pde;
309
		}
310
	    }
311
	}
301
                switch (pde & PTE_ENTRYTYPE_MASK) {
302
                default:
303
                case 0: /* Invalid */
304
                case 1: /* PDE, should not happen */
305
                case 3: /* Reserved */
306
                    return 0;
307
                case 2: /* L3 PTE */
308
                    return pde;
309
                }
310
            }
311
        }
312 312
    }
313 313
    return 0;
314 314
}
......
327 327
    printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
328 328
           (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
329 329
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
330
	pde = mmu_probe(env, va, 2);
331
	if (pde) {
332
	    pa = cpu_get_phys_page_debug(env, va);
333
 	    printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
330
        pde = mmu_probe(env, va, 2);
331
        if (pde) {
332
            pa = cpu_get_phys_page_debug(env, va);
333
            printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
334 334
                   " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
335
	    for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
336
		pde = mmu_probe(env, va1, 1);
337
		if (pde) {
338
		    pa = cpu_get_phys_page_debug(env, va1);
339
 		    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
335
            for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
336
                pde = mmu_probe(env, va1, 1);
337
                if (pde) {
338
                    pa = cpu_get_phys_page_debug(env, va1);
339
                    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
340 340
                           " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
341
		    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
342
			pde = mmu_probe(env, va2, 0);
343
			if (pde) {
344
			    pa = cpu_get_phys_page_debug(env, va2);
345
 			    printf("  VA: " TARGET_FMT_lx ", PA: "
341
                    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
342
                        pde = mmu_probe(env, va2, 0);
343
                        if (pde) {
344
                            pa = cpu_get_phys_page_debug(env, va2);
345
                            printf("  VA: " TARGET_FMT_lx ", PA: "
346 346
                                   TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
347 347
                                   va2, pa, pde);
348
			}
349
		    }
350
		}
351
	    }
352
	}
348
                        }
349
                    }
350
                }
351
            }
352
        }
353 353
    }
354 354
    printf("MMU dump ends\n");
355 355
}
......
360 360
 * UltraSparc IIi I/DMMUs
361 361
 */
362 362
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
363
			  int *access_index, target_ulong address, int rw,
364
			  int is_user)
363
                          int *access_index, target_ulong address, int rw,
364
                          int is_user)
365 365
{
366 366
    target_ulong mask;
367 367
    unsigned int i;
368 368

  
369 369
    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
370
	*physical = address;
371
	*prot = PAGE_READ | PAGE_WRITE;
370
        *physical = address;
371
        *prot = PAGE_READ | PAGE_WRITE;
372 372
        return 0;
373 373
    }
374 374

  
375 375
    for (i = 0; i < 64; i++) {
376
	switch ((env->dtlb_tte[i] >> 61) & 3) {
377
	default:
378
	case 0x0: // 8k
379
	    mask = 0xffffffffffffe000ULL;
380
	    break;
381
	case 0x1: // 64k
382
	    mask = 0xffffffffffff0000ULL;
383
	    break;
384
	case 0x2: // 512k
385
	    mask = 0xfffffffffff80000ULL;
386
	    break;
387
	case 0x3: // 4M
388
	    mask = 0xffffffffffc00000ULL;
389
	    break;
390
	}
391
	// ctx match, vaddr match?
392
	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
393
	    (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
394
	    // valid, access ok?
395
	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
396
		((env->dtlb_tte[i] & 0x4) && is_user) ||
397
		(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
398
		if (env->dmmuregs[3]) /* Fault status register */
399
		    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
400
		env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
401
		env->dmmuregs[4] = address; /* Fault address register */
402
		env->exception_index = TT_DFAULT;
376
        switch ((env->dtlb_tte[i] >> 61) & 3) {
377
        default:
378
        case 0x0: // 8k
379
            mask = 0xffffffffffffe000ULL;
380
            break;
381
        case 0x1: // 64k
382
            mask = 0xffffffffffff0000ULL;
383
            break;
384
        case 0x2: // 512k
385
            mask = 0xfffffffffff80000ULL;
386
            break;
387
        case 0x3: // 4M
388
            mask = 0xffffffffffc00000ULL;
389
            break;
390
        }
391
        // ctx match, vaddr match?
392
        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
393
            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
394
            // valid, access ok?
395
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
396
                ((env->dtlb_tte[i] & 0x4) && is_user) ||
397
                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
398
                if (env->dmmuregs[3]) /* Fault status register */
399
                    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
400
                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
401
                env->dmmuregs[4] = address; /* Fault address register */
402
                env->exception_index = TT_DFAULT;
403 403
#ifdef DEBUG_MMU
404
		printf("DFAULT at 0x%" PRIx64 "\n", address);
404
                printf("DFAULT at 0x%" PRIx64 "\n", address);
405 405
#endif
406
		return 1;
407
	    }
408
	    *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
409
	    *prot = PAGE_READ;
410
	    if (env->dtlb_tte[i] & 0x2)
411
		*prot |= PAGE_WRITE;
412
	    return 0;
413
	}
406
                return 1;
407
            }
408
            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
409
            *prot = PAGE_READ;
410
            if (env->dtlb_tte[i] & 0x2)
411
                *prot |= PAGE_WRITE;
412
            return 0;
413
        }
414 414
    }
415 415
#ifdef DEBUG_MMU
416 416
    printf("DMISS at 0x%" PRIx64 "\n", address);
......
420 420
}
421 421

  
422 422
static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
423
			  int *access_index, target_ulong address, int rw,
424
			  int is_user)
423
                          int *access_index, target_ulong address, int rw,
424
                          int is_user)
425 425
{
426 426
    target_ulong mask;
427 427
    unsigned int i;
428 428

  
429 429
    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
430
	*physical = address;
431
	*prot = PAGE_EXEC;
430
        *physical = address;
431
        *prot = PAGE_EXEC;
432 432
        return 0;
433 433
    }
434 434

  
435 435
    for (i = 0; i < 64; i++) {
436
	switch ((env->itlb_tte[i] >> 61) & 3) {
437
	default:
438
	case 0x0: // 8k
439
	    mask = 0xffffffffffffe000ULL;
440
	    break;
441
	case 0x1: // 64k
442
	    mask = 0xffffffffffff0000ULL;
443
	    break;
444
	case 0x2: // 512k
445
	    mask = 0xfffffffffff80000ULL;
446
	    break;
447
	case 0x3: // 4M
448
	    mask = 0xffffffffffc00000ULL;
449
		break;
450
	}
451
	// ctx match, vaddr match?
452
	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
453
	    (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
454
	    // valid, access ok?
455
	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
456
		((env->itlb_tte[i] & 0x4) && is_user)) {
457
		if (env->immuregs[3]) /* Fault status register */
458
		    env->immuregs[3] = 2; /* overflow (not read before another fault) */
459
		env->immuregs[3] |= (is_user << 3) | 1;
460
		env->exception_index = TT_TFAULT;
436
        switch ((env->itlb_tte[i] >> 61) & 3) {
437
        default:
438
        case 0x0: // 8k
439
            mask = 0xffffffffffffe000ULL;
440
            break;
441
        case 0x1: // 64k
442
            mask = 0xffffffffffff0000ULL;
443
            break;
444
        case 0x2: // 512k
445
            mask = 0xfffffffffff80000ULL;
446
            break;
447
        case 0x3: // 4M
448
            mask = 0xffffffffffc00000ULL;
449
                break;
450
        }
451
        // ctx match, vaddr match?
452
        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
453
            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
454
            // valid, access ok?
455
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
456
                ((env->itlb_tte[i] & 0x4) && is_user)) {
457
                if (env->immuregs[3]) /* Fault status register */
458
                    env->immuregs[3] = 2; /* overflow (not read before another fault) */
459
                env->immuregs[3] |= (is_user << 3) | 1;
460
                env->exception_index = TT_TFAULT;
461 461
#ifdef DEBUG_MMU
462
		printf("TFAULT at 0x%" PRIx64 "\n", address);
462
                printf("TFAULT at 0x%" PRIx64 "\n", address);
463 463
#endif
464
		return 1;
465
	    }
466
	    *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
467
	    *prot = PAGE_EXEC;
468
	    return 0;
469
	}
464
                return 1;
465
            }
466
            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
467
            *prot = PAGE_EXEC;
468
            return 0;
469
        }
470 470
    }
471 471
#ifdef DEBUG_MMU
472 472
    printf("TMISS at 0x%" PRIx64 "\n", address);
......
476 476
}
477 477

  
478 478
int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
479
			  int *access_index, target_ulong address, int rw,
480
			  int is_user)
479
                          int *access_index, target_ulong address, int rw,
480
                          int is_user)
481 481
{
482 482
    if (rw == 2)
483
	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
483
        return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
484 484
    else
485
	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
485
        return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
486 486
}
487 487

  
488 488
/* Perform address translation */
......
495 495

  
496 496
    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
497 497
    if (error_code == 0) {
498
	virt_addr = address & TARGET_PAGE_MASK;
499
	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
498
        virt_addr = address & TARGET_PAGE_MASK;
499
        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
500 500
#ifdef DEBUG_MMU
501
	printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
501
        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
502 502
#endif
503
	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
504
	return ret;
503
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
504
        return ret;
505 505
    }
506 506
    // XXX
507 507
    return 1;
......
515 515

  
516 516
    printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
517 517
    if ((env->lsu & DMMU_E) == 0) {
518
	printf("DMMU disabled\n");
518
        printf("DMMU disabled\n");
519 519
    } else {
520
	printf("DMMU dump:\n");
521
	for (i = 0; i < 64; i++) {
522
	    switch ((env->dtlb_tte[i] >> 61) & 3) {
523
	    default:
524
	    case 0x0:
525
		mask = "  8k";
526
		break;
527
	    case 0x1:
528
		mask = " 64k";
529
		break;
530
	    case 0x2:
531
		mask = "512k";
532
		break;
533
	    case 0x3:
534
		mask = "  4M";
535
		break;
536
	    }
537
	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
538
		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
539
		       env->dtlb_tag[i] & ~0x1fffULL,
540
		       env->dtlb_tte[i] & 0x1ffffffe000ULL,
541
		       mask,
542
		       env->dtlb_tte[i] & 0x4? "priv": "user",
543
		       env->dtlb_tte[i] & 0x2? "RW": "RO",
544
		       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
545
		       env->dtlb_tag[i] & 0x1fffULL);
546
	    }
547
	}
520
        printf("DMMU dump:\n");
521
        for (i = 0; i < 64; i++) {
522
            switch ((env->dtlb_tte[i] >> 61) & 3) {
523
            default:
524
            case 0x0:
525
                mask = "  8k";
526
                break;
527
            case 0x1:
528
                mask = " 64k";
529
                break;
530
            case 0x2:
531
                mask = "512k";
532
                break;
533
            case 0x3:
534
                mask = "  4M";
535
                break;
536
            }
537
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
538
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
539
                       env->dtlb_tag[i] & ~0x1fffULL,
540
                       env->dtlb_tte[i] & 0x1ffffffe000ULL,
541
                       mask,
542
                       env->dtlb_tte[i] & 0x4? "priv": "user",
543
                       env->dtlb_tte[i] & 0x2? "RW": "RO",
544
                       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
545
                       env->dtlb_tag[i] & 0x1fffULL);
546
            }
547
        }
548 548
    }
549 549
    if ((env->lsu & IMMU_E) == 0) {
550
	printf("IMMU disabled\n");
550
        printf("IMMU disabled\n");
551 551
    } else {
552
	printf("IMMU dump:\n");
553
	for (i = 0; i < 64; i++) {
554
	    switch ((env->itlb_tte[i] >> 61) & 3) {
555
	    default:
556
	    case 0x0:
557
		mask = "  8k";
558
		break;
559
	    case 0x1:
560
		mask = " 64k";
561
		break;
562
	    case 0x2:
563
		mask = "512k";
564
		break;
565
	    case 0x3:
566
		mask = "  4M";
567
		break;
568
	    }
569
	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
570
		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
571
		       env->itlb_tag[i] & ~0x1fffULL,
572
		       env->itlb_tte[i] & 0x1ffffffe000ULL,
573
		       mask,
574
		       env->itlb_tte[i] & 0x4? "priv": "user",
575
		       env->itlb_tte[i] & 0x40? "locked": "unlocked",
576
		       env->itlb_tag[i] & 0x1fffULL);
577
	    }
578
	}
552
        printf("IMMU dump:\n");
553
        for (i = 0; i < 64; i++) {
554
            switch ((env->itlb_tte[i] >> 61) & 3) {
555
            default:
556
            case 0x0:
557
                mask = "  8k";
558
                break;
559
            case 0x1:
560
                mask = " 64k";
561
                break;
562
            case 0x2:
563
                mask = "512k";
564
                break;
565
            case 0x3:
566
                mask = "  4M";
567
                break;
568
            }
569
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
570
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
571
                       env->itlb_tag[i] & ~0x1fffULL,
572
                       env->itlb_tte[i] & 0x1ffffffe000ULL,
573
                       mask,
574
                       env->itlb_tte[i] & 0x4? "priv": "user",
575
                       env->itlb_tte[i] & 0x40? "locked": "unlocked",
576
                       env->itlb_tag[i] & 0x1fffULL);
577
            }
578
        }
579 579
    }
580 580
}
581 581
#endif /* DEBUG_MMU */

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