Revision 0f8a249a target-sparc/translate.c

b/target-sparc/translate.c
45 45
                         according to jump_pc[T2] */
46 46

  
47 47
typedef struct DisasContext {
48
    target_ulong pc;	/* current Program Counter: integer or DYNAMIC_PC */
49
    target_ulong npc;	/* next PC: integer or DYNAMIC_PC or JUMP_PC */
48
    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
49
    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 50
    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
51 51
    int is_br;
52 52
    int mem_idx;
......
359 359
#define supervisor(dc) 0
360 360
#define hypervisor(dc) 0
361 361
#define gen_op_ldst(name)        gen_op_##name##_raw()
362
#define OP_LD_TABLE(width)						\
362
#define OP_LD_TABLE(width)                                              \
363 363
    static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
364
    {									\
365
	int asi, offset;						\
366
									\
367
	if (IS_IMM) {							\
368
	    offset = GET_FIELD(insn, 25, 31);				\
369
	    if (is_ld)							\
370
		gen_op_ld_asi_reg(offset, size, sign);			\
371
	    else							\
372
		gen_op_st_asi_reg(offset, size, sign);			\
373
	    return;							\
374
	}								\
375
	asi = GET_FIELD(insn, 19, 26);					\
376
	switch (asi) {							\
377
	case 0x80: /* Primary address space */				\
378
	    gen_op_##width##_raw();					\
379
	    break;							\
380
	case 0x82: /* Primary address space, non-faulting load */       \
381
	    gen_op_##width##_raw();					\
382
	    break;							\
383
	default:							\
384
            break;							\
385
	}								\
364
    {                                                                   \
365
        int asi, offset;                                                \
366
                                                                        \
367
        if (IS_IMM) {                                                   \
368
            offset = GET_FIELD(insn, 25, 31);                           \
369
            if (is_ld)                                                  \
370
                gen_op_ld_asi_reg(offset, size, sign);                  \
371
            else                                                        \
372
                gen_op_st_asi_reg(offset, size, sign);                  \
373
            return;                                                     \
374
        }                                                               \
375
        asi = GET_FIELD(insn, 19, 26);                                  \
376
        switch (asi) {                                                  \
377
        case 0x80: /* Primary address space */                          \
378
            gen_op_##width##_raw();                                     \
379
            break;                                                      \
380
        case 0x82: /* Primary address space, non-faulting load */       \
381
            gen_op_##width##_raw();                                     \
382
            break;                                                      \
383
        default:                                                        \
384
            break;                                                      \
385
        }                                                               \
386 386
    }
387 387

  
388 388
#else
389 389
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
390
#define OP_LD_TABLE(width)						\
390
#define OP_LD_TABLE(width)                                              \
391 391
    static GenOpFunc * const gen_op_##width[] = {                       \
392
	&gen_op_##width##_user,						\
393
	&gen_op_##width##_kernel,					\
394
    };									\
395
									\
392
        &gen_op_##width##_user,                                         \
393
        &gen_op_##width##_kernel,                                       \
394
    };                                                                  \
395
                                                                        \
396 396
    static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
397
    {									\
398
	int asi, offset;						\
399
									\
400
	if (IS_IMM) {							\
401
	    offset = GET_FIELD(insn, 25, 31);				\
402
	    if (is_ld)							\
403
		gen_op_ld_asi_reg(offset, size, sign);			\
404
	    else							\
405
		gen_op_st_asi_reg(offset, size, sign);			\
406
	    return;							\
407
	}								\
408
	asi = GET_FIELD(insn, 19, 26);					\
409
	if (is_ld)							\
410
	    gen_op_ld_asi(asi, size, sign);				\
411
	else								\
412
	    gen_op_st_asi(asi, size, sign);				\
397
    {                                                                   \
398
        int asi, offset;                                                \
399
                                                                        \
400
        if (IS_IMM) {                                                   \
401
            offset = GET_FIELD(insn, 25, 31);                           \
402
            if (is_ld)                                                  \
403
                gen_op_ld_asi_reg(offset, size, sign);                  \
404
            else                                                        \
405
                gen_op_st_asi_reg(offset, size, sign);                  \
406
            return;                                                     \
407
        }                                                               \
408
        asi = GET_FIELD(insn, 19, 26);                                  \
409
        if (is_ld)                                                      \
410
            gen_op_ld_asi(asi, size, sign);                             \
411
        else                                                            \
412
            gen_op_st_asi(asi, size, sign);                             \
413 413
    }
414 414

  
415 415
#define supervisor(dc) (dc->mem_idx == 1)
......
422 422
#define supervisor(dc) 0
423 423
#else
424 424
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
425
#define OP_LD_TABLE(width)						      \
425
#define OP_LD_TABLE(width)                                                    \
426 426
static GenOpFunc * const gen_op_##width[] = {                                 \
427 427
    &gen_op_##width##_user,                                                   \
428 428
    &gen_op_##width##_kernel,                                                 \
......
434 434
                                                                              \
435 435
    asi = GET_FIELD(insn, 19, 26);                                            \
436 436
    switch (asi) {                                                            \
437
	case 10: /* User data access */                                       \
438
	    gen_op_##width##_user();                                          \
439
	    break;                                                            \
440
	case 11: /* Supervisor data access */                                 \
441
	    gen_op_##width##_kernel();                                        \
442
	    break;                                                            \
443
        case 0x20 ... 0x2f: /* MMU passthrough */			      \
444
	    if (is_ld)                                                        \
445
		gen_op_ld_asi(asi, size, sign);				      \
446
	    else                                                              \
447
		gen_op_st_asi(asi, size, sign);				      \
448
	    break;                                                            \
449
	default:                                                              \
450
	    if (is_ld)                                                        \
451
		gen_op_ld_asi(asi, size, sign);			              \
452
	    else                                                              \
453
		gen_op_st_asi(asi, size, sign);				      \
437
        case 10: /* User data access */                                       \
438
            gen_op_##width##_user();                                          \
439
            break;                                                            \
440
        case 11: /* Supervisor data access */                                 \
441
            gen_op_##width##_kernel();                                        \
442
            break;                                                            \
443
        case 0x20 ... 0x2f: /* MMU passthrough */                             \
444
            if (is_ld)                                                        \
445
                gen_op_ld_asi(asi, size, sign);                               \
446
            else                                                              \
447
                gen_op_st_asi(asi, size, sign);                               \
448
            break;                                                            \
449
        default:                                                              \
450
            if (is_ld)                                                        \
451
                gen_op_ld_asi(asi, size, sign);                               \
452
            else                                                              \
453
                gen_op_st_asi(asi, size, sign);                               \
454 454
            break;                                                            \
455 455
    }                                                                         \
456 456
}
......
518 518
static inline void gen_movl_reg_TN(int reg, int t)
519 519
{
520 520
    if (reg)
521
	gen_op_movl_reg_TN[t][reg] ();
521
        gen_op_movl_reg_TN[t][reg] ();
522 522
    else
523
	gen_movl_imm_TN(t, 0);
523
        gen_movl_imm_TN(t, 0);
524 524
}
525 525

  
526 526
static inline void gen_movl_reg_T0(int reg)
......
541 541
static inline void gen_movl_TN_reg(int reg, int t)
542 542
{
543 543
    if (reg)
544
	gen_op_movl_TN_reg[t][reg] ();
544
        gen_op_movl_TN_reg[t][reg] ();
545 545
}
546 546

  
547 547
static inline void gen_movl_T0_reg(int reg)
......
699 699

  
700 700
static GenOpFunc * const gen_cond[2][16] = {
701 701
    {
702
	gen_op_eval_bn,
703
	gen_op_eval_be,
704
	gen_op_eval_ble,
705
	gen_op_eval_bl,
706
	gen_op_eval_bleu,
707
	gen_op_eval_bcs,
708
	gen_op_eval_bneg,
709
	gen_op_eval_bvs,
710
	gen_op_eval_ba,
711
	gen_op_eval_bne,
712
	gen_op_eval_bg,
713
	gen_op_eval_bge,
714
	gen_op_eval_bgu,
715
	gen_op_eval_bcc,
716
	gen_op_eval_bpos,
717
	gen_op_eval_bvc,
702
        gen_op_eval_bn,
703
        gen_op_eval_be,
704
        gen_op_eval_ble,
705
        gen_op_eval_bl,
706
        gen_op_eval_bleu,
707
        gen_op_eval_bcs,
708
        gen_op_eval_bneg,
709
        gen_op_eval_bvs,
710
        gen_op_eval_ba,
711
        gen_op_eval_bne,
712
        gen_op_eval_bg,
713
        gen_op_eval_bge,
714
        gen_op_eval_bgu,
715
        gen_op_eval_bcc,
716
        gen_op_eval_bpos,
717
        gen_op_eval_bvc,
718 718
    },
719 719
    {
720 720
#ifdef TARGET_SPARC64
721
	gen_op_eval_bn,
722
	gen_op_eval_xbe,
723
	gen_op_eval_xble,
724
	gen_op_eval_xbl,
725
	gen_op_eval_xbleu,
726
	gen_op_eval_xbcs,
727
	gen_op_eval_xbneg,
728
	gen_op_eval_xbvs,
729
	gen_op_eval_ba,
730
	gen_op_eval_xbne,
731
	gen_op_eval_xbg,
732
	gen_op_eval_xbge,
733
	gen_op_eval_xbgu,
734
	gen_op_eval_xbcc,
735
	gen_op_eval_xbpos,
736
	gen_op_eval_xbvc,
721
        gen_op_eval_bn,
722
        gen_op_eval_xbe,
723
        gen_op_eval_xble,
724
        gen_op_eval_xbl,
725
        gen_op_eval_xbleu,
726
        gen_op_eval_xbcs,
727
        gen_op_eval_xbneg,
728
        gen_op_eval_xbvs,
729
        gen_op_eval_ba,
730
        gen_op_eval_xbne,
731
        gen_op_eval_xbg,
732
        gen_op_eval_xbge,
733
        gen_op_eval_xbgu,
734
        gen_op_eval_xbcc,
735
        gen_op_eval_xbpos,
736
        gen_op_eval_xbvc,
737 737
#endif
738 738
    },
739 739
};
740 740

  
741 741
static GenOpFunc * const gen_fcond[4][16] = {
742 742
    {
743
	gen_op_eval_bn,
744
	gen_op_eval_fbne,
745
	gen_op_eval_fblg,
746
	gen_op_eval_fbul,
747
	gen_op_eval_fbl,
748
	gen_op_eval_fbug,
749
	gen_op_eval_fbg,
750
	gen_op_eval_fbu,
751
	gen_op_eval_ba,
752
	gen_op_eval_fbe,
753
	gen_op_eval_fbue,
754
	gen_op_eval_fbge,
755
	gen_op_eval_fbuge,
756
	gen_op_eval_fble,
757
	gen_op_eval_fbule,
758
	gen_op_eval_fbo,
743
        gen_op_eval_bn,
744
        gen_op_eval_fbne,
745
        gen_op_eval_fblg,
746
        gen_op_eval_fbul,
747
        gen_op_eval_fbl,
748
        gen_op_eval_fbug,
749
        gen_op_eval_fbg,
750
        gen_op_eval_fbu,
751
        gen_op_eval_ba,
752
        gen_op_eval_fbe,
753
        gen_op_eval_fbue,
754
        gen_op_eval_fbge,
755
        gen_op_eval_fbuge,
756
        gen_op_eval_fble,
757
        gen_op_eval_fbule,
758
        gen_op_eval_fbo,
759 759
    },
760 760
#ifdef TARGET_SPARC64
761 761
    {
762
	gen_op_eval_bn,
763
	gen_op_eval_fbne_fcc1,
764
	gen_op_eval_fblg_fcc1,
765
	gen_op_eval_fbul_fcc1,
766
	gen_op_eval_fbl_fcc1,
767
	gen_op_eval_fbug_fcc1,
768
	gen_op_eval_fbg_fcc1,
769
	gen_op_eval_fbu_fcc1,
770
	gen_op_eval_ba,
771
	gen_op_eval_fbe_fcc1,
772
	gen_op_eval_fbue_fcc1,
773
	gen_op_eval_fbge_fcc1,
774
	gen_op_eval_fbuge_fcc1,
775
	gen_op_eval_fble_fcc1,
776
	gen_op_eval_fbule_fcc1,
777
	gen_op_eval_fbo_fcc1,
762
        gen_op_eval_bn,
763
        gen_op_eval_fbne_fcc1,
764
        gen_op_eval_fblg_fcc1,
765
        gen_op_eval_fbul_fcc1,
766
        gen_op_eval_fbl_fcc1,
767
        gen_op_eval_fbug_fcc1,
768
        gen_op_eval_fbg_fcc1,
769
        gen_op_eval_fbu_fcc1,
770
        gen_op_eval_ba,
771
        gen_op_eval_fbe_fcc1,
772
        gen_op_eval_fbue_fcc1,
773
        gen_op_eval_fbge_fcc1,
774
        gen_op_eval_fbuge_fcc1,
775
        gen_op_eval_fble_fcc1,
776
        gen_op_eval_fbule_fcc1,
777
        gen_op_eval_fbo_fcc1,
778 778
    },
779 779
    {
780
	gen_op_eval_bn,
781
	gen_op_eval_fbne_fcc2,
782
	gen_op_eval_fblg_fcc2,
783
	gen_op_eval_fbul_fcc2,
784
	gen_op_eval_fbl_fcc2,
785
	gen_op_eval_fbug_fcc2,
786
	gen_op_eval_fbg_fcc2,
787
	gen_op_eval_fbu_fcc2,
788
	gen_op_eval_ba,
789
	gen_op_eval_fbe_fcc2,
790
	gen_op_eval_fbue_fcc2,
791
	gen_op_eval_fbge_fcc2,
792
	gen_op_eval_fbuge_fcc2,
793
	gen_op_eval_fble_fcc2,
794
	gen_op_eval_fbule_fcc2,
795
	gen_op_eval_fbo_fcc2,
780
        gen_op_eval_bn,
781
        gen_op_eval_fbne_fcc2,
782
        gen_op_eval_fblg_fcc2,
783
        gen_op_eval_fbul_fcc2,
784
        gen_op_eval_fbl_fcc2,
785
        gen_op_eval_fbug_fcc2,
786
        gen_op_eval_fbg_fcc2,
787
        gen_op_eval_fbu_fcc2,
788
        gen_op_eval_ba,
789
        gen_op_eval_fbe_fcc2,
790
        gen_op_eval_fbue_fcc2,
791
        gen_op_eval_fbge_fcc2,
792
        gen_op_eval_fbuge_fcc2,
793
        gen_op_eval_fble_fcc2,
794
        gen_op_eval_fbule_fcc2,
795
        gen_op_eval_fbo_fcc2,
796 796
    },
797 797
    {
798
	gen_op_eval_bn,
799
	gen_op_eval_fbne_fcc3,
800
	gen_op_eval_fblg_fcc3,
801
	gen_op_eval_fbul_fcc3,
802
	gen_op_eval_fbl_fcc3,
803
	gen_op_eval_fbug_fcc3,
804
	gen_op_eval_fbg_fcc3,
805
	gen_op_eval_fbu_fcc3,
806
	gen_op_eval_ba,
807
	gen_op_eval_fbe_fcc3,
808
	gen_op_eval_fbue_fcc3,
809
	gen_op_eval_fbge_fcc3,
810
	gen_op_eval_fbuge_fcc3,
811
	gen_op_eval_fble_fcc3,
812
	gen_op_eval_fbule_fcc3,
813
	gen_op_eval_fbo_fcc3,
798
        gen_op_eval_bn,
799
        gen_op_eval_fbne_fcc3,
800
        gen_op_eval_fblg_fcc3,
801
        gen_op_eval_fbul_fcc3,
802
        gen_op_eval_fbl_fcc3,
803
        gen_op_eval_fbug_fcc3,
804
        gen_op_eval_fbg_fcc3,
805
        gen_op_eval_fbu_fcc3,
806
        gen_op_eval_ba,
807
        gen_op_eval_fbe_fcc3,
808
        gen_op_eval_fbue_fcc3,
809
        gen_op_eval_fbge_fcc3,
810
        gen_op_eval_fbuge_fcc3,
811
        gen_op_eval_fble_fcc3,
812
        gen_op_eval_fbule_fcc3,
813
        gen_op_eval_fbo_fcc3,
814 814
    },
815 815
#else
816 816
    {}, {}, {},
......
820 820
#ifdef TARGET_SPARC64
821 821
static void gen_cond_reg(int cond)
822 822
{
823
	switch (cond) {
824
	case 0x1:
825
	    gen_op_eval_brz();
826
	    break;
827
	case 0x2:
828
	    gen_op_eval_brlez();
829
	    break;
830
	case 0x3:
831
	    gen_op_eval_brlz();
832
	    break;
833
	case 0x5:
834
	    gen_op_eval_brnz();
835
	    break;
836
	case 0x6:
837
	    gen_op_eval_brgz();
838
	    break;
823
        switch (cond) {
824
        case 0x1:
825
            gen_op_eval_brz();
826
            break;
827
        case 0x2:
828
            gen_op_eval_brlez();
829
            break;
830
        case 0x3:
831
            gen_op_eval_brlz();
832
            break;
833
        case 0x5:
834
            gen_op_eval_brnz();
835
            break;
836
        case 0x6:
837
            gen_op_eval_brgz();
838
            break;
839 839
        default:
840
	case 0x7:
841
	    gen_op_eval_brgez();
842
	    break;
843
	}
840
        case 0x7:
841
            gen_op_eval_brgez();
842
            break;
843
        }
844 844
}
845 845
#endif
846 846

  
......
851 851
    target_ulong target = dc->pc + offset;
852 852

  
853 853
    if (cond == 0x0) {
854
	/* unconditional not taken */
855
	if (a) {
856
	    dc->pc = dc->npc + 4;
857
	    dc->npc = dc->pc + 4;
858
	} else {
859
	    dc->pc = dc->npc;
860
	    dc->npc = dc->pc + 4;
861
	}
854
        /* unconditional not taken */
855
        if (a) {
856
            dc->pc = dc->npc + 4;
857
            dc->npc = dc->pc + 4;
858
        } else {
859
            dc->pc = dc->npc;
860
            dc->npc = dc->pc + 4;
861
        }
862 862
    } else if (cond == 0x8) {
863
	/* unconditional taken */
864
	if (a) {
865
	    dc->pc = target;
866
	    dc->npc = dc->pc + 4;
867
	} else {
868
	    dc->pc = dc->npc;
869
	    dc->npc = target;
870
	}
863
        /* unconditional taken */
864
        if (a) {
865
            dc->pc = target;
866
            dc->npc = dc->pc + 4;
867
        } else {
868
            dc->pc = dc->npc;
869
            dc->npc = target;
870
        }
871 871
    } else {
872 872
        flush_T2(dc);
873 873
        gen_cond[cc][cond]();
874
	if (a) {
875
	    gen_branch_a(dc, target, dc->npc);
874
        if (a) {
875
            gen_branch_a(dc, target, dc->npc);
876 876
            dc->is_br = 1;
877
	} else {
877
        } else {
878 878
            dc->pc = dc->npc;
879 879
            dc->jump_pc[0] = target;
880 880
            dc->jump_pc[1] = dc->npc + 4;
881 881
            dc->npc = JUMP_PC;
882
	}
882
        }
883 883
    }
884 884
}
885 885

  
......
890 890
    target_ulong target = dc->pc + offset;
891 891

  
892 892
    if (cond == 0x0) {
893
	/* unconditional not taken */
894
	if (a) {
895
	    dc->pc = dc->npc + 4;
896
	    dc->npc = dc->pc + 4;
897
	} else {
898
	    dc->pc = dc->npc;
899
	    dc->npc = dc->pc + 4;
900
	}
893
        /* unconditional not taken */
894
        if (a) {
895
            dc->pc = dc->npc + 4;
896
            dc->npc = dc->pc + 4;
897
        } else {
898
            dc->pc = dc->npc;
899
            dc->npc = dc->pc + 4;
900
        }
901 901
    } else if (cond == 0x8) {
902
	/* unconditional taken */
903
	if (a) {
904
	    dc->pc = target;
905
	    dc->npc = dc->pc + 4;
906
	} else {
907
	    dc->pc = dc->npc;
908
	    dc->npc = target;
909
	}
902
        /* unconditional taken */
903
        if (a) {
904
            dc->pc = target;
905
            dc->npc = dc->pc + 4;
906
        } else {
907
            dc->pc = dc->npc;
908
            dc->npc = target;
909
        }
910 910
    } else {
911 911
        flush_T2(dc);
912 912
        gen_fcond[cc][cond]();
913
	if (a) {
914
	    gen_branch_a(dc, target, dc->npc);
913
        if (a) {
914
            gen_branch_a(dc, target, dc->npc);
915 915
            dc->is_br = 1;
916
	} else {
916
        } else {
917 917
            dc->pc = dc->npc;
918 918
            dc->jump_pc[0] = target;
919 919
            dc->jump_pc[1] = dc->npc + 4;
920 920
            dc->npc = JUMP_PC;
921
	}
921
        }
922 922
    }
923 923
}
924 924

  
......
932 932
    flush_T2(dc);
933 933
    gen_cond_reg(cond);
934 934
    if (a) {
935
	gen_branch_a(dc, target, dc->npc);
936
	dc->is_br = 1;
935
        gen_branch_a(dc, target, dc->npc);
936
        dc->is_br = 1;
937 937
    } else {
938
	dc->pc = dc->npc;
939
	dc->jump_pc[0] = target;
940
	dc->jump_pc[1] = dc->npc + 4;
941
	dc->npc = JUMP_PC;
938
        dc->pc = dc->npc;
939
        dc->jump_pc[0] = target;
940
        dc->jump_pc[1] = dc->npc + 4;
941
        dc->npc = JUMP_PC;
942 942
    }
943 943
}
944 944

  
......
995 995

  
996 996
    rd = GET_FIELD(insn, 2, 6);
997 997
    switch (opc) {
998
    case 0:			/* branches/sethi */
999
	{
1000
	    unsigned int xop = GET_FIELD(insn, 7, 9);
1001
	    int32_t target;
1002
	    switch (xop) {
998
    case 0:                     /* branches/sethi */
999
        {
1000
            unsigned int xop = GET_FIELD(insn, 7, 9);
1001
            int32_t target;
1002
            switch (xop) {
1003 1003
#ifdef TARGET_SPARC64
1004
	    case 0x1:		/* V9 BPcc */
1005
		{
1006
		    int cc;
1007

  
1008
		    target = GET_FIELD_SP(insn, 0, 18);
1009
		    target = sign_extend(target, 18);
1010
		    target <<= 2;
1011
		    cc = GET_FIELD_SP(insn, 20, 21);
1012
		    if (cc == 0)
1013
			do_branch(dc, target, insn, 0);
1014
		    else if (cc == 2)
1015
			do_branch(dc, target, insn, 1);
1016
		    else
1017
			goto illegal_insn;
1018
		    goto jmp_insn;
1019
		}
1020
	    case 0x3:		/* V9 BPr */
1021
		{
1022
		    target = GET_FIELD_SP(insn, 0, 13) |
1004
            case 0x1:           /* V9 BPcc */
1005
                {
1006
                    int cc;
1007

  
1008
                    target = GET_FIELD_SP(insn, 0, 18);
1009
                    target = sign_extend(target, 18);
1010
                    target <<= 2;
1011
                    cc = GET_FIELD_SP(insn, 20, 21);
1012
                    if (cc == 0)
1013
                        do_branch(dc, target, insn, 0);
1014
                    else if (cc == 2)
1015
                        do_branch(dc, target, insn, 1);
1016
                    else
1017
                        goto illegal_insn;
1018
                    goto jmp_insn;
1019
                }
1020
            case 0x3:           /* V9 BPr */
1021
                {
1022
                    target = GET_FIELD_SP(insn, 0, 13) |
1023 1023
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1024
		    target = sign_extend(target, 16);
1025
		    target <<= 2;
1026
		    rs1 = GET_FIELD(insn, 13, 17);
1027
		    gen_movl_reg_T0(rs1);
1028
		    do_branch_reg(dc, target, insn);
1029
		    goto jmp_insn;
1030
		}
1031
	    case 0x5:		/* V9 FBPcc */
1032
		{
1033
		    int cc = GET_FIELD_SP(insn, 20, 21);
1024
                    target = sign_extend(target, 16);
1025
                    target <<= 2;
1026
                    rs1 = GET_FIELD(insn, 13, 17);
1027
                    gen_movl_reg_T0(rs1);
1028
                    do_branch_reg(dc, target, insn);
1029
                    goto jmp_insn;
1030
                }
1031
            case 0x5:           /* V9 FBPcc */
1032
                {
1033
                    int cc = GET_FIELD_SP(insn, 20, 21);
1034 1034
                    if (gen_trap_ifnofpu(dc))
1035 1035
                        goto jmp_insn;
1036
		    target = GET_FIELD_SP(insn, 0, 18);
1037
		    target = sign_extend(target, 19);
1038
		    target <<= 2;
1039
		    do_fbranch(dc, target, insn, cc);
1040
		    goto jmp_insn;
1041
		}
1036
                    target = GET_FIELD_SP(insn, 0, 18);
1037
                    target = sign_extend(target, 19);
1038
                    target <<= 2;
1039
                    do_fbranch(dc, target, insn, cc);
1040
                    goto jmp_insn;
1041
                }
1042 1042
#else
1043
	    case 0x7:		/* CBN+x */
1044
		{
1045
		    goto ncp_insn;
1046
		}
1047
#endif
1048
	    case 0x2:		/* BN+x */
1049
		{
1050
		    target = GET_FIELD(insn, 10, 31);
1051
		    target = sign_extend(target, 22);
1052
		    target <<= 2;
1053
		    do_branch(dc, target, insn, 0);
1054
		    goto jmp_insn;
1055
		}
1056
	    case 0x6:		/* FBN+x */
1057
		{
1043
            case 0x7:           /* CBN+x */
1044
                {
1045
                    goto ncp_insn;
1046
                }
1047
#endif
1048
            case 0x2:           /* BN+x */
1049
                {
1050
                    target = GET_FIELD(insn, 10, 31);
1051
                    target = sign_extend(target, 22);
1052
                    target <<= 2;
1053
                    do_branch(dc, target, insn, 0);
1054
                    goto jmp_insn;
1055
                }
1056
            case 0x6:           /* FBN+x */
1057
                {
1058 1058
                    if (gen_trap_ifnofpu(dc))
1059 1059
                        goto jmp_insn;
1060
		    target = GET_FIELD(insn, 10, 31);
1061
		    target = sign_extend(target, 22);
1062
		    target <<= 2;
1063
		    do_fbranch(dc, target, insn, 0);
1064
		    goto jmp_insn;
1065
		}
1066
	    case 0x4:		/* SETHI */
1060
                    target = GET_FIELD(insn, 10, 31);
1061
                    target = sign_extend(target, 22);
1062
                    target <<= 2;
1063
                    do_fbranch(dc, target, insn, 0);
1064
                    goto jmp_insn;
1065
                }
1066
            case 0x4:           /* SETHI */
1067 1067
#define OPTIM
1068 1068
#if defined(OPTIM)
1069
		if (rd) { // nop
1069
                if (rd) { // nop
1070 1070
#endif
1071
		    uint32_t value = GET_FIELD(insn, 10, 31);
1072
		    gen_movl_imm_T0(value << 10);
1073
		    gen_movl_T0_reg(rd);
1071
                    uint32_t value = GET_FIELD(insn, 10, 31);
1072
                    gen_movl_imm_T0(value << 10);
1073
                    gen_movl_T0_reg(rd);
1074 1074
#if defined(OPTIM)
1075
		}
1075
                }
1076 1076
#endif
1077
		break;
1078
	    case 0x0:		/* UNIMPL */
1079
	    default:
1077
                break;
1078
            case 0x0:           /* UNIMPL */
1079
            default:
1080 1080
                goto illegal_insn;
1081
	    }
1082
	    break;
1083
	}
1084
	break;
1081
            }
1082
            break;
1083
        }
1084
        break;
1085 1085
    case 1:
1086
	/*CALL*/ {
1087
	    target_long target = GET_FIELDs(insn, 2, 31) << 2;
1086
        /*CALL*/ {
1087
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
1088 1088

  
1089 1089
#ifdef TARGET_SPARC64
1090
	    if (dc->pc == (uint32_t)dc->pc) {
1091
		gen_op_movl_T0_im(dc->pc);
1092
	    } else {
1093
		gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1094
	    }
1090
            if (dc->pc == (uint32_t)dc->pc) {
1091
                gen_op_movl_T0_im(dc->pc);
1092
            } else {
1093
                gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1094
            }
1095 1095
#else
1096
	    gen_op_movl_T0_im(dc->pc);
1096
            gen_op_movl_T0_im(dc->pc);
1097 1097
#endif
1098
	    gen_movl_T0_reg(15);
1099
	    target += dc->pc;
1098
            gen_movl_T0_reg(15);
1099
            target += dc->pc;
1100 1100
            gen_mov_pc_npc(dc);
1101
	    dc->npc = target;
1102
	}
1103
	goto jmp_insn;
1104
    case 2:			/* FPU & Logical Operations */
1105
	{
1106
	    unsigned int xop = GET_FIELD(insn, 7, 12);
1107
	    if (xop == 0x3a) {	/* generate trap */
1101
            dc->npc = target;
1102
        }
1103
        goto jmp_insn;
1104
    case 2:                     /* FPU & Logical Operations */
1105
        {
1106
            unsigned int xop = GET_FIELD(insn, 7, 12);
1107
            if (xop == 0x3a) {  /* generate trap */
1108 1108
                int cond;
1109 1109

  
1110 1110
                rs1 = GET_FIELD(insn, 13, 17);
1111 1111
                gen_movl_reg_T0(rs1);
1112
		if (IS_IMM) {
1113
		    rs2 = GET_FIELD(insn, 25, 31);
1112
                if (IS_IMM) {
1113
                    rs2 = GET_FIELD(insn, 25, 31);
1114 1114
#if defined(OPTIM)
1115
		    if (rs2 != 0) {
1115
                    if (rs2 != 0) {
1116 1116
#endif
1117
			gen_movl_simm_T1(rs2);
1118
			gen_op_add_T1_T0();
1117
                        gen_movl_simm_T1(rs2);
1118
                        gen_op_add_T1_T0();
1119 1119
#if defined(OPTIM)
1120
		    }
1120
                    }
1121 1121
#endif
1122 1122
                } else {
1123 1123
                    rs2 = GET_FIELD(insn, 27, 31);
1124 1124
#if defined(OPTIM)
1125
		    if (rs2 != 0) {
1125
                    if (rs2 != 0) {
1126 1126
#endif
1127
			gen_movl_reg_T1(rs2);
1128
			gen_op_add_T1_T0();
1127
                        gen_movl_reg_T1(rs2);
1128
                        gen_op_add_T1_T0();
1129 1129
#if defined(OPTIM)
1130
		    }
1130
                    }
1131 1131
#endif
1132 1132
                }
1133 1133
                cond = GET_FIELD(insn, 3, 6);
......
1136 1136
                    gen_op_trap_T0();
1137 1137
                } else if (cond != 0) {
1138 1138
#ifdef TARGET_SPARC64
1139
		    /* V9 icc/xcc */
1140
		    int cc = GET_FIELD_SP(insn, 11, 12);
1141
		    flush_T2(dc);
1139
                    /* V9 icc/xcc */
1140
                    int cc = GET_FIELD_SP(insn, 11, 12);
1141
                    flush_T2(dc);
1142 1142
                    save_state(dc);
1143
		    if (cc == 0)
1144
			gen_cond[0][cond]();
1145
		    else if (cc == 2)
1146
			gen_cond[1][cond]();
1147
		    else
1148
			goto illegal_insn;
1143
                    if (cc == 0)
1144
                        gen_cond[0][cond]();
1145
                    else if (cc == 2)
1146
                        gen_cond[1][cond]();
1147
                    else
1148
                        goto illegal_insn;
1149 1149
#else
1150
		    flush_T2(dc);
1150
                    flush_T2(dc);
1151 1151
                    save_state(dc);
1152
		    gen_cond[0][cond]();
1152
                    gen_cond[0][cond]();
1153 1153
#endif
1154 1154
                    gen_op_trapcc_T0();
1155 1155
                }
......
1176 1176
                    gen_movl_T0_reg(rd);
1177 1177
                    break;
1178 1178
#ifdef TARGET_SPARC64
1179
		case 0x2: /* V9 rdccr */
1179
                case 0x2: /* V9 rdccr */
1180 1180
                    gen_op_rdccr();
1181 1181
                    gen_movl_T0_reg(rd);
1182 1182
                    break;
1183
		case 0x3: /* V9 rdasi */
1184
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1183
                case 0x3: /* V9 rdasi */
1184
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1185 1185
                    gen_movl_T0_reg(rd);
1186 1186
                    break;
1187
		case 0x4: /* V9 rdtick */
1187
                case 0x4: /* V9 rdtick */
1188 1188
                    gen_op_rdtick();
1189 1189
                    gen_movl_T0_reg(rd);
1190 1190
                    break;
1191
		case 0x5: /* V9 rdpc */
1192
		    if (dc->pc == (uint32_t)dc->pc) {
1193
			gen_op_movl_T0_im(dc->pc);
1194
		    } else {
1195
			gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1196
		    }
1197
		    gen_movl_T0_reg(rd);
1198
		    break;
1199
		case 0x6: /* V9 rdfprs */
1200
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1191
                case 0x5: /* V9 rdpc */
1192
                    if (dc->pc == (uint32_t)dc->pc) {
1193
                        gen_op_movl_T0_im(dc->pc);
1194
                    } else {
1195
                        gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1196
                    }
1197
                    gen_movl_T0_reg(rd);
1198
                    break;
1199
                case 0x6: /* V9 rdfprs */
1200
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1201 1201
                    gen_movl_T0_reg(rd);
1202 1202
                    break;
1203 1203
                case 0xf: /* V9 membar */
1204 1204
                    break; /* no effect */
1205
		case 0x13: /* Graphics Status */
1205
                case 0x13: /* Graphics Status */
1206 1206
                    if (gen_trap_ifnofpu(dc))
1207 1207
                        goto jmp_insn;
1208
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1208
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1209 1209
                    gen_movl_T0_reg(rd);
1210 1210
                    break;
1211
		case 0x17: /* Tick compare */
1212
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1211
                case 0x17: /* Tick compare */
1212
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1213 1213
                    gen_movl_T0_reg(rd);
1214 1214
                    break;
1215
		case 0x18: /* System tick */
1215
                case 0x18: /* System tick */
1216 1216
                    gen_op_rdstick();
1217 1217
                    gen_movl_T0_reg(rd);
1218 1218
                    break;
1219
		case 0x19: /* System tick compare */
1220
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1219
                case 0x19: /* System tick compare */
1220
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1221 1221
                    gen_movl_T0_reg(rd);
1222 1222
                    break;
1223
		case 0x10: /* Performance Control */
1224
		case 0x11: /* Performance Instrumentation Counter */
1225
		case 0x12: /* Dispatch Control */
1226
		case 0x14: /* Softint set, WO */
1227
		case 0x15: /* Softint clear, WO */
1228
		case 0x16: /* Softint write */
1223
                case 0x10: /* Performance Control */
1224
                case 0x11: /* Performance Instrumentation Counter */
1225
                case 0x12: /* Dispatch Control */
1226
                case 0x14: /* Softint set, WO */
1227
                case 0x15: /* Softint clear, WO */
1228
                case 0x16: /* Softint write */
1229 1229
#endif
1230 1230
                default:
1231 1231
                    goto illegal_insn;
......
1233 1233
#if !defined(CONFIG_USER_ONLY)
1234 1234
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1235 1235
#ifndef TARGET_SPARC64
1236
		if (!supervisor(dc))
1237
		    goto priv_insn;
1236
                if (!supervisor(dc))
1237
                    goto priv_insn;
1238 1238
                gen_op_rdpsr();
1239 1239
#else
1240 1240
                if (!hypervisor(dc))
......
1266 1266
                gen_movl_T0_reg(rd);
1267 1267
                break;
1268 1268
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1269
		if (!supervisor(dc))
1270
		    goto priv_insn;
1269
                if (!supervisor(dc))
1270
                    goto priv_insn;
1271 1271
#ifdef TARGET_SPARC64
1272 1272
                rs1 = GET_FIELD(insn, 13, 17);
1273
		switch (rs1) {
1274
		case 0: // tpc
1275
		    gen_op_rdtpc();
1276
		    break;
1277
		case 1: // tnpc
1278
		    gen_op_rdtnpc();
1279
		    break;
1280
		case 2: // tstate
1281
		    gen_op_rdtstate();
1282
		    break;
1283
		case 3: // tt
1284
		    gen_op_rdtt();
1285
		    break;
1286
		case 4: // tick
1287
		    gen_op_rdtick();
1288
		    break;
1289
		case 5: // tba
1290
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1291
		    break;
1292
		case 6: // pstate
1293
		    gen_op_rdpstate();
1294
		    break;
1295
		case 7: // tl
1296
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1297
		    break;
1298
		case 8: // pil
1299
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1300
		    break;
1301
		case 9: // cwp
1302
		    gen_op_rdcwp();
1303
		    break;
1304
		case 10: // cansave
1305
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1306
		    break;
1307
		case 11: // canrestore
1308
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1309
		    break;
1310
		case 12: // cleanwin
1311
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1312
		    break;
1313
		case 13: // otherwin
1314
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1315
		    break;
1316
		case 14: // wstate
1317
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1318
		    break;
1273
                switch (rs1) {
1274
                case 0: // tpc
1275
                    gen_op_rdtpc();
1276
                    break;
1277
                case 1: // tnpc
1278
                    gen_op_rdtnpc();
1279
                    break;
1280
                case 2: // tstate
1281
                    gen_op_rdtstate();
1282
                    break;
1283
                case 3: // tt
1284
                    gen_op_rdtt();
1285
                    break;
1286
                case 4: // tick
1287
                    gen_op_rdtick();
1288
                    break;
1289
                case 5: // tba
1290
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1291
                    break;
1292
                case 6: // pstate
1293
                    gen_op_rdpstate();
1294
                    break;
1295
                case 7: // tl
1296
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1297
                    break;
1298
                case 8: // pil
1299
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1300
                    break;
1301
                case 9: // cwp
1302
                    gen_op_rdcwp();
1303
                    break;
1304
                case 10: // cansave
1305
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1306
                    break;
1307
                case 11: // canrestore
1308
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1309
                    break;
1310
                case 12: // cleanwin
1311
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1312
                    break;
1313
                case 13: // otherwin
1314
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1315
                    break;
1316
                case 14: // wstate
1317
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1318
                    break;
1319 1319
                case 16: // UA2005 gl
1320 1320
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1321 1321
                    break;
......
1324 1324
                        goto priv_insn;
1325 1325
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1326 1326
                    break;
1327
		case 31: // ver
1328
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1329
		    break;
1330
		case 15: // fq
1331
		default:
1332
		    goto illegal_insn;
1333
		}
1327
                case 31: // ver
1328
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1329
                    break;
1330
                case 15: // fq
1331
                default:
1332
                    goto illegal_insn;
1333
                }
1334 1334
#else
1335
		gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1335
                gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1336 1336
#endif
1337 1337
                gen_movl_T0_reg(rd);
1338 1338
                break;
1339 1339
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1340 1340
#ifdef TARGET_SPARC64
1341
		gen_op_flushw();
1341
                gen_op_flushw();
1342 1342
#else
1343
		if (!supervisor(dc))
1344
		    goto priv_insn;
1345
		gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1343
                if (!supervisor(dc))
1344
                    goto priv_insn;
1345
                gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1346 1346
                gen_movl_T0_reg(rd);
1347 1347
#endif
1348 1348
                break;
1349 1349
#endif
1350
	    } else if (xop == 0x34) {	/* FPU Operations */
1350
            } else if (xop == 0x34) {   /* FPU Operations */
1351 1351
                if (gen_trap_ifnofpu(dc))
1352 1352
                    goto jmp_insn;
1353
		gen_op_clear_ieee_excp_and_FTT();
1353
                gen_op_clear_ieee_excp_and_FTT();
1354 1354
                rs1 = GET_FIELD(insn, 13, 17);
1355
	        rs2 = GET_FIELD(insn, 27, 31);
1356
	        xop = GET_FIELD(insn, 18, 26);
1357
		switch (xop) {
1358
		    case 0x1: /* fmovs */
1359
                	gen_op_load_fpr_FT0(rs2);
1360
			gen_op_store_FT0_fpr(rd);
1361
			break;
1362
		    case 0x5: /* fnegs */
1363
                	gen_op_load_fpr_FT1(rs2);
1364
			gen_op_fnegs();
1365
			gen_op_store_FT0_fpr(rd);
1366
			break;
1367
		    case 0x9: /* fabss */
1368
                	gen_op_load_fpr_FT1(rs2);
1369
			gen_op_fabss();
1370
			gen_op_store_FT0_fpr(rd);
1371
			break;
1372
		    case 0x29: /* fsqrts */
1373
                	gen_op_load_fpr_FT1(rs2);
1374
			gen_op_fsqrts();
1375
			gen_op_store_FT0_fpr(rd);
1376
			break;
1377
		    case 0x2a: /* fsqrtd */
1378
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1379
			gen_op_fsqrtd();
1380
			gen_op_store_DT0_fpr(DFPREG(rd));
1381
			break;
1382
		    case 0x2b: /* fsqrtq */
1383
		        goto nfpu_insn;
1384
		    case 0x41:
1385
                	gen_op_load_fpr_FT0(rs1);
1386
                	gen_op_load_fpr_FT1(rs2);
1387
			gen_op_fadds();
1388
			gen_op_store_FT0_fpr(rd);
1389
			break;
1390
		    case 0x42:
1391
                	gen_op_load_fpr_DT0(DFPREG(rs1));
1392
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1393
			gen_op_faddd();
1394
			gen_op_store_DT0_fpr(DFPREG(rd));
1395
			break;
1396
		    case 0x43: /* faddq */
1397
		        goto nfpu_insn;
1398
		    case 0x45:
1399
                	gen_op_load_fpr_FT0(rs1);
1400
                	gen_op_load_fpr_FT1(rs2);
1401
			gen_op_fsubs();
1402
			gen_op_store_FT0_fpr(rd);
1403
			break;
1404
		    case 0x46:
1405
                	gen_op_load_fpr_DT0(DFPREG(rs1));
1406
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1407
			gen_op_fsubd();
1408
			gen_op_store_DT0_fpr(DFPREG(rd));
1409
			break;
1410
		    case 0x47: /* fsubq */
1411
		        goto nfpu_insn;
1412
		    case 0x49:
1413
                	gen_op_load_fpr_FT0(rs1);
1414
                	gen_op_load_fpr_FT1(rs2);
1415
			gen_op_fmuls();
1416
			gen_op_store_FT0_fpr(rd);
1417
			break;
1418
		    case 0x4a:
1419
                	gen_op_load_fpr_DT0(DFPREG(rs1));
1420
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1421
			gen_op_fmuld();
1422
			gen_op_store_DT0_fpr(rd);
1423
			break;
1424
		    case 0x4b: /* fmulq */
1425
		        goto nfpu_insn;
1426
		    case 0x4d:
1427
                	gen_op_load_fpr_FT0(rs1);
1428
                	gen_op_load_fpr_FT1(rs2);
1429
			gen_op_fdivs();
1430
			gen_op_store_FT0_fpr(rd);
1431
			break;
1432
		    case 0x4e:
1433
                	gen_op_load_fpr_DT0(DFPREG(rs1));
1434
			gen_op_load_fpr_DT1(DFPREG(rs2));
1435
			gen_op_fdivd();
1436
			gen_op_store_DT0_fpr(DFPREG(rd));
1437
			break;
1438
		    case 0x4f: /* fdivq */
1439
		        goto nfpu_insn;
1440
		    case 0x69:
1441
                	gen_op_load_fpr_FT0(rs1);
1442
                	gen_op_load_fpr_FT1(rs2);
1443
			gen_op_fsmuld();
1444
			gen_op_store_DT0_fpr(DFPREG(rd));
1445
			break;
1446
		    case 0x6e: /* fdmulq */
1447
		        goto nfpu_insn;
1448
		    case 0xc4:
1449
                	gen_op_load_fpr_FT1(rs2);
1450
			gen_op_fitos();
1451
			gen_op_store_FT0_fpr(rd);
1452
			break;
1453
		    case 0xc6:
1454
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1455
			gen_op_fdtos();
1456
			gen_op_store_FT0_fpr(rd);
1457
			break;
1458
		    case 0xc7: /* fqtos */
1459
		        goto nfpu_insn;
1460
		    case 0xc8:
1461
                	gen_op_load_fpr_FT1(rs2);
1462
			gen_op_fitod();
1463
			gen_op_store_DT0_fpr(DFPREG(rd));
1464
			break;
1465
		    case 0xc9:
1466
                	gen_op_load_fpr_FT1(rs2);
1467
			gen_op_fstod();
1468
			gen_op_store_DT0_fpr(DFPREG(rd));
1469
			break;
1470
		    case 0xcb: /* fqtod */
1471
		        goto nfpu_insn;
1472
		    case 0xcc: /* fitoq */
1473
		        goto nfpu_insn;
1474
		    case 0xcd: /* fstoq */
1475
		        goto nfpu_insn;
1476
		    case 0xce: /* fdtoq */
1477
		        goto nfpu_insn;
1478
		    case 0xd1:
1479
                	gen_op_load_fpr_FT1(rs2);
1480
			gen_op_fstoi();
1481
			gen_op_store_FT0_fpr(rd);
1482
			break;
1483
		    case 0xd2:
1484
                	gen_op_load_fpr_DT1(rs2);
1485
			gen_op_fdtoi();
1486
			gen_op_store_FT0_fpr(rd);
1487
			break;
1488
		    case 0xd3: /* fqtoi */
1489
		        goto nfpu_insn;
1355
                rs2 = GET_FIELD(insn, 27, 31);
1356
                xop = GET_FIELD(insn, 18, 26);
1357
                switch (xop) {
1358
                    case 0x1: /* fmovs */
1359
                        gen_op_load_fpr_FT0(rs2);
1360
                        gen_op_store_FT0_fpr(rd);
1361
                        break;
1362
                    case 0x5: /* fnegs */
1363
                        gen_op_load_fpr_FT1(rs2);
1364
                        gen_op_fnegs();
1365
                        gen_op_store_FT0_fpr(rd);
1366
                        break;
1367
                    case 0x9: /* fabss */
1368
                        gen_op_load_fpr_FT1(rs2);
1369
                        gen_op_fabss();
1370
                        gen_op_store_FT0_fpr(rd);
1371
                        break;
1372
                    case 0x29: /* fsqrts */
1373
                        gen_op_load_fpr_FT1(rs2);
1374
                        gen_op_fsqrts();
1375
                        gen_op_store_FT0_fpr(rd);
1376
                        break;
1377
                    case 0x2a: /* fsqrtd */
1378
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1379
                        gen_op_fsqrtd();
1380
                        gen_op_store_DT0_fpr(DFPREG(rd));
1381
                        break;
1382
                    case 0x2b: /* fsqrtq */
1383
                        goto nfpu_insn;
1384
                    case 0x41:
1385
                        gen_op_load_fpr_FT0(rs1);
1386
                        gen_op_load_fpr_FT1(rs2);
1387
                        gen_op_fadds();
1388
                        gen_op_store_FT0_fpr(rd);
1389
                        break;
1390
                    case 0x42:
1391
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1392
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1393
                        gen_op_faddd();
1394
                        gen_op_store_DT0_fpr(DFPREG(rd));
1395
                        break;
1396
                    case 0x43: /* faddq */
1397
                        goto nfpu_insn;
1398
                    case 0x45:
1399
                        gen_op_load_fpr_FT0(rs1);
1400
                        gen_op_load_fpr_FT1(rs2);
1401
                        gen_op_fsubs();
1402
                        gen_op_store_FT0_fpr(rd);
1403
                        break;
1404
                    case 0x46:
1405
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1406
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1407
                        gen_op_fsubd();
1408
                        gen_op_store_DT0_fpr(DFPREG(rd));
1409
                        break;
1410
                    case 0x47: /* fsubq */
1411
                        goto nfpu_insn;
1412
                    case 0x49:
1413
                        gen_op_load_fpr_FT0(rs1);
1414
                        gen_op_load_fpr_FT1(rs2);
1415
                        gen_op_fmuls();
1416
                        gen_op_store_FT0_fpr(rd);
1417
                        break;
1418
                    case 0x4a:
1419
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1420
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1421
                        gen_op_fmuld();
1422
                        gen_op_store_DT0_fpr(rd);
1423
                        break;
1424
                    case 0x4b: /* fmulq */
1425
                        goto nfpu_insn;
1426
                    case 0x4d:
1427
                        gen_op_load_fpr_FT0(rs1);
1428
                        gen_op_load_fpr_FT1(rs2);
1429
                        gen_op_fdivs();
1430
                        gen_op_store_FT0_fpr(rd);
1431
                        break;
1432
                    case 0x4e:
1433
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1434
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1435
                        gen_op_fdivd();
1436
                        gen_op_store_DT0_fpr(DFPREG(rd));
1437
                        break;
1438
                    case 0x4f: /* fdivq */
1439
                        goto nfpu_insn;
1440
                    case 0x69:
1441
                        gen_op_load_fpr_FT0(rs1);
1442
                        gen_op_load_fpr_FT1(rs2);
1443
                        gen_op_fsmuld();
1444
                        gen_op_store_DT0_fpr(DFPREG(rd));
1445
                        break;
1446
                    case 0x6e: /* fdmulq */
1447
                        goto nfpu_insn;
1448
                    case 0xc4:
1449
                        gen_op_load_fpr_FT1(rs2);
1450
                        gen_op_fitos();
1451
                        gen_op_store_FT0_fpr(rd);
1452
                        break;
1453
                    case 0xc6:
1454
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1455
                        gen_op_fdtos();
1456
                        gen_op_store_FT0_fpr(rd);
1457
                        break;
1458
                    case 0xc7: /* fqtos */
1459
                        goto nfpu_insn;
1460
                    case 0xc8:
1461
                        gen_op_load_fpr_FT1(rs2);
1462
                        gen_op_fitod();
1463
                        gen_op_store_DT0_fpr(DFPREG(rd));
1464
                        break;
1465
                    case 0xc9:
1466
                        gen_op_load_fpr_FT1(rs2);
1467
                        gen_op_fstod();
1468
                        gen_op_store_DT0_fpr(DFPREG(rd));
1469
                        break;
1470
                    case 0xcb: /* fqtod */
1471
                        goto nfpu_insn;
1472
                    case 0xcc: /* fitoq */
1473
                        goto nfpu_insn;
1474
                    case 0xcd: /* fstoq */
1475
                        goto nfpu_insn;
1476
                    case 0xce: /* fdtoq */
1477
                        goto nfpu_insn;
1478
                    case 0xd1:
1479
                        gen_op_load_fpr_FT1(rs2);
1480
                        gen_op_fstoi();
1481
                        gen_op_store_FT0_fpr(rd);
1482
                        break;
1483
                    case 0xd2:
1484
                        gen_op_load_fpr_DT1(rs2);
1485
                        gen_op_fdtoi();
1486
                        gen_op_store_FT0_fpr(rd);
1487
                        break;
1488
                    case 0xd3: /* fqtoi */
1489
                        goto nfpu_insn;
1490 1490
#ifdef TARGET_SPARC64
1491
		    case 0x2: /* V9 fmovd */
1492
                	gen_op_load_fpr_DT0(DFPREG(rs2));
1493
			gen_op_store_DT0_fpr(DFPREG(rd));
1494
			break;
1495
		    case 0x6: /* V9 fnegd */
1496
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1497
			gen_op_fnegd();
1498
			gen_op_store_DT0_fpr(DFPREG(rd));
1499
			break;
1500
		    case 0xa: /* V9 fabsd */
1501
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1502
			gen_op_fabsd();
1503
			gen_op_store_DT0_fpr(DFPREG(rd));
1504
			break;
1505
		    case 0x81: /* V9 fstox */
1506
                	gen_op_load_fpr_FT1(rs2);
1507
			gen_op_fstox();
1508
			gen_op_store_DT0_fpr(DFPREG(rd));
1509
			break;
1510
		    case 0x82: /* V9 fdtox */
1511
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1512
			gen_op_fdtox();
1513
			gen_op_store_DT0_fpr(DFPREG(rd));
1514
			break;
1515
		    case 0x84: /* V9 fxtos */
1516
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1517
			gen_op_fxtos();
1518
			gen_op_store_FT0_fpr(rd);
1519
			break;
1520
		    case 0x88: /* V9 fxtod */
1521
                	gen_op_load_fpr_DT1(DFPREG(rs2));
1522
			gen_op_fxtod();
1523
			gen_op_store_DT0_fpr(DFPREG(rd));
1524
			break;
1525
		    case 0x3: /* V9 fmovq */
1526
		    case 0x7: /* V9 fnegq */
1527
		    case 0xb: /* V9 fabsq */
1528
		    case 0x83: /* V9 fqtox */
1529
		    case 0x8c: /* V9 fxtoq */
1530
		        goto nfpu_insn;
1531
#endif
1532
		    default:
1533
                	goto illegal_insn;
1534
		}
1535
	    } else if (xop == 0x35) {	/* FPU Operations */
1491
                    case 0x2: /* V9 fmovd */
1492
                        gen_op_load_fpr_DT0(DFPREG(rs2));
1493
                        gen_op_store_DT0_fpr(DFPREG(rd));
1494
                        break;
1495
                    case 0x6: /* V9 fnegd */
1496
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1497
                        gen_op_fnegd();
1498
                        gen_op_store_DT0_fpr(DFPREG(rd));
1499
                        break;
1500
                    case 0xa: /* V9 fabsd */
1501
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1502
                        gen_op_fabsd();
1503
                        gen_op_store_DT0_fpr(DFPREG(rd));
1504
                        break;
1505
                    case 0x81: /* V9 fstox */
1506
                        gen_op_load_fpr_FT1(rs2);
1507
                        gen_op_fstox();
1508
                        gen_op_store_DT0_fpr(DFPREG(rd));
1509
                        break;
1510
                    case 0x82: /* V9 fdtox */
1511
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1512
                        gen_op_fdtox();
1513
                        gen_op_store_DT0_fpr(DFPREG(rd));
1514
                        break;
1515
                    case 0x84: /* V9 fxtos */
1516
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1517
                        gen_op_fxtos();
1518
                        gen_op_store_FT0_fpr(rd);
1519
                        break;
1520
                    case 0x88: /* V9 fxtod */
1521
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1522
                        gen_op_fxtod();
1523
                        gen_op_store_DT0_fpr(DFPREG(rd));
1524
                        break;
1525
                    case 0x3: /* V9 fmovq */
1526
                    case 0x7: /* V9 fnegq */
1527
                    case 0xb: /* V9 fabsq */
1528
                    case 0x83: /* V9 fqtox */
1529
                    case 0x8c: /* V9 fxtoq */
1530
                        goto nfpu_insn;
1531
#endif
1532
                    default:
1533
                        goto illegal_insn;
1534
                }
1535
            } else if (xop == 0x35) {   /* FPU Operations */
1536 1536
#ifdef TARGET_SPARC64
1537
		int cond;
1537
                int cond;
1538 1538
#endif
1539 1539
                if (gen_trap_ifnofpu(dc))
1540 1540
                    goto jmp_insn;
1541
		gen_op_clear_ieee_excp_and_FTT();
1541
                gen_op_clear_ieee_excp_and_FTT();
1542 1542
                rs1 = GET_FIELD(insn, 13, 17);
1543
	        rs2 = GET_FIELD(insn, 27, 31);
1544
	        xop = GET_FIELD(insn, 18, 26);
1543
                rs2 = GET_FIELD(insn, 27, 31);
1544
                xop = GET_FIELD(insn, 18, 26);
1545 1545
#ifdef TARGET_SPARC64
1546
		if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1547
		    cond = GET_FIELD_SP(insn, 14, 17);
1548
		    gen_op_load_fpr_FT0(rd);
1549
		    gen_op_load_fpr_FT1(rs2);
1550
		    rs1 = GET_FIELD(insn, 13, 17);
1551
		    gen_movl_reg_T0(rs1);
1552
		    flush_T2(dc);
1553
		    gen_cond_reg(cond);
1554
		    gen_op_fmovs_cc();
1555
		    gen_op_store_FT0_fpr(rd);
1556
		    break;
1557
		} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1558
		    cond = GET_FIELD_SP(insn, 14, 17);
1559
		    gen_op_load_fpr_DT0(rd);
1560
		    gen_op_load_fpr_DT1(rs2);
... This diff was truncated because it exceeds the maximum size that can be displayed.

Also available in: Unified diff