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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sun4u System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 3475187d | bellard | #include "vl.h" |
25 | 83469015 | bellard | #include "m48t59.h" |
26 | 3475187d | bellard | |
27 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
28 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
29 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
30 | 75956cf0 | pbrook | #define PROM_SIZE_MAX (512 * 1024) |
31 | f930d07e | blueswir1 | #define PROM_ADDR 0x1fff0000000ULL |
32 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
33 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
34 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
35 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
36 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
37 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
38 | 3475187d | bellard | |
39 | 3475187d | bellard | /* TSC handling */
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40 | 3475187d | bellard | |
41 | 3475187d | bellard | uint64_t cpu_get_tsc() |
42 | 3475187d | bellard | { |
43 | 3475187d | bellard | return qemu_get_clock(vm_clock);
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44 | 3475187d | bellard | } |
45 | 3475187d | bellard | |
46 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
47 | 3475187d | bellard | { |
48 | 3475187d | bellard | return 0; |
49 | 3475187d | bellard | } |
50 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
51 | 3475187d | bellard | { |
52 | 3475187d | bellard | return 0; |
53 | 3475187d | bellard | } |
54 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
55 | 3475187d | bellard | { |
56 | 3475187d | bellard | return 0; |
57 | 3475187d | bellard | } |
58 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
59 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
60 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
61 | 3475187d | bellard | void DMA_run (void) {} |
62 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
63 | 3475187d | bellard | void DMA_register_channel (int nchan, |
64 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
65 | 3475187d | bellard | void *opaque)
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66 | 3475187d | bellard | { |
67 | 3475187d | bellard | } |
68 | 3475187d | bellard | |
69 | 83469015 | bellard | /* NVRAM helpers */
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70 | 0fe5ea89 | blueswir1 | static void nvram_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value) |
71 | 3475187d | bellard | { |
72 | 819385c5 | bellard | m48t59_write(nvram, addr, value); |
73 | 3475187d | bellard | } |
74 | 3475187d | bellard | |
75 | 0fe5ea89 | blueswir1 | static uint8_t nvram_get_byte (m48t59_t *nvram, uint32_t addr)
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76 | 3475187d | bellard | { |
77 | 819385c5 | bellard | return m48t59_read(nvram, addr);
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78 | 3475187d | bellard | } |
79 | 3475187d | bellard | |
80 | 0fe5ea89 | blueswir1 | static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
81 | 83469015 | bellard | { |
82 | 0fe5ea89 | blueswir1 | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
83 | 0fe5ea89 | blueswir1 | m48t59_write(nvram, addr++, value & 0xff);
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84 | 83469015 | bellard | } |
85 | 83469015 | bellard | |
86 | 0fe5ea89 | blueswir1 | static uint16_t nvram_get_word (m48t59_t *nvram, uint32_t addr)
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87 | 83469015 | bellard | { |
88 | 83469015 | bellard | uint16_t tmp; |
89 | 83469015 | bellard | |
90 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 8;
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91 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1);
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92 | 83469015 | bellard | |
93 | 83469015 | bellard | return tmp;
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94 | 83469015 | bellard | } |
95 | 83469015 | bellard | |
96 | 0fe5ea89 | blueswir1 | static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
97 | 83469015 | bellard | { |
98 | 0fe5ea89 | blueswir1 | m48t59_write(nvram, addr++, value >> 24);
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99 | 0fe5ea89 | blueswir1 | m48t59_write(nvram, addr++, (value >> 16) & 0xff); |
100 | 0fe5ea89 | blueswir1 | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
101 | 0fe5ea89 | blueswir1 | m48t59_write(nvram, addr++, value & 0xff);
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102 | 83469015 | bellard | } |
103 | 83469015 | bellard | |
104 | 0fe5ea89 | blueswir1 | static void nvram_set_string (m48t59_t *nvram, uint32_t addr, |
105 | 3475187d | bellard | const unsigned char *str, uint32_t max) |
106 | 3475187d | bellard | { |
107 | 0fe5ea89 | blueswir1 | unsigned int i; |
108 | 3475187d | bellard | |
109 | 3475187d | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
110 | 819385c5 | bellard | m48t59_write(nvram, addr + i, str[i]); |
111 | 3475187d | bellard | } |
112 | 819385c5 | bellard | m48t59_write(nvram, addr + max - 1, '\0'); |
113 | 3475187d | bellard | } |
114 | 3475187d | bellard | |
115 | 0fe5ea89 | blueswir1 | static uint16_t nvram_crc_update (uint16_t prev, uint16_t value)
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116 | 83469015 | bellard | { |
117 | 83469015 | bellard | uint16_t tmp; |
118 | 83469015 | bellard | uint16_t pd, pd1, pd2; |
119 | 83469015 | bellard | |
120 | 83469015 | bellard | tmp = prev >> 8;
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121 | 83469015 | bellard | pd = prev ^ value; |
122 | 83469015 | bellard | pd1 = pd & 0x000F;
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123 | 83469015 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
124 | 83469015 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
125 | 83469015 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
126 | 83469015 | bellard | |
127 | 83469015 | bellard | return tmp;
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128 | 83469015 | bellard | } |
129 | 83469015 | bellard | |
130 | 0fe5ea89 | blueswir1 | static uint16_t nvram_compute_crc (m48t59_t *nvram, uint32_t start,
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131 | 0fe5ea89 | blueswir1 | uint32_t count) |
132 | 83469015 | bellard | { |
133 | 83469015 | bellard | uint32_t i; |
134 | 83469015 | bellard | uint16_t crc = 0xFFFF;
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135 | 83469015 | bellard | int odd;
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136 | 83469015 | bellard | |
137 | 83469015 | bellard | odd = count & 1;
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138 | 83469015 | bellard | count &= ~1;
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139 | 83469015 | bellard | for (i = 0; i != count; i++) { |
140 | 0fe5ea89 | blueswir1 | crc = nvram_crc_update(crc, nvram_get_word(nvram, start + i)); |
141 | 83469015 | bellard | } |
142 | 83469015 | bellard | if (odd) {
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143 | 0fe5ea89 | blueswir1 | crc = nvram_crc_update(crc, nvram_get_byte(nvram, start + i) << 8);
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144 | 83469015 | bellard | } |
145 | 83469015 | bellard | |
146 | 83469015 | bellard | return crc;
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147 | 83469015 | bellard | } |
148 | 3475187d | bellard | |
149 | 66508601 | blueswir1 | static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
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150 | 66508601 | blueswir1 | const unsigned char *str) |
151 | 66508601 | blueswir1 | { |
152 | 66508601 | blueswir1 | uint32_t len; |
153 | 66508601 | blueswir1 | |
154 | 66508601 | blueswir1 | len = strlen(str) + 1;
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155 | 0fe5ea89 | blueswir1 | nvram_set_string(nvram, addr, str, len); |
156 | 66508601 | blueswir1 | |
157 | 66508601 | blueswir1 | return addr + len;
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158 | 66508601 | blueswir1 | } |
159 | 66508601 | blueswir1 | |
160 | 66508601 | blueswir1 | static void nvram_finish_partition (m48t59_t *nvram, uint32_t start, |
161 | 66508601 | blueswir1 | uint32_t end) |
162 | 66508601 | blueswir1 | { |
163 | 66508601 | blueswir1 | unsigned int i, sum; |
164 | 66508601 | blueswir1 | |
165 | 66508601 | blueswir1 | // Length divided by 16
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166 | 66508601 | blueswir1 | m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff); |
167 | 66508601 | blueswir1 | m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff); |
168 | 66508601 | blueswir1 | // Checksum
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169 | 66508601 | blueswir1 | sum = m48t59_read(nvram, start); |
170 | 66508601 | blueswir1 | for (i = 0; i < 14; i++) { |
171 | 66508601 | blueswir1 | sum += m48t59_read(nvram, start + 2 + i);
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172 | 66508601 | blueswir1 | sum = (sum + ((sum & 0xff00) >> 8)) & 0xff; |
173 | 66508601 | blueswir1 | } |
174 | 66508601 | blueswir1 | m48t59_write(nvram, start + 1, sum & 0xff); |
175 | 66508601 | blueswir1 | } |
176 | 66508601 | blueswir1 | |
177 | 3475187d | bellard | extern int nographic; |
178 | 3475187d | bellard | |
179 | 83469015 | bellard | int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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180 | 83469015 | bellard | const unsigned char *arch, |
181 | 83469015 | bellard | uint32_t RAM_size, int boot_device,
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182 | 83469015 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
183 | 83469015 | bellard | const char *cmdline, |
184 | 83469015 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
185 | 83469015 | bellard | uint32_t NVRAM_image, |
186 | 83469015 | bellard | int width, int height, int depth) |
187 | 83469015 | bellard | { |
188 | 83469015 | bellard | uint16_t crc; |
189 | 66508601 | blueswir1 | unsigned int i; |
190 | 66508601 | blueswir1 | uint32_t start, end; |
191 | 83469015 | bellard | |
192 | 83469015 | bellard | /* Set parameters for Open Hack'Ware BIOS */
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193 | 0fe5ea89 | blueswir1 | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
194 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
195 | 0fe5ea89 | blueswir1 | nvram_set_word(nvram, 0x14, NVRAM_size);
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196 | 0fe5ea89 | blueswir1 | nvram_set_string(nvram, 0x20, arch, 16); |
197 | 0fe5ea89 | blueswir1 | nvram_set_byte(nvram, 0x2f, nographic & 0xff); |
198 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x30, RAM_size);
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199 | 0fe5ea89 | blueswir1 | nvram_set_byte(nvram, 0x34, boot_device);
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200 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x38, kernel_image);
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201 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x3C, kernel_size);
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202 | 3475187d | bellard | if (cmdline) {
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203 | 83469015 | bellard | /* XXX: put the cmdline in NVRAM too ? */
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204 | 83469015 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
205 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
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206 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x44, strlen(cmdline));
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207 | 83469015 | bellard | } else {
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208 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x40, 0); |
209 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x44, 0); |
210 | 3475187d | bellard | } |
211 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x48, initrd_image);
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212 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x4C, initrd_size);
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213 | 0fe5ea89 | blueswir1 | nvram_set_lword(nvram, 0x50, NVRAM_image);
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214 | 83469015 | bellard | |
215 | 0fe5ea89 | blueswir1 | nvram_set_word(nvram, 0x54, width);
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216 | 0fe5ea89 | blueswir1 | nvram_set_word(nvram, 0x56, height);
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217 | 0fe5ea89 | blueswir1 | nvram_set_word(nvram, 0x58, depth);
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218 | 0fe5ea89 | blueswir1 | crc = nvram_compute_crc(nvram, 0x00, 0xF8); |
219 | 0fe5ea89 | blueswir1 | nvram_set_word(nvram, 0xFC, crc);
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220 | 83469015 | bellard | |
221 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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222 | 66508601 | blueswir1 | // Variable partition
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223 | f19e918d | blueswir1 | start = 256;
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224 | 66508601 | blueswir1 | m48t59_write(nvram, start, 0x70);
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225 | 0fe5ea89 | blueswir1 | nvram_set_string(nvram, start + 4, "system", 12); |
226 | 66508601 | blueswir1 | |
227 | 66508601 | blueswir1 | end = start + 16;
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228 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
229 | 66508601 | blueswir1 | end = nvram_set_var(nvram, end, prom_envs[i]); |
230 | 66508601 | blueswir1 | |
231 | 66508601 | blueswir1 | m48t59_write(nvram, end++ , 0);
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232 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
233 | 66508601 | blueswir1 | nvram_finish_partition(nvram, start, end); |
234 | 66508601 | blueswir1 | |
235 | 66508601 | blueswir1 | // free partition
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236 | 66508601 | blueswir1 | start = end; |
237 | 66508601 | blueswir1 | m48t59_write(nvram, start, 0x7f);
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238 | 0fe5ea89 | blueswir1 | nvram_set_string(nvram, start + 4, "free", 12); |
239 | 66508601 | blueswir1 | |
240 | 66508601 | blueswir1 | end = 0x1fd0;
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241 | 66508601 | blueswir1 | nvram_finish_partition(nvram, start, end); |
242 | 66508601 | blueswir1 | |
243 | 83469015 | bellard | return 0; |
244 | 3475187d | bellard | } |
245 | 3475187d | bellard | |
246 | 3475187d | bellard | void pic_info()
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247 | 3475187d | bellard | { |
248 | 3475187d | bellard | } |
249 | 3475187d | bellard | |
250 | 3475187d | bellard | void irq_info()
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251 | 3475187d | bellard | { |
252 | 3475187d | bellard | } |
253 | 3475187d | bellard | |
254 | 83469015 | bellard | void qemu_system_powerdown(void) |
255 | 3475187d | bellard | { |
256 | 3475187d | bellard | } |
257 | 3475187d | bellard | |
258 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
259 | c68ea704 | bellard | { |
260 | c68ea704 | bellard | CPUState *env = opaque; |
261 | 20c9f095 | blueswir1 | |
262 | c68ea704 | bellard | cpu_reset(env); |
263 | 20c9f095 | blueswir1 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
264 | 20c9f095 | blueswir1 | ptimer_run(env->tick, 0);
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265 | 20c9f095 | blueswir1 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); |
266 | 20c9f095 | blueswir1 | ptimer_run(env->stick, 0);
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267 | 20c9f095 | blueswir1 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); |
268 | 20c9f095 | blueswir1 | ptimer_run(env->hstick, 0);
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269 | 20c9f095 | blueswir1 | } |
270 | 20c9f095 | blueswir1 | |
271 | 20c9f095 | blueswir1 | void tick_irq(void *opaque) |
272 | 20c9f095 | blueswir1 | { |
273 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
274 | 20c9f095 | blueswir1 | |
275 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
276 | 20c9f095 | blueswir1 | } |
277 | 20c9f095 | blueswir1 | |
278 | 20c9f095 | blueswir1 | void stick_irq(void *opaque) |
279 | 20c9f095 | blueswir1 | { |
280 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
281 | 20c9f095 | blueswir1 | |
282 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
283 | 20c9f095 | blueswir1 | } |
284 | 20c9f095 | blueswir1 | |
285 | 20c9f095 | blueswir1 | void hstick_irq(void *opaque) |
286 | 20c9f095 | blueswir1 | { |
287 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
288 | 20c9f095 | blueswir1 | |
289 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
290 | c68ea704 | bellard | } |
291 | c68ea704 | bellard | |
292 | f19e918d | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
293 | f19e918d | blueswir1 | { |
294 | f19e918d | blueswir1 | } |
295 | f19e918d | blueswir1 | |
296 | 83469015 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
297 | 83469015 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
298 | 83469015 | bellard | static const int ide_irq[2] = { 14, 15 }; |
299 | 3475187d | bellard | |
300 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
301 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
302 | 83469015 | bellard | |
303 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
304 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
305 | 83469015 | bellard | |
306 | 83469015 | bellard | static fdctrl_t *floppy_controller;
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307 | 3475187d | bellard | |
308 | 3475187d | bellard | /* Sun4u hardware initialisation */
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309 | 6ac0e82d | balrog | static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device, |
310 | 3475187d | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
311 | 3475187d | bellard | const char *kernel_filename, const char *kernel_cmdline, |
312 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
313 | 3475187d | bellard | { |
314 | c68ea704 | bellard | CPUState *env; |
315 | 3475187d | bellard | char buf[1024]; |
316 | 83469015 | bellard | m48t59_t *nvram; |
317 | 3475187d | bellard | int ret, linux_boot;
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318 | 3475187d | bellard | unsigned int i; |
319 | 83469015 | bellard | long prom_offset, initrd_size, kernel_size;
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320 | 83469015 | bellard | PCIBus *pci_bus; |
321 | 20c9f095 | blueswir1 | QEMUBH *bh; |
322 | f19e918d | blueswir1 | qemu_irq *irq; |
323 | 3475187d | bellard | |
324 | 3475187d | bellard | linux_boot = (kernel_filename != NULL);
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325 | 3475187d | bellard | |
326 | 62724a37 | blueswir1 | /* init CPUs */
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327 | 62724a37 | blueswir1 | if (cpu_model == NULL) |
328 | 62724a37 | blueswir1 | cpu_model = "TI UltraSparc II";
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329 | aaed909a | bellard | env = cpu_init(cpu_model); |
330 | aaed909a | bellard | if (!env) {
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331 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
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332 | 62724a37 | blueswir1 | exit(1);
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333 | 62724a37 | blueswir1 | } |
334 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
335 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
336 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
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337 | 20c9f095 | blueswir1 | |
338 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
339 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
340 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
|
341 | 20c9f095 | blueswir1 | |
342 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
343 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
344 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
|
345 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
346 | c68ea704 | bellard | qemu_register_reset(main_cpu_reset, env); |
347 | 20c9f095 | blueswir1 | main_cpu_reset(env); |
348 | c68ea704 | bellard | |
349 | 3475187d | bellard | /* allocate RAM */
|
350 | 3475187d | bellard | cpu_register_physical_memory(0, ram_size, 0); |
351 | 3475187d | bellard | |
352 | 83469015 | bellard | prom_offset = ram_size + vga_ram_size; |
353 | 5fafdf24 | ths | cpu_register_physical_memory(PROM_ADDR, |
354 | 5fafdf24 | ths | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
355 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
356 | 3475187d | bellard | |
357 | 1192dad8 | j_mayer | if (bios_name == NULL) |
358 | 1192dad8 | j_mayer | bios_name = PROM_FILENAME; |
359 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
360 | f19e918d | blueswir1 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
361 | 3475187d | bellard | if (ret < 0) { |
362 | f930d07e | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
363 | f930d07e | blueswir1 | buf); |
364 | f930d07e | blueswir1 | exit(1);
|
365 | 3475187d | bellard | } |
366 | 3475187d | bellard | |
367 | 3475187d | bellard | kernel_size = 0;
|
368 | 83469015 | bellard | initrd_size = 0;
|
369 | 3475187d | bellard | if (linux_boot) {
|
370 | b3783731 | bellard | /* XXX: put correct offset */
|
371 | 74287114 | ths | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
372 | 3475187d | bellard | if (kernel_size < 0) |
373 | f930d07e | blueswir1 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
374 | f930d07e | blueswir1 | if (kernel_size < 0) |
375 | f930d07e | blueswir1 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
376 | 3475187d | bellard | if (kernel_size < 0) { |
377 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
378 | 3475187d | bellard | kernel_filename); |
379 | f930d07e | blueswir1 | exit(1);
|
380 | 3475187d | bellard | } |
381 | 3475187d | bellard | |
382 | 3475187d | bellard | /* load initrd */
|
383 | 3475187d | bellard | if (initrd_filename) {
|
384 | 3475187d | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
385 | 3475187d | bellard | if (initrd_size < 0) { |
386 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
387 | 3475187d | bellard | initrd_filename); |
388 | 3475187d | bellard | exit(1);
|
389 | 3475187d | bellard | } |
390 | 3475187d | bellard | } |
391 | 3475187d | bellard | if (initrd_size > 0) { |
392 | f930d07e | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
393 | f930d07e | blueswir1 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
394 | f930d07e | blueswir1 | == 0x48647253) { // HdrS |
395 | f930d07e | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
396 | f930d07e | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
397 | f930d07e | blueswir1 | break;
|
398 | f930d07e | blueswir1 | } |
399 | f930d07e | blueswir1 | } |
400 | 3475187d | bellard | } |
401 | 3475187d | bellard | } |
402 | 502a5395 | pbrook | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
|
403 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
404 | 75956cf0 | pbrook | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size); |
405 | 83469015 | bellard | |
406 | 83469015 | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
407 | 83469015 | bellard | if (serial_hds[i]) {
|
408 | d537cf6c | pbrook | serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]); |
409 | 83469015 | bellard | } |
410 | 83469015 | bellard | } |
411 | 83469015 | bellard | |
412 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
413 | 83469015 | bellard | if (parallel_hds[i]) {
|
414 | d537cf6c | pbrook | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]); |
415 | 83469015 | bellard | } |
416 | 83469015 | bellard | } |
417 | 83469015 | bellard | |
418 | 83469015 | bellard | for(i = 0; i < nb_nics; i++) { |
419 | a41b2ff2 | pbrook | if (!nd_table[i].model)
|
420 | a41b2ff2 | pbrook | nd_table[i].model = "ne2k_pci";
|
421 | f930d07e | blueswir1 | pci_nic_init(pci_bus, &nd_table[i], -1);
|
422 | 83469015 | bellard | } |
423 | 83469015 | bellard | |
424 | f19e918d | blueswir1 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
425 | f19e918d | blueswir1 | // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
|
426 | f19e918d | blueswir1 | pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
|
427 | d537cf6c | pbrook | /* FIXME: wire up interrupts. */
|
428 | d537cf6c | pbrook | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
429 | d537cf6c | pbrook | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table); |
430 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
431 | 6ac0e82d | balrog | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device[0], |
432 | 83469015 | bellard | KERNEL_LOAD_ADDR, kernel_size, |
433 | 83469015 | bellard | kernel_cmdline, |
434 | 83469015 | bellard | INITRD_LOAD_ADDR, initrd_size, |
435 | 83469015 | bellard | /* XXX: need an option to load a NVRAM image */
|
436 | 83469015 | bellard | 0,
|
437 | 83469015 | bellard | graphic_width, graphic_height, graphic_depth); |
438 | 83469015 | bellard | |
439 | 3475187d | bellard | } |
440 | 3475187d | bellard | |
441 | 3475187d | bellard | QEMUMachine sun4u_machine = { |
442 | 3475187d | bellard | "sun4u",
|
443 | 3475187d | bellard | "Sun4u platform",
|
444 | 3475187d | bellard | sun4u_init, |
445 | 3475187d | bellard | }; |