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/*
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 * QEMU Sun4u System Emulator
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 *
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 * Copyright (c) 2005 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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#include "m48t59.h"
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#define KERNEL_LOAD_ADDR     0x00404000
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#define CMDLINE_ADDR         0x003ff000
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#define INITRD_LOAD_ADDR     0x00300000
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#define PROM_SIZE_MAX        (512 * 1024)
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#define PROM_ADDR            0x1fff0000000ULL
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#define PROM_VADDR           0x000ffd00000ULL
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#define APB_SPECIAL_BASE     0x1fe00000000ULL
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#define APB_MEM_BASE         0x1ff00000000ULL
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#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
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#define PROM_FILENAME        "openbios-sparc64"
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#define NVRAM_SIZE           0x2000
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/* TSC handling */
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uint64_t cpu_get_tsc()
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{
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    return qemu_get_clock(vm_clock);
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}
45

    
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int DMA_get_channel_mode (int nchan)
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{
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    return 0;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int size)
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{
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    return 0;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int size)
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{
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    return 0;
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}
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_run (void) {}
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void DMA_init (int high_page_enable) {}
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void DMA_register_channel (int nchan,
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                           DMA_transfer_handler transfer_handler,
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                           void *opaque)
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{
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}
68

    
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/* NVRAM helpers */
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static void nvram_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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{
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    m48t59_write(nvram, addr, value);
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}
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static uint8_t nvram_get_byte (m48t59_t *nvram, uint32_t addr)
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{
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    return m48t59_read(nvram, addr);
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}
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static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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    m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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    m48t59_write(nvram, addr++, value & 0xff);
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}
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static uint16_t nvram_get_word (m48t59_t *nvram, uint32_t addr)
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{
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    uint16_t tmp;
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    tmp = m48t59_read(nvram, addr) << 8;
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    tmp |= m48t59_read(nvram, addr + 1);
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    return tmp;
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}
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static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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    m48t59_write(nvram, addr++, value >> 24);
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    m48t59_write(nvram, addr++, (value >> 16) & 0xff);
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    m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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    m48t59_write(nvram, addr++, value & 0xff);
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}
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static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
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                       const unsigned char *str, uint32_t max)
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{
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    unsigned int i;
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    for (i = 0; i < max && str[i] != '\0'; i++) {
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        m48t59_write(nvram, addr + i, str[i]);
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    }
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    m48t59_write(nvram, addr + max - 1, '\0');
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}
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static uint16_t nvram_crc_update (uint16_t prev, uint16_t value)
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{
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    uint16_t tmp;
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    uint16_t pd, pd1, pd2;
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    tmp = prev >> 8;
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    pd = prev ^ value;
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    pd1 = pd & 0x000F;
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    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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    tmp ^= (pd1 << 3) | (pd1 << 8);
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    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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    return tmp;
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}
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static uint16_t nvram_compute_crc (m48t59_t *nvram, uint32_t start,
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                                   uint32_t count)
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{
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    uint32_t i;
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    uint16_t crc = 0xFFFF;
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    int odd;
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    odd = count & 1;
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    count &= ~1;
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    for (i = 0; i != count; i++) {
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        crc = nvram_crc_update(crc, nvram_get_word(nvram, start + i));
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    }
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    if (odd) {
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        crc = nvram_crc_update(crc, nvram_get_byte(nvram, start + i) << 8);
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    }
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    return crc;
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}
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static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
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                                const unsigned char *str)
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{
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    uint32_t len;
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    len = strlen(str) + 1;
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    nvram_set_string(nvram, addr, str, len);
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    return addr + len;
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}
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static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
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                                    uint32_t end)
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{
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    unsigned int i, sum;
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    // Length divided by 16
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    m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
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    m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
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    // Checksum
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    sum = m48t59_read(nvram, start);
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    for (i = 0; i < 14; i++) {
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        sum += m48t59_read(nvram, start + 2 + i);
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        sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
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    }
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    m48t59_write(nvram, start + 1, sum & 0xff);
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}
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extern int nographic;
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int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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                          const unsigned char *arch,
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                          uint32_t RAM_size, int boot_device,
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                          uint32_t kernel_image, uint32_t kernel_size,
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                          const char *cmdline,
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                          uint32_t initrd_image, uint32_t initrd_size,
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                          uint32_t NVRAM_image,
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                          int width, int height, int depth)
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{
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    uint16_t crc;
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    unsigned int i;
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    uint32_t start, end;
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    /* Set parameters for Open Hack'Ware BIOS */
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    nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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    nvram_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
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    nvram_set_word(nvram,   0x14, NVRAM_size);
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    nvram_set_string(nvram, 0x20, arch, 16);
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    nvram_set_byte(nvram,   0x2f, nographic & 0xff);
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    nvram_set_lword(nvram,  0x30, RAM_size);
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    nvram_set_byte(nvram,   0x34, boot_device);
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    nvram_set_lword(nvram,  0x38, kernel_image);
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    nvram_set_lword(nvram,  0x3C, kernel_size);
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    if (cmdline) {
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        /* XXX: put the cmdline in NVRAM too ? */
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        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
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        nvram_set_lword(nvram,  0x40, CMDLINE_ADDR);
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        nvram_set_lword(nvram,  0x44, strlen(cmdline));
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    } else {
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        nvram_set_lword(nvram,  0x40, 0);
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        nvram_set_lword(nvram,  0x44, 0);
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    }
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    nvram_set_lword(nvram,  0x48, initrd_image);
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    nvram_set_lword(nvram,  0x4C, initrd_size);
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    nvram_set_lword(nvram,  0x50, NVRAM_image);
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    nvram_set_word(nvram,   0x54, width);
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    nvram_set_word(nvram,   0x56, height);
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    nvram_set_word(nvram,   0x58, depth);
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    crc = nvram_compute_crc(nvram, 0x00, 0xF8);
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    nvram_set_word(nvram,  0xFC, crc);
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    // OpenBIOS nvram variables
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    // Variable partition
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    start = 256;
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    m48t59_write(nvram, start, 0x70);
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    nvram_set_string(nvram, start + 4, "system", 12);
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    end = start + 16;
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    for (i = 0; i < nb_prom_envs; i++)
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        end = nvram_set_var(nvram, end, prom_envs[i]);
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    m48t59_write(nvram, end++ , 0);
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    end = start + ((end - start + 15) & ~15);
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    nvram_finish_partition(nvram, start, end);
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    // free partition
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    start = end;
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    m48t59_write(nvram, start, 0x7f);
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    nvram_set_string(nvram, start + 4, "free", 12);
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240
    end = 0x1fd0;
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    nvram_finish_partition(nvram, start, end);
242

    
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    return 0;
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}
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void pic_info()
247
{
248
}
249

    
250
void irq_info()
251
{
252
}
253

    
254
void qemu_system_powerdown(void)
255
{
256
}
257

    
258
static void main_cpu_reset(void *opaque)
259
{
260
    CPUState *env = opaque;
261

    
262
    cpu_reset(env);
263
    ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
264
    ptimer_run(env->tick, 0);
265
    ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
266
    ptimer_run(env->stick, 0);
267
    ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
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    ptimer_run(env->hstick, 0);
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}
270

    
271
void tick_irq(void *opaque)
272
{
273
    CPUState *env = opaque;
274

    
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    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
277

    
278
void stick_irq(void *opaque)
279
{
280
    CPUState *env = opaque;
281

    
282
    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
283
}
284

    
285
void hstick_irq(void *opaque)
286
{
287
    CPUState *env = opaque;
288

    
289
    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
290
}
291

    
292
static void dummy_cpu_set_irq(void *opaque, int irq, int level)
293
{
294
}
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296
static const int ide_iobase[2] = { 0x1f0, 0x170 };
297
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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300
static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
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static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
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303
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
304
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
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static fdctrl_t *floppy_controller;
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308
/* Sun4u hardware initialisation */
309
static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device,
310
             DisplayState *ds, const char **fd_filename, int snapshot,
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             const char *kernel_filename, const char *kernel_cmdline,
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             const char *initrd_filename, const char *cpu_model)
313
{
314
    CPUState *env;
315
    char buf[1024];
316
    m48t59_t *nvram;
317
    int ret, linux_boot;
318
    unsigned int i;
319
    long prom_offset, initrd_size, kernel_size;
320
    PCIBus *pci_bus;
321
    QEMUBH *bh;
322
    qemu_irq *irq;
323

    
324
    linux_boot = (kernel_filename != NULL);
325

    
326
    /* init CPUs */
327
    if (cpu_model == NULL)
328
        cpu_model = "TI UltraSparc II";
329
    env = cpu_init(cpu_model);
330
    if (!env) {
331
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
332
        exit(1);
333
    }
334
    bh = qemu_bh_new(tick_irq, env);
335
    env->tick = ptimer_init(bh);
336
    ptimer_set_period(env->tick, 1ULL);
337

    
338
    bh = qemu_bh_new(stick_irq, env);
339
    env->stick = ptimer_init(bh);
340
    ptimer_set_period(env->stick, 1ULL);
341

    
342
    bh = qemu_bh_new(hstick_irq, env);
343
    env->hstick = ptimer_init(bh);
344
    ptimer_set_period(env->hstick, 1ULL);
345
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
346
    qemu_register_reset(main_cpu_reset, env);
347
    main_cpu_reset(env);
348

    
349
    /* allocate RAM */
350
    cpu_register_physical_memory(0, ram_size, 0);
351

    
352
    prom_offset = ram_size + vga_ram_size;
353
    cpu_register_physical_memory(PROM_ADDR,
354
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
355
                                 prom_offset | IO_MEM_ROM);
356

    
357
    if (bios_name == NULL)
358
        bios_name = PROM_FILENAME;
359
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
360
    ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
361
    if (ret < 0) {
362
        fprintf(stderr, "qemu: could not load prom '%s'\n",
363
                buf);
364
        exit(1);
365
    }
366

    
367
    kernel_size = 0;
368
    initrd_size = 0;
369
    if (linux_boot) {
370
        /* XXX: put correct offset */
371
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
372
        if (kernel_size < 0)
373
            kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
374
        if (kernel_size < 0)
375
            kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
376
        if (kernel_size < 0) {
377
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
378
                    kernel_filename);
379
            exit(1);
380
        }
381

    
382
        /* load initrd */
383
        if (initrd_filename) {
384
            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
385
            if (initrd_size < 0) {
386
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
387
                        initrd_filename);
388
                exit(1);
389
            }
390
        }
391
        if (initrd_size > 0) {
392
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
393
                if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
394
                    == 0x48647253) { // HdrS
395
                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
396
                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
397
                    break;
398
                }
399
            }
400
        }
401
    }
402
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
403
    isa_mem_base = VGA_BASE;
404
    pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
405

    
406
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
407
        if (serial_hds[i]) {
408
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
409
        }
410
    }
411

    
412
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
413
        if (parallel_hds[i]) {
414
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
415
        }
416
    }
417

    
418
    for(i = 0; i < nb_nics; i++) {
419
        if (!nd_table[i].model)
420
            nd_table[i].model = "ne2k_pci";
421
        pci_nic_init(pci_bus, &nd_table[i], -1);
422
    }
423

    
424
    irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
425
    // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
426
    pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
427
    /* FIXME: wire up interrupts.  */
428
    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
429
    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
430
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
431
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device[0],
432
                         KERNEL_LOAD_ADDR, kernel_size,
433
                         kernel_cmdline,
434
                         INITRD_LOAD_ADDR, initrd_size,
435
                         /* XXX: need an option to load a NVRAM image */
436
                         0,
437
                         graphic_width, graphic_height, graphic_depth);
438

    
439
}
440

    
441
QEMUMachine sun4u_machine = {
442
    "sun4u",
443
    "Sun4u platform",
444
    sun4u_init,
445
};