Revision 100d9891 hw/mc146818rtc.c
| b/hw/mc146818rtc.c | ||
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#define REG_A_UIP 0x80 |
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#define REG_B_SET 0x80 |
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#define REG_B_PIE 0x40 |
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#define REG_B_AIE 0x20 |
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#define REG_B_UIE 0x10 |
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#define REG_B_DM 0x04 |
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#define REG_B_SET 0x80 |
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#define REG_B_PIE 0x40 |
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#define REG_B_AIE 0x20 |
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#define REG_B_UIE 0x10 |
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#define REG_B_SQWE 0x08 |
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#define REG_B_DM 0x04 |
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struct RTCState {
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uint8_t cmos_data[128]; |
| ... | ... | |
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struct tm current_tm; |
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int base_year; |
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qemu_irq irq; |
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qemu_irq sqw_irq; |
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int it_shift; |
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/* periodic timer */ |
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QEMUTimer *periodic_timer; |
| ... | ... | |
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{
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int period_code, period; |
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int64_t cur_clock, next_irq_clock; |
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int enable_pie; |
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period_code = s->cmos_data[RTC_REG_A] & 0x0f; |
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#if defined TARGET_I386 || defined TARGET_X86_64 |
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/* disable periodic timer if hpet is in legacy mode, since interrupts are |
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* disabled anyway. |
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*/ |
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if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) {
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enable_pie = hpet_in_legacy_mode();
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#else |
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if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
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enable_pie = 1;
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#endif |
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if (period_code != 0 |
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&& (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2) |
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period_code += 7; |
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/* period in 32 Khz cycles */ |
| ... | ... | |
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return; |
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} |
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#endif |
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s->cmos_data[RTC_REG_C] |= 0xc0; |
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rtc_irq_raise(s->irq); |
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= 0xc0; |
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rtc_irq_raise(s->irq); |
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} |
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts! |
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Must be seen as a pulse. */ |
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qemu_irq_raise(s->sqw_irq); |
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} |
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} |
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
| ... | ... | |
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} |
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#endif |
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RTCState *rtc_init(int base, qemu_irq irq, int base_year)
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RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year)
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{
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RTCState *s; |
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s = qemu_mallocz(sizeof(RTCState)); |
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s->irq = irq; |
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s->sqw_irq = sqw_irq; |
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s->cmos_data[RTC_REG_A] = 0x26; |
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s->cmos_data[RTC_REG_B] = 0x02; |
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s->cmos_data[RTC_REG_C] = 0x00; |
| ... | ... | |
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return s; |
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} |
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RTCState *rtc_init(int base, qemu_irq irq, int base_year) |
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{
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return rtc_init_sqw(base, irq, NULL, base_year); |
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} |
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/* Memory mapped interface */ |
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static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
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{
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