pci: move ids of config space into PCIDeviceInfo
vender id/device id... in configuration space are read-only registerswhich are commonly defined for all pci devices.So move those initialization into common place.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>...
CPUPhysMemoryClient: batch addresses in catchup
When a phys memory client registers and we play catchup by walkingthe page tables, we can make a huge improvement in the number oftimes the set_memory callback is called by batching contiguouspages together. With a 4G guest, this reduces the number of callbacks...
ich/ahci: fix uninitialized memory use
The commit 667bb59d2358daeef179583c944becba3f1f9680uses d->ahci.mem before it is initialized byahci_init(). Fix this by calling ahci_init() first thingso that it's safe to use all fields in the ahci state struct....
Merge remote branch 'origin/master' into pci
Conflicts: exec.c
CPUPhysMemoryClient: Pass guest physical address not region offset
When we're trying to get a newly registered phys memory client updatedwith the current page mappings, we end up passing the region offset(a ram_addr_t) as the start address rather than the actual guest...
CPUPhysMemoryClient: Fix typo in phys memory client registration
When we register a physical memory client, we try to walk the pagetables, calling the set_memory hook for every entry. Effectivelyplaying catchup for the client for everything already registered....
pci: Add class 0x403 as 'audio controller'
Used by HD audio controllers like our intel-hda.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
MSI: Robust resource release
msi_init may fail, so we need to check on uninit if the cap wasactually installed. This also avoids that the users need to check.
eepro100: Support byte read access to general control register
The general control register is a byte register.Add support for byte reads.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
eepro100: Support 32 bit read/write access to flash register
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