Revision 129d8aa5
| b/linux-user/main.c | ||
|---|---|---|
| 2524 | 2524 |
env->lock_addr = -1; |
| 2525 | 2525 |
info.si_signo = TARGET_SIGSEGV; |
| 2526 | 2526 |
info.si_errno = 0; |
| 2527 |
info.si_code = (page_get_flags(env->ipr[IPR_EXC_ADDR]) & PAGE_VALID
|
|
| 2527 |
info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
|
|
| 2528 | 2528 |
? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); |
| 2529 |
info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR];
|
|
| 2529 |
info._sifields._sigfault._addr = env->trap_arg0;
|
|
| 2530 | 2530 |
queue_signal(env, info.si_signo, &info); |
| 2531 | 2531 |
break; |
| 2532 | 2532 |
case EXCP_DTB_MISS_PAL: |
| ... | ... | |
| 2550 | 2550 |
info.si_signo = TARGET_SIGBUS; |
| 2551 | 2551 |
info.si_errno = 0; |
| 2552 | 2552 |
info.si_code = TARGET_BUS_ADRALN; |
| 2553 |
info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR];
|
|
| 2553 |
info._sifields._sigfault._addr = env->trap_arg0;
|
|
| 2554 | 2554 |
queue_signal(env, info.si_signo, &info); |
| 2555 | 2555 |
break; |
| 2556 | 2556 |
case EXCP_OPCDEC: |
| b/target-alpha/cpu.h | ||
|---|---|---|
| 192 | 192 |
|
| 193 | 193 |
#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) |
| 194 | 194 |
|
| 195 |
/* Internal processor registers */ |
|
| 196 |
/* XXX: TOFIX: most of those registers are implementation dependant */ |
|
| 197 |
enum {
|
|
| 198 |
#if defined(CONFIG_USER_ONLY) |
|
| 199 |
IPR_EXC_ADDR, |
|
| 200 |
IPR_EXC_SUM, |
|
| 201 |
IPR_EXC_MASK, |
|
| 202 |
#else |
|
| 203 |
/* Ebox IPRs */ |
|
| 204 |
IPR_CC = 0xC0, /* 21264 */ |
|
| 205 |
IPR_CC_CTL = 0xC1, /* 21264 */ |
|
| 206 |
#define IPR_CC_CTL_ENA_SHIFT 32 |
|
| 207 |
#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL |
|
| 208 |
IPR_VA = 0xC2, /* 21264 */ |
|
| 209 |
IPR_VA_CTL = 0xC4, /* 21264 */ |
|
| 210 |
#define IPR_VA_CTL_VA_48_SHIFT 1 |
|
| 211 |
#define IPR_VA_CTL_VPTB_SHIFT 30 |
|
| 212 |
IPR_VA_FORM = 0xC3, /* 21264 */ |
|
| 213 |
/* Ibox IPRs */ |
|
| 214 |
IPR_ITB_TAG = 0x00, /* 21264 */ |
|
| 215 |
IPR_ITB_PTE = 0x01, /* 21264 */ |
|
| 216 |
IPR_ITB_IAP = 0x02, |
|
| 217 |
IPR_ITB_IA = 0x03, /* 21264 */ |
|
| 218 |
IPR_ITB_IS = 0x04, /* 21264 */ |
|
| 219 |
IPR_PMPC = 0x05, |
|
| 220 |
IPR_EXC_ADDR = 0x06, /* 21264 */ |
|
| 221 |
IPR_IVA_FORM = 0x07, /* 21264 */ |
|
| 222 |
IPR_CM = 0x09, /* 21264 */ |
|
| 223 |
#define IPR_CM_SHIFT 3 |
|
| 224 |
#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */ |
|
| 225 |
IPR_IER = 0x0A, /* 21264 */ |
|
| 226 |
#define IPR_IER_MASK 0x0000007fffffe000ULL |
|
| 227 |
IPR_IER_CM = 0x0B, /* 21264: = CM | IER */ |
|
| 228 |
IPR_SIRR = 0x0C, /* 21264 */ |
|
| 229 |
#define IPR_SIRR_SHIFT 14 |
|
| 230 |
#define IPR_SIRR_MASK 0x7fff |
|
| 231 |
IPR_ISUM = 0x0D, /* 21264 */ |
|
| 232 |
IPR_HW_INT_CLR = 0x0E, /* 21264 */ |
|
| 233 |
IPR_EXC_SUM = 0x0F, |
|
| 234 |
IPR_PAL_BASE = 0x10, |
|
| 235 |
IPR_I_CTL = 0x11, |
|
| 236 |
#define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */ |
|
| 237 |
#define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */ |
|
| 238 |
#define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */ |
|
| 239 |
#define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */ |
|
| 240 |
#define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */ |
|
| 241 |
#define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */ |
|
| 242 |
#define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */ |
|
| 243 |
#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */ |
|
| 244 |
IPR_I_STAT = 0x16, /* 21264 */ |
|
| 245 |
IPR_IC_FLUSH = 0x13, /* 21264 */ |
|
| 246 |
IPR_IC_FLUSH_ASM = 0x12, /* 21264 */ |
|
| 247 |
IPR_CLR_MAP = 0x15, |
|
| 248 |
IPR_SLEEP = 0x17, |
|
| 249 |
IPR_PCTX = 0x40, |
|
| 250 |
IPR_PCTX_ASN = 0x01, /* field */ |
|
| 251 |
#define IPR_PCTX_ASN_SHIFT 39 |
|
| 252 |
IPR_PCTX_ASTER = 0x02, /* field */ |
|
| 253 |
#define IPR_PCTX_ASTER_SHIFT 5 |
|
| 254 |
IPR_PCTX_ASTRR = 0x04, /* field */ |
|
| 255 |
#define IPR_PCTX_ASTRR_SHIFT 9 |
|
| 256 |
IPR_PCTX_PPCE = 0x08, /* field */ |
|
| 257 |
#define IPR_PCTX_PPCE_SHIFT 1 |
|
| 258 |
IPR_PCTX_FPE = 0x10, /* field */ |
|
| 259 |
#define IPR_PCTX_FPE_SHIFT 2 |
|
| 260 |
IPR_PCTX_ALL = 0x5f, /* all fields */ |
|
| 261 |
IPR_PCTR_CTL = 0x14, /* 21264 */ |
|
| 262 |
/* Mbox IPRs */ |
|
| 263 |
IPR_DTB_TAG0 = 0x20, /* 21264 */ |
|
| 264 |
IPR_DTB_TAG1 = 0xA0, /* 21264 */ |
|
| 265 |
IPR_DTB_PTE0 = 0x21, /* 21264 */ |
|
| 266 |
IPR_DTB_PTE1 = 0xA1, /* 21264 */ |
|
| 267 |
IPR_DTB_ALTMODE = 0xA6, |
|
| 268 |
IPR_DTB_ALTMODE0 = 0x26, /* 21264 */ |
|
| 269 |
#define IPR_DTB_ALTMODE_MASK 3 |
|
| 270 |
IPR_DTB_IAP = 0xA2, |
|
| 271 |
IPR_DTB_IA = 0xA3, /* 21264 */ |
|
| 272 |
IPR_DTB_IS0 = 0x24, |
|
| 273 |
IPR_DTB_IS1 = 0xA4, |
|
| 274 |
IPR_DTB_ASN0 = 0x25, /* 21264 */ |
|
| 275 |
IPR_DTB_ASN1 = 0xA5, /* 21264 */ |
|
| 276 |
#define IPR_DTB_ASN_SHIFT 56 |
|
| 277 |
IPR_MM_STAT = 0x27, /* 21264 */ |
|
| 278 |
IPR_M_CTL = 0x28, /* 21264 */ |
|
| 279 |
#define IPR_M_CTL_SPE_SHIFT 1 |
|
| 280 |
#define IPR_M_CTL_SPE_MASK 7 |
|
| 281 |
IPR_DC_CTL = 0x29, /* 21264 */ |
|
| 282 |
IPR_DC_STAT = 0x2A, /* 21264 */ |
|
| 283 |
/* Cbox IPRs */ |
|
| 284 |
IPR_C_DATA = 0x2B, |
|
| 285 |
IPR_C_SHIFT = 0x2C, |
|
| 286 |
|
|
| 287 |
IPR_ASN, |
|
| 288 |
IPR_ASTEN, |
|
| 289 |
IPR_ASTSR, |
|
| 290 |
IPR_DATFX, |
|
| 291 |
IPR_ESP, |
|
| 292 |
IPR_FEN, |
|
| 293 |
IPR_IPIR, |
|
| 294 |
IPR_IPL, |
|
| 295 |
IPR_KSP, |
|
| 296 |
IPR_MCES, |
|
| 297 |
IPR_PERFMON, |
|
| 298 |
IPR_PCBB, |
|
| 299 |
IPR_PRBR, |
|
| 300 |
IPR_PTBR, |
|
| 301 |
IPR_SCBB, |
|
| 302 |
IPR_SISR, |
|
| 303 |
IPR_SSP, |
|
| 304 |
IPR_SYSPTBR, |
|
| 305 |
IPR_TBCHK, |
|
| 306 |
IPR_TBIA, |
|
| 307 |
IPR_TBIAP, |
|
| 308 |
IPR_TBIS, |
|
| 309 |
IPR_TBISD, |
|
| 310 |
IPR_TBISI, |
|
| 311 |
IPR_USP, |
|
| 312 |
IPR_VIRBND, |
|
| 313 |
IPR_VPTB, |
|
| 314 |
IPR_WHAMI, |
|
| 315 |
IPR_ALT_MODE, |
|
| 316 |
#endif |
|
| 317 |
IPR_LAST, |
|
| 318 |
}; |
|
| 319 |
|
|
| 320 | 195 |
/* MMU modes definitions */ |
| 321 | 196 |
|
| 322 | 197 |
/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user. |
| ... | ... | |
| 350 | 225 |
uint64_t ir[31]; |
| 351 | 226 |
float64 fir[31]; |
| 352 | 227 |
uint64_t pc; |
| 353 |
uint64_t ipr[IPR_LAST]; |
|
| 354 |
uint64_t ps; |
|
| 355 | 228 |
uint64_t unique; |
| 356 | 229 |
uint64_t lock_addr; |
| 357 | 230 |
uint64_t lock_st_addr; |
| ... | ... | |
| 366 | 239 |
uint8_t fpcr_dnod; |
| 367 | 240 |
uint8_t fpcr_undz; |
| 368 | 241 |
|
| 369 |
/* Used for HW_LD / HW_ST */
|
|
| 370 |
uint8_t saved_mode;
|
|
| 371 |
/* For RC and RS */
|
|
| 242 |
/* The Internal Processor Registers. Some of these we assume always
|
|
| 243 |
exist for use in user-mode. */
|
|
| 244 |
uint8_t ps;
|
|
| 372 | 245 |
uint8_t intr_flag; |
| 246 |
uint8_t pal_mode; |
|
| 247 |
|
|
| 248 |
/* These pass data from the exception logic in the translator and |
|
| 249 |
helpers to the OS entry point. This is used for both system |
|
| 250 |
emulation and user-mode. */ |
|
| 251 |
uint64_t trap_arg0; |
|
| 252 |
uint64_t trap_arg1; |
|
| 253 |
uint64_t trap_arg2; |
|
| 373 | 254 |
|
| 374 | 255 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| 375 | 256 |
/* temporary fixed-point registers |
| ... | ... | |
| 381 | 262 |
/* Those resources are used only in Qemu core */ |
| 382 | 263 |
CPU_COMMON |
| 383 | 264 |
|
| 384 |
uint32_t hflags; |
|
| 385 |
|
|
| 386 | 265 |
int error_code; |
| 387 | 266 |
|
| 388 | 267 |
uint32_t features; |
| ... | ... | |
| 492 | 371 |
|
| 493 | 372 |
uint64_t cpu_alpha_load_fpcr (CPUState *env); |
| 494 | 373 |
void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); |
| 495 |
int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); |
|
| 496 |
int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); |
|
| 497 | 374 |
|
| 498 | 375 |
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
| 499 | 376 |
target_ulong *cs_base, int *flags) |
| b/target-alpha/helper.c | ||
|---|---|---|
| 168 | 168 |
env->exception_index = EXCP_ITB_MISS; |
| 169 | 169 |
else |
| 170 | 170 |
env->exception_index = EXCP_DFAULT; |
| 171 |
env->ipr[IPR_EXC_ADDR] = address; |
|
| 172 |
|
|
| 171 |
env->trap_arg0 = address; |
|
| 173 | 172 |
return 1; |
| 174 | 173 |
} |
| 175 | 174 |
|
| ... | ... | |
| 188 | 187 |
int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 189 | 188 |
int mmu_idx, int is_softmmu) |
| 190 | 189 |
{
|
| 191 |
uint32_t opc; |
|
| 192 |
|
|
| 193 |
if (rw == 2) {
|
|
| 194 |
/* Instruction translation buffer miss */ |
|
| 195 |
env->exception_index = EXCP_ITB_MISS; |
|
| 196 |
} else {
|
|
| 197 |
if (env->ipr[IPR_EXC_ADDR] & 1) |
|
| 198 |
env->exception_index = EXCP_DTB_MISS_PAL; |
|
| 199 |
else |
|
| 200 |
env->exception_index = EXCP_DTB_MISS_NATIVE; |
|
| 201 |
opc = (ldl_code(env->pc) >> 21) << 4; |
|
| 202 |
if (rw) {
|
|
| 203 |
opc |= 0x9; |
|
| 204 |
} else {
|
|
| 205 |
opc |= 0x4; |
|
| 206 |
} |
|
| 207 |
env->ipr[IPR_MM_STAT] = opc; |
|
| 208 |
} |
|
| 209 |
|
|
| 210 |
return 1; |
|
| 211 |
} |
|
| 212 |
|
|
| 213 |
int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp) |
|
| 214 |
{
|
|
| 215 |
uint64_t hwpcb; |
|
| 216 |
int ret = 0; |
|
| 217 |
|
|
| 218 |
hwpcb = env->ipr[IPR_PCBB]; |
|
| 219 |
switch (iprn) {
|
|
| 220 |
case IPR_ASN: |
|
| 221 |
if (env->features & FEATURE_ASN) |
|
| 222 |
*valp = env->ipr[IPR_ASN]; |
|
| 223 |
else |
|
| 224 |
*valp = 0; |
|
| 225 |
break; |
|
| 226 |
case IPR_ASTEN: |
|
| 227 |
*valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60; |
|
| 228 |
break; |
|
| 229 |
case IPR_ASTSR: |
|
| 230 |
*valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60; |
|
| 231 |
break; |
|
| 232 |
case IPR_DATFX: |
|
| 233 |
/* Write only */ |
|
| 234 |
ret = -1; |
|
| 235 |
break; |
|
| 236 |
case IPR_ESP: |
|
| 237 |
if (env->features & FEATURE_SPS) |
|
| 238 |
*valp = env->ipr[IPR_ESP]; |
|
| 239 |
else |
|
| 240 |
*valp = ldq_raw(hwpcb + 8); |
|
| 241 |
break; |
|
| 242 |
case IPR_FEN: |
|
| 243 |
*valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63; |
|
| 244 |
break; |
|
| 245 |
case IPR_IPIR: |
|
| 246 |
/* Write-only */ |
|
| 247 |
ret = -1; |
|
| 248 |
break; |
|
| 249 |
case IPR_IPL: |
|
| 250 |
*valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59; |
|
| 251 |
break; |
|
| 252 |
case IPR_KSP: |
|
| 253 |
if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
|
|
| 254 |
ret = -1; |
|
| 255 |
} else {
|
|
| 256 |
if (env->features & FEATURE_SPS) |
|
| 257 |
*valp = env->ipr[IPR_KSP]; |
|
| 258 |
else |
|
| 259 |
*valp = ldq_raw(hwpcb + 0); |
|
| 260 |
} |
|
| 261 |
break; |
|
| 262 |
case IPR_MCES: |
|
| 263 |
*valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59; |
|
| 264 |
break; |
|
| 265 |
case IPR_PERFMON: |
|
| 266 |
/* Implementation specific */ |
|
| 267 |
*valp = 0; |
|
| 268 |
break; |
|
| 269 |
case IPR_PCBB: |
|
| 270 |
*valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16; |
|
| 271 |
break; |
|
| 272 |
case IPR_PRBR: |
|
| 273 |
*valp = env->ipr[IPR_PRBR]; |
|
| 274 |
break; |
|
| 275 |
case IPR_PTBR: |
|
| 276 |
*valp = env->ipr[IPR_PTBR]; |
|
| 277 |
break; |
|
| 278 |
case IPR_SCBB: |
|
| 279 |
*valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]); |
|
| 280 |
break; |
|
| 281 |
case IPR_SIRR: |
|
| 282 |
/* Write-only */ |
|
| 283 |
ret = -1; |
|
| 284 |
break; |
|
| 285 |
case IPR_SISR: |
|
| 286 |
*valp = (int64_t)((int16_t)env->ipr[IPR_SISR]); |
|
| 287 |
case IPR_SSP: |
|
| 288 |
if (env->features & FEATURE_SPS) |
|
| 289 |
*valp = env->ipr[IPR_SSP]; |
|
| 290 |
else |
|
| 291 |
*valp = ldq_raw(hwpcb + 16); |
|
| 292 |
break; |
|
| 293 |
case IPR_SYSPTBR: |
|
| 294 |
if (env->features & FEATURE_VIRBND) |
|
| 295 |
*valp = env->ipr[IPR_SYSPTBR]; |
|
| 296 |
else |
|
| 297 |
ret = -1; |
|
| 298 |
break; |
|
| 299 |
case IPR_TBCHK: |
|
| 300 |
if ((env->features & FEATURE_TBCHK)) {
|
|
| 301 |
/* XXX: TODO */ |
|
| 302 |
*valp = 0; |
|
| 303 |
ret = -1; |
|
| 304 |
} else {
|
|
| 305 |
ret = -1; |
|
| 306 |
} |
|
| 307 |
break; |
|
| 308 |
case IPR_TBIA: |
|
| 309 |
/* Write-only */ |
|
| 310 |
ret = -1; |
|
| 311 |
break; |
|
| 312 |
case IPR_TBIAP: |
|
| 313 |
/* Write-only */ |
|
| 314 |
ret = -1; |
|
| 315 |
break; |
|
| 316 |
case IPR_TBIS: |
|
| 317 |
/* Write-only */ |
|
| 318 |
ret = -1; |
|
| 319 |
break; |
|
| 320 |
case IPR_TBISD: |
|
| 321 |
/* Write-only */ |
|
| 322 |
ret = -1; |
|
| 323 |
break; |
|
| 324 |
case IPR_TBISI: |
|
| 325 |
/* Write-only */ |
|
| 326 |
ret = -1; |
|
| 327 |
break; |
|
| 328 |
case IPR_USP: |
|
| 329 |
if (env->features & FEATURE_SPS) |
|
| 330 |
*valp = env->ipr[IPR_USP]; |
|
| 331 |
else |
|
| 332 |
*valp = ldq_raw(hwpcb + 24); |
|
| 333 |
break; |
|
| 334 |
case IPR_VIRBND: |
|
| 335 |
if (env->features & FEATURE_VIRBND) |
|
| 336 |
*valp = env->ipr[IPR_VIRBND]; |
|
| 337 |
else |
|
| 338 |
ret = -1; |
|
| 339 |
break; |
|
| 340 |
case IPR_VPTB: |
|
| 341 |
*valp = env->ipr[IPR_VPTB]; |
|
| 342 |
break; |
|
| 343 |
case IPR_WHAMI: |
|
| 344 |
*valp = env->ipr[IPR_WHAMI]; |
|
| 345 |
break; |
|
| 346 |
default: |
|
| 347 |
/* Invalid */ |
|
| 348 |
ret = -1; |
|
| 349 |
break; |
|
| 350 |
} |
|
| 351 |
|
|
| 352 |
return ret; |
|
| 353 |
} |
|
| 354 |
|
|
| 355 |
int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp) |
|
| 356 |
{
|
|
| 357 |
uint64_t hwpcb, tmp64; |
|
| 358 |
uint8_t tmp8; |
|
| 359 |
int ret = 0; |
|
| 360 |
|
|
| 361 |
hwpcb = env->ipr[IPR_PCBB]; |
|
| 362 |
switch (iprn) {
|
|
| 363 |
case IPR_ASN: |
|
| 364 |
/* Read-only */ |
|
| 365 |
ret = -1; |
|
| 366 |
break; |
|
| 367 |
case IPR_ASTEN: |
|
| 368 |
tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4; |
|
| 369 |
*oldvalp = tmp8; |
|
| 370 |
tmp8 &= val & 0xF; |
|
| 371 |
tmp8 |= (val >> 4) & 0xF; |
|
| 372 |
env->ipr[IPR_ASTEN] &= ~0xF; |
|
| 373 |
env->ipr[IPR_ASTEN] |= tmp8; |
|
| 374 |
ret = 1; |
|
| 375 |
break; |
|
| 376 |
case IPR_ASTSR: |
|
| 377 |
tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4; |
|
| 378 |
*oldvalp = tmp8; |
|
| 379 |
tmp8 &= val & 0xF; |
|
| 380 |
tmp8 |= (val >> 4) & 0xF; |
|
| 381 |
env->ipr[IPR_ASTSR] &= ~0xF; |
|
| 382 |
env->ipr[IPR_ASTSR] |= tmp8; |
|
| 383 |
ret = 1; |
|
| 384 |
case IPR_DATFX: |
|
| 385 |
env->ipr[IPR_DATFX] &= ~0x1; |
|
| 386 |
env->ipr[IPR_DATFX] |= val & 1; |
|
| 387 |
tmp64 = ldq_raw(hwpcb + 56); |
|
| 388 |
tmp64 &= ~0x8000000000000000ULL; |
|
| 389 |
tmp64 |= (val & 1) << 63; |
|
| 390 |
stq_raw(hwpcb + 56, tmp64); |
|
| 391 |
break; |
|
| 392 |
case IPR_ESP: |
|
| 393 |
if (env->features & FEATURE_SPS) |
|
| 394 |
env->ipr[IPR_ESP] = val; |
|
| 395 |
else |
|
| 396 |
stq_raw(hwpcb + 8, val); |
|
| 397 |
break; |
|
| 398 |
case IPR_FEN: |
|
| 399 |
env->ipr[IPR_FEN] = val & 1; |
|
| 400 |
tmp64 = ldq_raw(hwpcb + 56); |
|
| 401 |
tmp64 &= ~1; |
|
| 402 |
tmp64 |= val & 1; |
|
| 403 |
stq_raw(hwpcb + 56, tmp64); |
|
| 404 |
break; |
|
| 405 |
case IPR_IPIR: |
|
| 406 |
/* XXX: TODO: Send IRQ to CPU #ir[16] */ |
|
| 407 |
break; |
|
| 408 |
case IPR_IPL: |
|
| 409 |
*oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59; |
|
| 410 |
env->ipr[IPR_IPL] &= ~0x1F; |
|
| 411 |
env->ipr[IPR_IPL] |= val & 0x1F; |
|
| 412 |
/* XXX: may issue an interrupt or ASR _now_ */ |
|
| 413 |
ret = 1; |
|
| 414 |
break; |
|
| 415 |
case IPR_KSP: |
|
| 416 |
if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
|
|
| 417 |
ret = -1; |
|
| 418 |
} else {
|
|
| 419 |
if (env->features & FEATURE_SPS) |
|
| 420 |
env->ipr[IPR_KSP] = val; |
|
| 421 |
else |
|
| 422 |
stq_raw(hwpcb + 0, val); |
|
| 423 |
} |
|
| 424 |
break; |
|
| 425 |
case IPR_MCES: |
|
| 426 |
env->ipr[IPR_MCES] &= ~((val & 0x7) | 0x18); |
|
| 427 |
env->ipr[IPR_MCES] |= val & 0x18; |
|
| 428 |
break; |
|
| 429 |
case IPR_PERFMON: |
|
| 430 |
/* Implementation specific */ |
|
| 431 |
*oldvalp = 0; |
|
| 432 |
ret = 1; |
|
| 433 |
break; |
|
| 434 |
case IPR_PCBB: |
|
| 435 |
/* Read-only */ |
|
| 436 |
ret = -1; |
|
| 437 |
break; |
|
| 438 |
case IPR_PRBR: |
|
| 439 |
env->ipr[IPR_PRBR] = val; |
|
| 440 |
break; |
|
| 441 |
case IPR_PTBR: |
|
| 442 |
/* Read-only */ |
|
| 443 |
ret = -1; |
|
| 444 |
break; |
|
| 445 |
case IPR_SCBB: |
|
| 446 |
env->ipr[IPR_SCBB] = (uint32_t)val; |
|
| 447 |
break; |
|
| 448 |
case IPR_SIRR: |
|
| 449 |
if (val & 0xF) {
|
|
| 450 |
env->ipr[IPR_SISR] |= 1 << (val & 0xF); |
|
| 451 |
/* XXX: request a software interrupt _now_ */ |
|
| 452 |
} |
|
| 453 |
break; |
|
| 454 |
case IPR_SISR: |
|
| 455 |
/* Read-only */ |
|
| 456 |
ret = -1; |
|
| 457 |
break; |
|
| 458 |
case IPR_SSP: |
|
| 459 |
if (env->features & FEATURE_SPS) |
|
| 460 |
env->ipr[IPR_SSP] = val; |
|
| 461 |
else |
|
| 462 |
stq_raw(hwpcb + 16, val); |
|
| 463 |
break; |
|
| 464 |
case IPR_SYSPTBR: |
|
| 465 |
if (env->features & FEATURE_VIRBND) |
|
| 466 |
env->ipr[IPR_SYSPTBR] = val; |
|
| 467 |
else |
|
| 468 |
ret = -1; |
|
| 469 |
break; |
|
| 470 |
case IPR_TBCHK: |
|
| 471 |
/* Read-only */ |
|
| 472 |
ret = -1; |
|
| 473 |
break; |
|
| 474 |
case IPR_TBIA: |
|
| 475 |
tlb_flush(env, 1); |
|
| 476 |
break; |
|
| 477 |
case IPR_TBIAP: |
|
| 478 |
tlb_flush(env, 1); |
|
| 479 |
break; |
|
| 480 |
case IPR_TBIS: |
|
| 481 |
tlb_flush_page(env, val); |
|
| 482 |
break; |
|
| 483 |
case IPR_TBISD: |
|
| 484 |
tlb_flush_page(env, val); |
|
| 485 |
break; |
|
| 486 |
case IPR_TBISI: |
|
| 487 |
tlb_flush_page(env, val); |
|
| 488 |
break; |
|
| 489 |
case IPR_USP: |
|
| 490 |
if (env->features & FEATURE_SPS) |
|
| 491 |
env->ipr[IPR_USP] = val; |
|
| 492 |
else |
|
| 493 |
stq_raw(hwpcb + 24, val); |
|
| 494 |
break; |
|
| 495 |
case IPR_VIRBND: |
|
| 496 |
if (env->features & FEATURE_VIRBND) |
|
| 497 |
env->ipr[IPR_VIRBND] = val; |
|
| 498 |
else |
|
| 499 |
ret = -1; |
|
| 500 |
break; |
|
| 501 |
case IPR_VPTB: |
|
| 502 |
env->ipr[IPR_VPTB] = val; |
|
| 503 |
break; |
|
| 504 |
case IPR_WHAMI: |
|
| 505 |
/* Read-only */ |
|
| 506 |
ret = -1; |
|
| 507 |
break; |
|
| 508 |
default: |
|
| 509 |
/* Invalid */ |
|
| 510 |
ret = -1; |
|
| 511 |
break; |
|
| 512 |
} |
|
| 513 |
|
|
| 514 |
return ret; |
|
| 190 |
return 0; |
|
| 515 | 191 |
} |
| 516 | 192 |
|
| 517 | 193 |
void do_interrupt (CPUState *env) |
| 518 | 194 |
{
|
| 519 |
int excp; |
|
| 520 |
|
|
| 521 |
env->ipr[IPR_EXC_ADDR] = env->pc | 1; |
|
| 522 |
excp = env->exception_index; |
|
| 523 |
env->exception_index = -1; |
|
| 524 |
env->error_code = 0; |
|
| 525 |
/* XXX: disable interrupts and memory mapping */ |
|
| 526 |
if (env->ipr[IPR_PAL_BASE] != -1ULL) {
|
|
| 527 |
/* We use native PALcode */ |
|
| 528 |
env->pc = env->ipr[IPR_PAL_BASE] + excp; |
|
| 529 |
} else {
|
|
| 530 |
/* We use emulated PALcode */ |
|
| 531 |
abort(); |
|
| 532 |
/* Emulate REI */ |
|
| 533 |
env->pc = env->ipr[IPR_EXC_ADDR] & ~7; |
|
| 534 |
env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1; |
|
| 535 |
/* XXX: re-enable interrupts and memory mapping */ |
|
| 536 |
} |
|
| 195 |
abort(); |
|
| 537 | 196 |
} |
| 538 | 197 |
#endif |
| 539 | 198 |
|
| ... | ... | |
| 548 | 207 |
}; |
| 549 | 208 |
int i; |
| 550 | 209 |
|
| 551 |
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS " TARGET_FMT_lx "\n",
|
|
| 210 |
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
|
|
| 552 | 211 |
env->pc, env->ps); |
| 553 | 212 |
for (i = 0; i < 31; i++) {
|
| 554 | 213 |
cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, |
| b/target-alpha/helper.h | ||
|---|---|---|
| 101 | 101 |
|
| 102 | 102 |
#if !defined (CONFIG_USER_ONLY) |
| 103 | 103 |
DEF_HELPER_1(hw_ret, void, i64) |
| 104 |
DEF_HELPER_2(mfpr, i64, int, i64) |
|
| 105 |
DEF_HELPER_2(mtpr, void, int, i64) |
|
| 106 | 104 |
|
| 107 | 105 |
DEF_HELPER_1(ldl_phys, i64, i64) |
| 108 | 106 |
DEF_HELPER_1(ldq_phys, i64, i64) |
| b/target-alpha/op_helper.c | ||
|---|---|---|
| 373 | 373 |
if (exc) {
|
| 374 | 374 |
uint32_t hw_exc = 0; |
| 375 | 375 |
|
| 376 |
env->ipr[IPR_EXC_MASK] |= 1ull << regno;
|
|
| 376 |
env->trap_arg1 = 1ull << regno;
|
|
| 377 | 377 |
|
| 378 | 378 |
if (exc & float_flag_invalid) {
|
| 379 | 379 |
hw_exc |= EXC_M_INV; |
| ... | ... | |
| 1159 | 1159 |
void helper_hw_ret (uint64_t a) |
| 1160 | 1160 |
{
|
| 1161 | 1161 |
env->pc = a & ~3; |
| 1162 |
env->ipr[IPR_EXC_ADDR] = a & 1;
|
|
| 1162 |
env->pal_mode = a & 1;
|
|
| 1163 | 1163 |
env->intr_flag = 0; |
| 1164 | 1164 |
env->lock_addr = -1; |
| 1165 | 1165 |
} |
| 1166 |
|
|
| 1167 |
uint64_t helper_mfpr (int iprn, uint64_t val) |
|
| 1168 |
{
|
|
| 1169 |
uint64_t tmp; |
|
| 1170 |
|
|
| 1171 |
if (cpu_alpha_mfpr(env, iprn, &tmp) == 0) |
|
| 1172 |
val = tmp; |
|
| 1173 |
|
|
| 1174 |
return val; |
|
| 1175 |
} |
|
| 1176 |
|
|
| 1177 |
void helper_mtpr (int iprn, uint64_t val) |
|
| 1178 |
{
|
|
| 1179 |
cpu_alpha_mtpr(env, iprn, val, NULL); |
|
| 1180 |
} |
|
| 1181 | 1166 |
#endif |
| 1182 | 1167 |
|
| 1183 | 1168 |
/*****************************************************************************/ |
| b/target-alpha/translate.c | ||
|---|---|---|
| 2576 | 2576 |
break; |
| 2577 | 2577 |
case 0x19: |
| 2578 | 2578 |
/* HW_MFPR (PALcode) */ |
| 2579 |
#if defined (CONFIG_USER_ONLY) |
|
| 2580 | 2579 |
goto invalid_opc; |
| 2581 |
#else |
|
| 2582 |
if (!ctx->pal_mode) |
|
| 2583 |
goto invalid_opc; |
|
| 2584 |
if (ra != 31) {
|
|
| 2585 |
TCGv tmp = tcg_const_i32(insn & 0xFF); |
|
| 2586 |
gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); |
|
| 2587 |
tcg_temp_free(tmp); |
|
| 2588 |
} |
|
| 2589 |
break; |
|
| 2590 |
#endif |
|
| 2591 | 2580 |
case 0x1A: |
| 2592 | 2581 |
/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch |
| 2593 | 2582 |
prediction stack action, which of course we don't implement. */ |
| ... | ... | |
| 2856 | 2845 |
break; |
| 2857 | 2846 |
case 0x1D: |
| 2858 | 2847 |
/* HW_MTPR (PALcode) */ |
| 2859 |
#if defined (CONFIG_USER_ONLY) |
|
| 2860 | 2848 |
goto invalid_opc; |
| 2861 |
#else |
|
| 2862 |
if (!ctx->pal_mode) |
|
| 2863 |
goto invalid_opc; |
|
| 2864 |
else {
|
|
| 2865 |
TCGv tmp1 = tcg_const_i32(insn & 0xFF); |
|
| 2866 |
if (ra != 31) |
|
| 2867 |
gen_helper_mtpr(tmp1, cpu_ir[ra]); |
|
| 2868 |
else {
|
|
| 2869 |
TCGv tmp2 = tcg_const_i64(0); |
|
| 2870 |
gen_helper_mtpr(tmp1, tmp2); |
|
| 2871 |
tcg_temp_free(tmp2); |
|
| 2872 |
} |
|
| 2873 |
tcg_temp_free(tmp1); |
|
| 2874 |
ret = EXIT_PC_STALE; |
|
| 2875 |
} |
|
| 2876 |
break; |
|
| 2877 |
#endif |
|
| 2878 | 2849 |
case 0x1E: |
| 2879 | 2850 |
/* HW_RET (PALcode) */ |
| 2880 | 2851 |
#if defined (CONFIG_USER_ONLY) |
| ... | ... | |
| 2887 | 2858 |
address from EXC_ADDR. This turns out to be useful for our |
| 2888 | 2859 |
emulation PALcode, so continue to accept it. */ |
| 2889 | 2860 |
TCGv tmp = tcg_temp_new(); |
| 2890 |
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, ipr[IPR_EXC_ADDR]));
|
|
| 2861 |
/* FIXME: Get exc_addr. */
|
|
| 2891 | 2862 |
gen_helper_hw_ret(tmp); |
| 2892 | 2863 |
tcg_temp_free(tmp); |
| 2893 | 2864 |
} else {
|
| ... | ... | |
| 3131 | 3102 |
ctx.mem_idx = 0; |
| 3132 | 3103 |
#else |
| 3133 | 3104 |
ctx.mem_idx = ((env->ps >> 3) & 3); |
| 3134 |
ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
|
|
| 3105 |
ctx.pal_mode = env->pal_mode;
|
|
| 3135 | 3106 |
#endif |
| 3136 | 3107 |
|
| 3137 | 3108 |
/* ??? Every TB begins with unset rounding mode, to be initialized on |
| ... | ... | |
| 3297 | 3268 |
env->implver = implver; |
| 3298 | 3269 |
env->amask = amask; |
| 3299 | 3270 |
|
| 3300 |
env->ps = 0x1F00; |
|
| 3301 | 3271 |
#if defined (CONFIG_USER_ONLY) |
| 3302 |
env->ps |= 1 << 3;
|
|
| 3272 |
env->ps = 1 << 3; |
|
| 3303 | 3273 |
cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD |
| 3304 | 3274 |
| FPCR_UNFD | FPCR_INED | FPCR_DNOD)); |
| 3305 | 3275 |
#endif |
| 3306 | 3276 |
env->lock_addr = -1; |
| 3307 | 3277 |
|
| 3308 |
/* Initialize IPR */ |
|
| 3309 |
#if defined (CONFIG_USER_ONLY) |
|
| 3310 |
env->ipr[IPR_EXC_ADDR] = 0; |
|
| 3311 |
env->ipr[IPR_EXC_SUM] = 0; |
|
| 3312 |
env->ipr[IPR_EXC_MASK] = 0; |
|
| 3313 |
#else |
|
| 3314 |
{
|
|
| 3315 |
// uint64_t hwpcb; |
|
| 3316 |
// hwpcb = env->ipr[IPR_PCBB]; |
|
| 3317 |
env->ipr[IPR_ASN] = 0; |
|
| 3318 |
env->ipr[IPR_ASTEN] = 0; |
|
| 3319 |
env->ipr[IPR_ASTSR] = 0; |
|
| 3320 |
env->ipr[IPR_DATFX] = 0; |
|
| 3321 |
/* XXX: fix this */ |
|
| 3322 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); |
|
| 3323 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); |
|
| 3324 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); |
|
| 3325 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); |
|
| 3326 |
env->ipr[IPR_FEN] = 0; |
|
| 3327 |
env->ipr[IPR_IPL] = 31; |
|
| 3328 |
env->ipr[IPR_MCES] = 0; |
|
| 3329 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
|
| 3330 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); |
|
| 3331 |
env->ipr[IPR_SISR] = 0; |
|
| 3332 |
env->ipr[IPR_VIRBND] = -1ULL; |
|
| 3333 |
} |
|
| 3334 |
#endif |
|
| 3335 |
|
|
| 3336 | 3278 |
qemu_init_vcpu(env); |
| 3337 | 3279 |
return env; |
| 3338 | 3280 |
} |
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