Revision 129d8aa5 target-alpha/cpu.h
| b/target-alpha/cpu.h | ||
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#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) |
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/* Internal processor registers */ |
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/* XXX: TOFIX: most of those registers are implementation dependant */ |
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enum {
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#if defined(CONFIG_USER_ONLY) |
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IPR_EXC_ADDR, |
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IPR_EXC_SUM, |
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IPR_EXC_MASK, |
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#else |
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/* Ebox IPRs */ |
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IPR_CC = 0xC0, /* 21264 */ |
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IPR_CC_CTL = 0xC1, /* 21264 */ |
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#define IPR_CC_CTL_ENA_SHIFT 32 |
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#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL |
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IPR_VA = 0xC2, /* 21264 */ |
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IPR_VA_CTL = 0xC4, /* 21264 */ |
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#define IPR_VA_CTL_VA_48_SHIFT 1 |
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#define IPR_VA_CTL_VPTB_SHIFT 30 |
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IPR_VA_FORM = 0xC3, /* 21264 */ |
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/* Ibox IPRs */ |
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IPR_ITB_TAG = 0x00, /* 21264 */ |
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IPR_ITB_PTE = 0x01, /* 21264 */ |
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IPR_ITB_IAP = 0x02, |
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IPR_ITB_IA = 0x03, /* 21264 */ |
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IPR_ITB_IS = 0x04, /* 21264 */ |
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IPR_PMPC = 0x05, |
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IPR_EXC_ADDR = 0x06, /* 21264 */ |
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IPR_IVA_FORM = 0x07, /* 21264 */ |
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IPR_CM = 0x09, /* 21264 */ |
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#define IPR_CM_SHIFT 3 |
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#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */ |
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IPR_IER = 0x0A, /* 21264 */ |
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#define IPR_IER_MASK 0x0000007fffffe000ULL |
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IPR_IER_CM = 0x0B, /* 21264: = CM | IER */ |
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IPR_SIRR = 0x0C, /* 21264 */ |
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#define IPR_SIRR_SHIFT 14 |
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#define IPR_SIRR_MASK 0x7fff |
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IPR_ISUM = 0x0D, /* 21264 */ |
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IPR_HW_INT_CLR = 0x0E, /* 21264 */ |
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IPR_EXC_SUM = 0x0F, |
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IPR_PAL_BASE = 0x10, |
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IPR_I_CTL = 0x11, |
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#define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */ |
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#define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */ |
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#define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */ |
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#define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */ |
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#define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */ |
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#define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */ |
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#define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */ |
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#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */ |
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IPR_I_STAT = 0x16, /* 21264 */ |
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IPR_IC_FLUSH = 0x13, /* 21264 */ |
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IPR_IC_FLUSH_ASM = 0x12, /* 21264 */ |
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IPR_CLR_MAP = 0x15, |
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IPR_SLEEP = 0x17, |
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IPR_PCTX = 0x40, |
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IPR_PCTX_ASN = 0x01, /* field */ |
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#define IPR_PCTX_ASN_SHIFT 39 |
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IPR_PCTX_ASTER = 0x02, /* field */ |
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#define IPR_PCTX_ASTER_SHIFT 5 |
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IPR_PCTX_ASTRR = 0x04, /* field */ |
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#define IPR_PCTX_ASTRR_SHIFT 9 |
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IPR_PCTX_PPCE = 0x08, /* field */ |
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#define IPR_PCTX_PPCE_SHIFT 1 |
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IPR_PCTX_FPE = 0x10, /* field */ |
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#define IPR_PCTX_FPE_SHIFT 2 |
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IPR_PCTX_ALL = 0x5f, /* all fields */ |
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IPR_PCTR_CTL = 0x14, /* 21264 */ |
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/* Mbox IPRs */ |
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IPR_DTB_TAG0 = 0x20, /* 21264 */ |
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IPR_DTB_TAG1 = 0xA0, /* 21264 */ |
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IPR_DTB_PTE0 = 0x21, /* 21264 */ |
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IPR_DTB_PTE1 = 0xA1, /* 21264 */ |
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IPR_DTB_ALTMODE = 0xA6, |
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IPR_DTB_ALTMODE0 = 0x26, /* 21264 */ |
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#define IPR_DTB_ALTMODE_MASK 3 |
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IPR_DTB_IAP = 0xA2, |
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IPR_DTB_IA = 0xA3, /* 21264 */ |
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IPR_DTB_IS0 = 0x24, |
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IPR_DTB_IS1 = 0xA4, |
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IPR_DTB_ASN0 = 0x25, /* 21264 */ |
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IPR_DTB_ASN1 = 0xA5, /* 21264 */ |
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#define IPR_DTB_ASN_SHIFT 56 |
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IPR_MM_STAT = 0x27, /* 21264 */ |
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IPR_M_CTL = 0x28, /* 21264 */ |
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#define IPR_M_CTL_SPE_SHIFT 1 |
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#define IPR_M_CTL_SPE_MASK 7 |
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IPR_DC_CTL = 0x29, /* 21264 */ |
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IPR_DC_STAT = 0x2A, /* 21264 */ |
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/* Cbox IPRs */ |
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IPR_C_DATA = 0x2B, |
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IPR_C_SHIFT = 0x2C, |
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IPR_ASN, |
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IPR_ASTEN, |
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IPR_ASTSR, |
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IPR_DATFX, |
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IPR_ESP, |
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IPR_FEN, |
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IPR_IPIR, |
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IPR_IPL, |
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IPR_KSP, |
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IPR_MCES, |
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IPR_PERFMON, |
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IPR_PCBB, |
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IPR_PRBR, |
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IPR_PTBR, |
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IPR_SCBB, |
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IPR_SISR, |
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IPR_SSP, |
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IPR_SYSPTBR, |
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IPR_TBCHK, |
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IPR_TBIA, |
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IPR_TBIAP, |
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IPR_TBIS, |
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IPR_TBISD, |
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IPR_TBISI, |
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IPR_USP, |
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IPR_VIRBND, |
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IPR_VPTB, |
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IPR_WHAMI, |
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IPR_ALT_MODE, |
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#endif |
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IPR_LAST, |
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}; |
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/* MMU modes definitions */ |
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/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user. |
| ... | ... | |
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uint64_t ir[31]; |
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float64 fir[31]; |
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uint64_t pc; |
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uint64_t ipr[IPR_LAST]; |
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uint64_t ps; |
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uint64_t unique; |
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uint64_t lock_addr; |
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uint64_t lock_st_addr; |
| ... | ... | |
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uint8_t fpcr_dnod; |
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uint8_t fpcr_undz; |
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/* Used for HW_LD / HW_ST */
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uint8_t saved_mode;
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/* For RC and RS */
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/* The Internal Processor Registers. Some of these we assume always
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exist for use in user-mode. */
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uint8_t ps;
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uint8_t intr_flag; |
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uint8_t pal_mode; |
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/* These pass data from the exception logic in the translator and |
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helpers to the OS entry point. This is used for both system |
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emulation and user-mode. */ |
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uint64_t trap_arg0; |
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uint64_t trap_arg1; |
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uint64_t trap_arg2; |
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#if TARGET_LONG_BITS > HOST_LONG_BITS |
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/* temporary fixed-point registers |
| ... | ... | |
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/* Those resources are used only in Qemu core */ |
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CPU_COMMON |
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uint32_t hflags; |
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int error_code; |
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uint32_t features; |
| ... | ... | |
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uint64_t cpu_alpha_load_fpcr (CPUState *env); |
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void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); |
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int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); |
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int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); |
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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target_ulong *cs_base, int *flags) |
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