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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
24 | 4ad40f36 | bellard | |
25 | 6af0bf9c | bellard | /*****************************************************************************/
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26 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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27 | 6af0bf9c | bellard | void cpu_loop_exit(void) |
28 | 6af0bf9c | bellard | { |
29 | 6af0bf9c | bellard | longjmp(env->jmp_env, 1);
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30 | 6af0bf9c | bellard | } |
31 | 6af0bf9c | bellard | |
32 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
33 | 6af0bf9c | bellard | { |
34 | 6af0bf9c | bellard | #if 1 |
35 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
36 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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37 | 6af0bf9c | bellard | #endif
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38 | 6af0bf9c | bellard | env->exception_index = exception; |
39 | 6af0bf9c | bellard | env->error_code = error_code; |
40 | 6af0bf9c | bellard | T0 = 0;
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41 | 6af0bf9c | bellard | cpu_loop_exit(); |
42 | 6af0bf9c | bellard | } |
43 | 6af0bf9c | bellard | |
44 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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45 | 6af0bf9c | bellard | { |
46 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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47 | 6af0bf9c | bellard | } |
48 | 6af0bf9c | bellard | |
49 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
50 | 4ad40f36 | bellard | { |
51 | 4ad40f36 | bellard | TranslationBlock *tb; |
52 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
53 | 4ad40f36 | bellard | |
54 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
55 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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56 | 4ad40f36 | bellard | } |
57 | 4ad40f36 | bellard | |
58 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code) |
59 | 4ad40f36 | bellard | { |
60 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
61 | e397ee33 | ths | do_raise_exception_err (exception, error_code); |
62 | e397ee33 | ths | } |
63 | e397ee33 | ths | |
64 | e397ee33 | ths | void do_raise_exception_direct (uint32_t exception)
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65 | e397ee33 | ths | { |
66 | e397ee33 | ths | do_raise_exception_direct_err (exception, 0);
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67 | 4ad40f36 | bellard | } |
68 | 4ad40f36 | bellard | |
69 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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70 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
71 | 6af0bf9c | bellard | #undef MEMSUFFIX
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72 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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73 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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74 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
75 | 6af0bf9c | bellard | #undef MEMSUFFIX
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76 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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77 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
78 | 6af0bf9c | bellard | #undef MEMSUFFIX
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79 | 6af0bf9c | bellard | #endif
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80 | 6af0bf9c | bellard | |
81 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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82 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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83 | c570fd16 | ths | /* Those might call libgcc functions. */
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84 | c570fd16 | ths | void do_dsll (void) |
85 | c570fd16 | ths | { |
86 | c570fd16 | ths | T0 = T0 << T1; |
87 | c570fd16 | ths | } |
88 | c570fd16 | ths | |
89 | c570fd16 | ths | void do_dsll32 (void) |
90 | c570fd16 | ths | { |
91 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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92 | c570fd16 | ths | } |
93 | c570fd16 | ths | |
94 | c570fd16 | ths | void do_dsra (void) |
95 | c570fd16 | ths | { |
96 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
97 | c570fd16 | ths | } |
98 | c570fd16 | ths | |
99 | c570fd16 | ths | void do_dsra32 (void) |
100 | c570fd16 | ths | { |
101 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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102 | c570fd16 | ths | } |
103 | c570fd16 | ths | |
104 | c570fd16 | ths | void do_dsrl (void) |
105 | c570fd16 | ths | { |
106 | c570fd16 | ths | T0 = T0 >> T1; |
107 | c570fd16 | ths | } |
108 | c570fd16 | ths | |
109 | c570fd16 | ths | void do_dsrl32 (void) |
110 | c570fd16 | ths | { |
111 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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112 | c570fd16 | ths | } |
113 | c570fd16 | ths | |
114 | c570fd16 | ths | void do_drotr (void) |
115 | c570fd16 | ths | { |
116 | c570fd16 | ths | target_ulong tmp; |
117 | c570fd16 | ths | |
118 | c570fd16 | ths | if (T1) {
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119 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
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120 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
121 | 5a63bcb2 | ths | } |
122 | c570fd16 | ths | } |
123 | c570fd16 | ths | |
124 | c570fd16 | ths | void do_drotr32 (void) |
125 | c570fd16 | ths | { |
126 | c570fd16 | ths | target_ulong tmp; |
127 | c570fd16 | ths | |
128 | c570fd16 | ths | if (T1) {
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129 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
130 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
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131 | 5a63bcb2 | ths | } |
132 | c570fd16 | ths | } |
133 | c570fd16 | ths | |
134 | c570fd16 | ths | void do_dsllv (void) |
135 | c570fd16 | ths | { |
136 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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137 | c570fd16 | ths | } |
138 | c570fd16 | ths | |
139 | c570fd16 | ths | void do_dsrav (void) |
140 | c570fd16 | ths | { |
141 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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142 | c570fd16 | ths | } |
143 | c570fd16 | ths | |
144 | c570fd16 | ths | void do_dsrlv (void) |
145 | c570fd16 | ths | { |
146 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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147 | c570fd16 | ths | } |
148 | c570fd16 | ths | |
149 | c570fd16 | ths | void do_drotrv (void) |
150 | c570fd16 | ths | { |
151 | c570fd16 | ths | target_ulong tmp; |
152 | c570fd16 | ths | |
153 | c570fd16 | ths | T0 &= 0x3F;
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154 | c570fd16 | ths | if (T0) {
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155 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
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156 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
157 | c570fd16 | ths | } else
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158 | c570fd16 | ths | T0 = T1; |
159 | c570fd16 | ths | } |
160 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
161 | 60aa19ab | ths | #endif /* TARGET_MIPS64 */ |
162 | c570fd16 | ths | |
163 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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164 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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165 | 6af0bf9c | bellard | static inline uint64_t get_HILO (void) |
166 | 6af0bf9c | bellard | { |
167 | 7495fd0f | ths | return (env->HI << 32) | (uint32_t)env->LO; |
168 | 6af0bf9c | bellard | } |
169 | 6af0bf9c | bellard | |
170 | 6af0bf9c | bellard | static inline void set_HILO (uint64_t HILO) |
171 | 6af0bf9c | bellard | { |
172 | 7495fd0f | ths | env->LO = (int32_t)HILO; |
173 | 5dc4b744 | ths | env->HI = (int32_t)(HILO >> 32);
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174 | 6af0bf9c | bellard | } |
175 | 6af0bf9c | bellard | |
176 | 6af0bf9c | bellard | void do_mult (void) |
177 | 6af0bf9c | bellard | { |
178 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
179 | 6af0bf9c | bellard | } |
180 | 6af0bf9c | bellard | |
181 | 6af0bf9c | bellard | void do_multu (void) |
182 | 6af0bf9c | bellard | { |
183 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
184 | 6af0bf9c | bellard | } |
185 | 6af0bf9c | bellard | |
186 | 6af0bf9c | bellard | void do_madd (void) |
187 | 6af0bf9c | bellard | { |
188 | 6af0bf9c | bellard | int64_t tmp; |
189 | 6af0bf9c | bellard | |
190 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
191 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
192 | 6af0bf9c | bellard | } |
193 | 6af0bf9c | bellard | |
194 | 6af0bf9c | bellard | void do_maddu (void) |
195 | 6af0bf9c | bellard | { |
196 | 6af0bf9c | bellard | uint64_t tmp; |
197 | 6af0bf9c | bellard | |
198 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
199 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
200 | 6af0bf9c | bellard | } |
201 | 6af0bf9c | bellard | |
202 | 6af0bf9c | bellard | void do_msub (void) |
203 | 6af0bf9c | bellard | { |
204 | 6af0bf9c | bellard | int64_t tmp; |
205 | 6af0bf9c | bellard | |
206 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
207 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
208 | 6af0bf9c | bellard | } |
209 | 6af0bf9c | bellard | |
210 | 6af0bf9c | bellard | void do_msubu (void) |
211 | 6af0bf9c | bellard | { |
212 | 6af0bf9c | bellard | uint64_t tmp; |
213 | 6af0bf9c | bellard | |
214 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
215 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
216 | 6af0bf9c | bellard | } |
217 | 6af0bf9c | bellard | #endif
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218 | 6af0bf9c | bellard | |
219 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
220 | 80c27194 | ths | void do_div (void) |
221 | 80c27194 | ths | { |
222 | 80c27194 | ths | /* 64bit datatypes because we may see overflow/underflow. */
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223 | 80c27194 | ths | if (T1 != 0) { |
224 | 80c27194 | ths | env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1); |
225 | 80c27194 | ths | env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1); |
226 | 80c27194 | ths | } |
227 | 80c27194 | ths | } |
228 | 80c27194 | ths | #endif
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229 | 80c27194 | ths | |
230 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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231 | c570fd16 | ths | void do_ddiv (void) |
232 | c570fd16 | ths | { |
233 | c570fd16 | ths | if (T1 != 0) { |
234 | 2d0e944d | ths | lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
235 | 2d0e944d | ths | env->LO = res.quot; |
236 | 2d0e944d | ths | env->HI = res.rem; |
237 | c570fd16 | ths | } |
238 | c570fd16 | ths | } |
239 | c570fd16 | ths | |
240 | 12a4b2aa | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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241 | c570fd16 | ths | void do_ddivu (void) |
242 | c570fd16 | ths | { |
243 | c570fd16 | ths | if (T1 != 0) { |
244 | 12a4b2aa | ths | env->LO = T0 / T1; |
245 | 12a4b2aa | ths | env->HI = T0 % T1; |
246 | c570fd16 | ths | } |
247 | c570fd16 | ths | } |
248 | c570fd16 | ths | #endif
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249 | 12a4b2aa | ths | #endif /* TARGET_MIPS64 */ |
250 | c570fd16 | ths | |
251 | 048f6b4d | bellard | #if defined(CONFIG_USER_ONLY)
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252 | 873eb012 | ths | void do_mfc0_random (void) |
253 | 048f6b4d | bellard | { |
254 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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255 | 048f6b4d | bellard | } |
256 | 873eb012 | ths | |
257 | 873eb012 | ths | void do_mfc0_count (void) |
258 | 873eb012 | ths | { |
259 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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260 | 873eb012 | ths | } |
261 | 873eb012 | ths | |
262 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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263 | 048f6b4d | bellard | { |
264 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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265 | 8c0fdd85 | ths | } |
266 | 8c0fdd85 | ths | |
267 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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268 | 8c0fdd85 | ths | { |
269 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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270 | 8c0fdd85 | ths | } |
271 | 8c0fdd85 | ths | |
272 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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273 | 4de9b249 | ths | { |
274 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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275 | 4de9b249 | ths | } |
276 | 4de9b249 | ths | |
277 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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278 | 8c0fdd85 | ths | { |
279 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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280 | 8c0fdd85 | ths | } |
281 | 8c0fdd85 | ths | |
282 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
283 | 8c0fdd85 | ths | { |
284 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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285 | 048f6b4d | bellard | } |
286 | 048f6b4d | bellard | |
287 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
288 | 8c0fdd85 | ths | { |
289 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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290 | 8c0fdd85 | ths | } |
291 | 8c0fdd85 | ths | |
292 | 048f6b4d | bellard | #else
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293 | 048f6b4d | bellard | |
294 | 6af0bf9c | bellard | /* CP0 helpers */
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295 | 873eb012 | ths | void do_mfc0_random (void) |
296 | 6af0bf9c | bellard | { |
297 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
298 | 873eb012 | ths | } |
299 | 6af0bf9c | bellard | |
300 | 873eb012 | ths | void do_mfc0_count (void) |
301 | 873eb012 | ths | { |
302 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
303 | 6af0bf9c | bellard | } |
304 | 6af0bf9c | bellard | |
305 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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306 | 6af0bf9c | bellard | { |
307 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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308 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
309 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
310 | f41c52f1 | ths | env->CP0_Cause); |
311 | f41c52f1 | ths | (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
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312 | f41c52f1 | ths | : fputs("\n", logfile);
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313 | 8c0fdd85 | ths | } |
314 | 8c0fdd85 | ths | |
315 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
316 | 8c0fdd85 | ths | { |
317 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
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318 | 6af0bf9c | bellard | } |
319 | 6af0bf9c | bellard | |
320 | 6ea83fed | bellard | void fpu_handle_exception(void) |
321 | 6ea83fed | bellard | { |
322 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
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323 | 6ea83fed | bellard | int flags = get_float_exception_flags(&env->fp_status);
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324 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
325 | 6ea83fed | bellard | |
326 | 6ea83fed | bellard | enable = GET_FP_ENABLE(env->fcr31); |
327 | 6ea83fed | bellard | |
328 | 6ea83fed | bellard | /* determine current flags */
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329 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
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330 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
331 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
332 | 6ea83fed | bellard | } |
333 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
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334 | 6ea83fed | bellard | cpuflags |= FP_DIV0; |
335 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
336 | 6ea83fed | bellard | } |
337 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
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338 | 6ea83fed | bellard | cpuflags |= FP_OVERFLOW; |
339 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
340 | 6ea83fed | bellard | } |
341 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
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342 | 6ea83fed | bellard | cpuflags |= FP_UNDERFLOW; |
343 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
344 | 6ea83fed | bellard | } |
345 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
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346 | 6ea83fed | bellard | cpuflags |= FP_INEXACT; |
347 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
348 | 6ea83fed | bellard | } |
349 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, cpuflags); |
350 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, cause); |
351 | 6ea83fed | bellard | #else
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352 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, 0);
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353 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, 0);
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354 | 6ea83fed | bellard | #endif
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355 | 6ea83fed | bellard | } |
356 | 6ea83fed | bellard | |
357 | 6af0bf9c | bellard | /* TLB management */
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358 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
359 | 814b9a47 | ths | { |
360 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
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361 | 814b9a47 | ths | tlb_flush (env, flush_global); |
362 | fcb4a419 | ths | env->tlb_in_use = env->nb_tlb; |
363 | 814b9a47 | ths | } |
364 | 814b9a47 | ths | |
365 | 29929e34 | ths | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
366 | 814b9a47 | ths | { |
367 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
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368 | 814b9a47 | ths | while (env->tlb_in_use > first) {
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369 | 29929e34 | ths | r4k_invalidate_tlb(env, --env->tlb_in_use, 0);
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370 | 814b9a47 | ths | } |
371 | 814b9a47 | ths | } |
372 | 814b9a47 | ths | |
373 | 29929e34 | ths | static void r4k_fill_tlb (int idx) |
374 | 6af0bf9c | bellard | { |
375 | 29929e34 | ths | r4k_tlb_t *tlb; |
376 | 6af0bf9c | bellard | |
377 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
378 | 29929e34 | ths | tlb = &env->mmu.r4k.tlb[idx]; |
379 | f2e9ebef | ths | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
380 | 100ce988 | ths | #ifdef TARGET_MIPS64
|
381 | 100ce988 | ths | tlb->VPN &= 0xC00000FFFFFFFFFFULL;
|
382 | 100ce988 | ths | #endif
|
383 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
384 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
385 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
386 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
387 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
388 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
389 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
390 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
391 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
392 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
393 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
394 | 6af0bf9c | bellard | } |
395 | 6af0bf9c | bellard | |
396 | 29929e34 | ths | void r4k_do_tlbwi (void) |
397 | 6af0bf9c | bellard | { |
398 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
|
399 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
|
400 | 814b9a47 | ths | that might be a further win. */
|
401 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, env->nb_tlb); |
402 | 814b9a47 | ths | |
403 | 29929e34 | ths | r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
|
404 | 29929e34 | ths | r4k_fill_tlb(env->CP0_Index % env->nb_tlb); |
405 | 6af0bf9c | bellard | } |
406 | 6af0bf9c | bellard | |
407 | 29929e34 | ths | void r4k_do_tlbwr (void) |
408 | 6af0bf9c | bellard | { |
409 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
410 | 6af0bf9c | bellard | |
411 | 29929e34 | ths | r4k_invalidate_tlb(env, r, 1);
|
412 | 29929e34 | ths | r4k_fill_tlb(r); |
413 | 6af0bf9c | bellard | } |
414 | 6af0bf9c | bellard | |
415 | 29929e34 | ths | void r4k_do_tlbp (void) |
416 | 6af0bf9c | bellard | { |
417 | 29929e34 | ths | r4k_tlb_t *tlb; |
418 | f2e9ebef | ths | target_ulong mask; |
419 | 6af0bf9c | bellard | target_ulong tag; |
420 | f2e9ebef | ths | target_ulong VPN; |
421 | 6af0bf9c | bellard | uint8_t ASID; |
422 | 6af0bf9c | bellard | int i;
|
423 | 6af0bf9c | bellard | |
424 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
425 | fcb4a419 | ths | for (i = 0; i < env->nb_tlb; i++) { |
426 | 29929e34 | ths | tlb = &env->mmu.r4k.tlb[i]; |
427 | f2e9ebef | ths | /* 1k pages are not supported. */
|
428 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
429 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
430 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
431 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
432 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
433 | 6af0bf9c | bellard | /* TLB match */
|
434 | 9c2149c8 | ths | env->CP0_Index = i; |
435 | 6af0bf9c | bellard | break;
|
436 | 6af0bf9c | bellard | } |
437 | 6af0bf9c | bellard | } |
438 | fcb4a419 | ths | if (i == env->nb_tlb) {
|
439 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
|
440 | fcb4a419 | ths | for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
|
441 | 29929e34 | ths | tlb = &env->mmu.r4k.tlb[i]; |
442 | f2e9ebef | ths | /* 1k pages are not supported. */
|
443 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
444 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
445 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
446 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
447 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
448 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, i); |
449 | 814b9a47 | ths | break;
|
450 | 814b9a47 | ths | } |
451 | 814b9a47 | ths | } |
452 | 814b9a47 | ths | |
453 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
454 | 6af0bf9c | bellard | } |
455 | 6af0bf9c | bellard | } |
456 | 6af0bf9c | bellard | |
457 | 29929e34 | ths | void r4k_do_tlbr (void) |
458 | 6af0bf9c | bellard | { |
459 | 29929e34 | ths | r4k_tlb_t *tlb; |
460 | 09c56b84 | pbrook | uint8_t ASID; |
461 | 6af0bf9c | bellard | |
462 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
463 | 29929e34 | ths | tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb]; |
464 | 4ad40f36 | bellard | |
465 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
466 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
467 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
468 | 814b9a47 | ths | |
469 | 29929e34 | ths | r4k_mips_tlb_flush_extra(env, env->nb_tlb); |
470 | 4ad40f36 | bellard | |
471 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
472 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
473 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
474 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
475 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
476 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
477 | 6af0bf9c | bellard | } |
478 | 6af0bf9c | bellard | |
479 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
480 | 048f6b4d | bellard | |
481 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
482 | 6af0bf9c | bellard | { |
483 | 6af0bf9c | bellard | if (loglevel)
|
484 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
485 | 6af0bf9c | bellard | } |
486 | 6af0bf9c | bellard | |
487 | 6af0bf9c | bellard | void dump_sc (void) |
488 | 6af0bf9c | bellard | { |
489 | 6af0bf9c | bellard | if (loglevel) {
|
490 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
491 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
492 | 6af0bf9c | bellard | } |
493 | 6af0bf9c | bellard | } |
494 | 6af0bf9c | bellard | |
495 | f41c52f1 | ths | void debug_pre_eret (void) |
496 | 6af0bf9c | bellard | { |
497 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
498 | f41c52f1 | ths | env->PC, env->CP0_EPC); |
499 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
500 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
501 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
502 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
503 | f41c52f1 | ths | fputs("\n", logfile);
|
504 | f41c52f1 | ths | } |
505 | f41c52f1 | ths | |
506 | f41c52f1 | ths | void debug_post_eret (void) |
507 | f41c52f1 | ths | { |
508 | 744e0915 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
509 | f41c52f1 | ths | env->PC, env->CP0_EPC); |
510 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
511 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
512 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
513 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
514 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_UM)
|
515 | f41c52f1 | ths | fputs(", UM\n", logfile);
|
516 | f41c52f1 | ths | else
|
517 | 24c7b0e3 | ths | fputs("\n", logfile);
|
518 | 6af0bf9c | bellard | } |
519 | 6af0bf9c | bellard | |
520 | 6af0bf9c | bellard | void do_pmon (int function) |
521 | 6af0bf9c | bellard | { |
522 | 6af0bf9c | bellard | function /= 2;
|
523 | 6af0bf9c | bellard | switch (function) {
|
524 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
525 | 6af0bf9c | bellard | if (env->gpr[4] == 0) |
526 | 6af0bf9c | bellard | env->gpr[2] = -1; |
527 | 6af0bf9c | bellard | /* Fall through */
|
528 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
529 | 6af0bf9c | bellard | env->gpr[2] = -1; |
530 | 6af0bf9c | bellard | break;
|
531 | 6af0bf9c | bellard | case 3: |
532 | 6af0bf9c | bellard | case 12: |
533 | c570fd16 | ths | printf("%c", (char)(env->gpr[4] & 0xFF)); |
534 | 6af0bf9c | bellard | break;
|
535 | 6af0bf9c | bellard | case 17: |
536 | 6af0bf9c | bellard | break;
|
537 | 6af0bf9c | bellard | case 158: |
538 | 6af0bf9c | bellard | { |
539 | c570fd16 | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
540 | 6af0bf9c | bellard | printf("%s", fmt);
|
541 | 6af0bf9c | bellard | } |
542 | 6af0bf9c | bellard | break;
|
543 | 6af0bf9c | bellard | } |
544 | 6af0bf9c | bellard | } |
545 | e37e863f | bellard | |
546 | e37e863f | bellard | #if !defined(CONFIG_USER_ONLY)
|
547 | e37e863f | bellard | |
548 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
549 | 4ad40f36 | bellard | |
550 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
551 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
552 | e37e863f | bellard | |
553 | e37e863f | bellard | #define SHIFT 0 |
554 | e37e863f | bellard | #include "softmmu_template.h" |
555 | e37e863f | bellard | |
556 | e37e863f | bellard | #define SHIFT 1 |
557 | e37e863f | bellard | #include "softmmu_template.h" |
558 | e37e863f | bellard | |
559 | e37e863f | bellard | #define SHIFT 2 |
560 | e37e863f | bellard | #include "softmmu_template.h" |
561 | e37e863f | bellard | |
562 | e37e863f | bellard | #define SHIFT 3 |
563 | e37e863f | bellard | #include "softmmu_template.h" |
564 | e37e863f | bellard | |
565 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
566 | 4ad40f36 | bellard | { |
567 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
568 | 4ad40f36 | bellard | do_restore_state (retaddr); |
569 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
570 | 4ad40f36 | bellard | } |
571 | 4ad40f36 | bellard | |
572 | e37e863f | bellard | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
573 | e37e863f | bellard | { |
574 | e37e863f | bellard | TranslationBlock *tb; |
575 | e37e863f | bellard | CPUState *saved_env; |
576 | e37e863f | bellard | unsigned long pc; |
577 | e37e863f | bellard | int ret;
|
578 | e37e863f | bellard | |
579 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
580 | e37e863f | bellard | generated code */
|
581 | e37e863f | bellard | saved_env = env; |
582 | e37e863f | bellard | env = cpu_single_env; |
583 | e37e863f | bellard | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
584 | e37e863f | bellard | if (ret) {
|
585 | e37e863f | bellard | if (retaddr) {
|
586 | e37e863f | bellard | /* now we have a real cpu fault */
|
587 | e37e863f | bellard | pc = (unsigned long)retaddr; |
588 | e37e863f | bellard | tb = tb_find_pc(pc); |
589 | e37e863f | bellard | if (tb) {
|
590 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
591 | e37e863f | bellard | a virtual CPU fault */
|
592 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
593 | e37e863f | bellard | } |
594 | e37e863f | bellard | } |
595 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
596 | e37e863f | bellard | } |
597 | e37e863f | bellard | env = saved_env; |
598 | e37e863f | bellard | } |
599 | e37e863f | bellard | |
600 | e37e863f | bellard | #endif
|
601 | fd4a04eb | ths | |
602 | fd4a04eb | ths | /* Complex FPU operations which may need stack space. */
|
603 | fd4a04eb | ths | |
604 | fd4a04eb | ths | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
605 | fd4a04eb | ths | unsigned int ieee_rm[] = { |
606 | fd4a04eb | ths | float_round_nearest_even, |
607 | fd4a04eb | ths | float_round_to_zero, |
608 | fd4a04eb | ths | float_round_up, |
609 | fd4a04eb | ths | float_round_down |
610 | fd4a04eb | ths | }; |
611 | fd4a04eb | ths | |
612 | fd4a04eb | ths | #define RESTORE_ROUNDING_MODE \
|
613 | fd4a04eb | ths | set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
|
614 | fd4a04eb | ths | |
615 | fd4a04eb | ths | void do_ctc1 (void) |
616 | fd4a04eb | ths | { |
617 | fd4a04eb | ths | switch(T1) {
|
618 | fd4a04eb | ths | case 25: |
619 | fd4a04eb | ths | if (T0 & 0xffffff00) |
620 | fd4a04eb | ths | return;
|
621 | fd4a04eb | ths | env->fcr31 = (env->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
622 | fd4a04eb | ths | ((T0 & 0x1) << 23); |
623 | fd4a04eb | ths | break;
|
624 | fd4a04eb | ths | case 26: |
625 | fd4a04eb | ths | if (T0 & 0x007c0000) |
626 | fd4a04eb | ths | return;
|
627 | fd4a04eb | ths | env->fcr31 = (env->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
628 | fd4a04eb | ths | break;
|
629 | fd4a04eb | ths | case 28: |
630 | fd4a04eb | ths | if (T0 & 0x007c0000) |
631 | fd4a04eb | ths | return;
|
632 | fd4a04eb | ths | env->fcr31 = (env->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
633 | fd4a04eb | ths | ((T0 & 0x4) << 22); |
634 | fd4a04eb | ths | break;
|
635 | fd4a04eb | ths | case 31: |
636 | fd4a04eb | ths | if (T0 & 0x007c0000) |
637 | fd4a04eb | ths | return;
|
638 | fd4a04eb | ths | env->fcr31 = T0; |
639 | fd4a04eb | ths | break;
|
640 | fd4a04eb | ths | default:
|
641 | fd4a04eb | ths | return;
|
642 | fd4a04eb | ths | } |
643 | fd4a04eb | ths | /* set rounding mode */
|
644 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
645 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
646 | fd4a04eb | ths | if ((GET_FP_ENABLE(env->fcr31) | 0x20) & GET_FP_CAUSE(env->fcr31)) |
647 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
648 | fd4a04eb | ths | } |
649 | fd4a04eb | ths | |
650 | fd4a04eb | ths | inline char ieee_ex_to_mips(char xcpt) |
651 | fd4a04eb | ths | { |
652 | fd4a04eb | ths | return (xcpt & float_flag_inexact) >> 5 | |
653 | fd4a04eb | ths | (xcpt & float_flag_underflow) >> 3 |
|
654 | fd4a04eb | ths | (xcpt & float_flag_overflow) >> 1 |
|
655 | fd4a04eb | ths | (xcpt & float_flag_divbyzero) << 1 |
|
656 | fd4a04eb | ths | (xcpt & float_flag_invalid) << 4;
|
657 | fd4a04eb | ths | } |
658 | fd4a04eb | ths | |
659 | fd4a04eb | ths | inline char mips_ex_to_ieee(char xcpt) |
660 | fd4a04eb | ths | { |
661 | fd4a04eb | ths | return (xcpt & FP_INEXACT) << 5 | |
662 | fd4a04eb | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
663 | fd4a04eb | ths | (xcpt & FP_OVERFLOW) << 1 |
|
664 | fd4a04eb | ths | (xcpt & FP_DIV0) >> 1 |
|
665 | fd4a04eb | ths | (xcpt & FP_INVALID) >> 4;
|
666 | fd4a04eb | ths | } |
667 | fd4a04eb | ths | |
668 | fd4a04eb | ths | inline void update_fcr31(void) |
669 | fd4a04eb | ths | { |
670 | fd4a04eb | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fp_status));
|
671 | fd4a04eb | ths | |
672 | fd4a04eb | ths | SET_FP_CAUSE(env->fcr31, tmp); |
673 | fd4a04eb | ths | if (GET_FP_ENABLE(env->fcr31) & tmp)
|
674 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
675 | fd4a04eb | ths | else
|
676 | fd4a04eb | ths | UPDATE_FP_FLAGS(env->fcr31, tmp); |
677 | fd4a04eb | ths | } |
678 | fd4a04eb | ths | |
679 | fd4a04eb | ths | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
680 | fd4a04eb | ths | |
681 | fd4a04eb | ths | FLOAT_OP(cvtd, s) |
682 | fd4a04eb | ths | { |
683 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
684 | fd4a04eb | ths | FDT2 = float32_to_float64(FST0, &env->fp_status); |
685 | fd4a04eb | ths | update_fcr31(); |
686 | fd4a04eb | ths | } |
687 | fd4a04eb | ths | FLOAT_OP(cvtd, w) |
688 | fd4a04eb | ths | { |
689 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
690 | fd4a04eb | ths | FDT2 = int32_to_float64(WT0, &env->fp_status); |
691 | fd4a04eb | ths | update_fcr31(); |
692 | fd4a04eb | ths | } |
693 | fd4a04eb | ths | FLOAT_OP(cvtd, l) |
694 | fd4a04eb | ths | { |
695 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
696 | fd4a04eb | ths | FDT2 = int64_to_float64(DT0, &env->fp_status); |
697 | fd4a04eb | ths | update_fcr31(); |
698 | fd4a04eb | ths | } |
699 | fd4a04eb | ths | FLOAT_OP(cvtl, d) |
700 | fd4a04eb | ths | { |
701 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
702 | fd4a04eb | ths | DT2 = float64_to_int64(FDT0, &env->fp_status); |
703 | fd4a04eb | ths | update_fcr31(); |
704 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
705 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
706 | fd4a04eb | ths | } |
707 | fd4a04eb | ths | FLOAT_OP(cvtl, s) |
708 | fd4a04eb | ths | { |
709 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
710 | fd4a04eb | ths | DT2 = float32_to_int64(FST0, &env->fp_status); |
711 | fd4a04eb | ths | update_fcr31(); |
712 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
713 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
714 | fd4a04eb | ths | } |
715 | fd4a04eb | ths | |
716 | fd4a04eb | ths | FLOAT_OP(cvtps, pw) |
717 | fd4a04eb | ths | { |
718 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
719 | fd4a04eb | ths | FST2 = int32_to_float32(WT0, &env->fp_status); |
720 | fd4a04eb | ths | FSTH2 = int32_to_float32(WTH0, &env->fp_status); |
721 | fd4a04eb | ths | update_fcr31(); |
722 | fd4a04eb | ths | } |
723 | fd4a04eb | ths | FLOAT_OP(cvtpw, ps) |
724 | fd4a04eb | ths | { |
725 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
726 | fd4a04eb | ths | WT2 = float32_to_int32(FST0, &env->fp_status); |
727 | fd4a04eb | ths | WTH2 = float32_to_int32(FSTH0, &env->fp_status); |
728 | fd4a04eb | ths | update_fcr31(); |
729 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
730 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
731 | fd4a04eb | ths | } |
732 | fd4a04eb | ths | FLOAT_OP(cvts, d) |
733 | fd4a04eb | ths | { |
734 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
735 | fd4a04eb | ths | FST2 = float64_to_float32(FDT0, &env->fp_status); |
736 | fd4a04eb | ths | update_fcr31(); |
737 | fd4a04eb | ths | } |
738 | fd4a04eb | ths | FLOAT_OP(cvts, w) |
739 | fd4a04eb | ths | { |
740 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
741 | fd4a04eb | ths | FST2 = int32_to_float32(WT0, &env->fp_status); |
742 | fd4a04eb | ths | update_fcr31(); |
743 | fd4a04eb | ths | } |
744 | fd4a04eb | ths | FLOAT_OP(cvts, l) |
745 | fd4a04eb | ths | { |
746 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
747 | fd4a04eb | ths | FST2 = int64_to_float32(DT0, &env->fp_status); |
748 | fd4a04eb | ths | update_fcr31(); |
749 | fd4a04eb | ths | } |
750 | fd4a04eb | ths | FLOAT_OP(cvts, pl) |
751 | fd4a04eb | ths | { |
752 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
753 | fd4a04eb | ths | WT2 = WT0; |
754 | fd4a04eb | ths | update_fcr31(); |
755 | fd4a04eb | ths | } |
756 | fd4a04eb | ths | FLOAT_OP(cvts, pu) |
757 | fd4a04eb | ths | { |
758 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
759 | fd4a04eb | ths | WT2 = WTH0; |
760 | fd4a04eb | ths | update_fcr31(); |
761 | fd4a04eb | ths | } |
762 | fd4a04eb | ths | FLOAT_OP(cvtw, s) |
763 | fd4a04eb | ths | { |
764 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
765 | fd4a04eb | ths | WT2 = float32_to_int32(FST0, &env->fp_status); |
766 | fd4a04eb | ths | update_fcr31(); |
767 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
768 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
769 | fd4a04eb | ths | } |
770 | fd4a04eb | ths | FLOAT_OP(cvtw, d) |
771 | fd4a04eb | ths | { |
772 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
773 | fd4a04eb | ths | WT2 = float64_to_int32(FDT0, &env->fp_status); |
774 | fd4a04eb | ths | update_fcr31(); |
775 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
776 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
777 | fd4a04eb | ths | } |
778 | fd4a04eb | ths | |
779 | fd4a04eb | ths | FLOAT_OP(roundl, d) |
780 | fd4a04eb | ths | { |
781 | fd4a04eb | ths | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
782 | fd4a04eb | ths | DT2 = float64_round_to_int(FDT0, &env->fp_status); |
783 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
784 | fd4a04eb | ths | update_fcr31(); |
785 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
786 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
787 | fd4a04eb | ths | } |
788 | fd4a04eb | ths | FLOAT_OP(roundl, s) |
789 | fd4a04eb | ths | { |
790 | fd4a04eb | ths | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
791 | fd4a04eb | ths | DT2 = float32_round_to_int(FST0, &env->fp_status); |
792 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
793 | fd4a04eb | ths | update_fcr31(); |
794 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
795 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
796 | fd4a04eb | ths | } |
797 | fd4a04eb | ths | FLOAT_OP(roundw, d) |
798 | fd4a04eb | ths | { |
799 | fd4a04eb | ths | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
800 | fd4a04eb | ths | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
801 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
802 | fd4a04eb | ths | update_fcr31(); |
803 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
804 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
805 | fd4a04eb | ths | } |
806 | fd4a04eb | ths | FLOAT_OP(roundw, s) |
807 | fd4a04eb | ths | { |
808 | fd4a04eb | ths | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
809 | fd4a04eb | ths | WT2 = float32_round_to_int(FST0, &env->fp_status); |
810 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
811 | fd4a04eb | ths | update_fcr31(); |
812 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
813 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
814 | fd4a04eb | ths | } |
815 | fd4a04eb | ths | |
816 | fd4a04eb | ths | FLOAT_OP(truncl, d) |
817 | fd4a04eb | ths | { |
818 | fd4a04eb | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fp_status); |
819 | fd4a04eb | ths | update_fcr31(); |
820 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
821 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
822 | fd4a04eb | ths | } |
823 | fd4a04eb | ths | FLOAT_OP(truncl, s) |
824 | fd4a04eb | ths | { |
825 | fd4a04eb | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fp_status); |
826 | fd4a04eb | ths | update_fcr31(); |
827 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
828 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
829 | fd4a04eb | ths | } |
830 | fd4a04eb | ths | FLOAT_OP(truncw, d) |
831 | fd4a04eb | ths | { |
832 | fd4a04eb | ths | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); |
833 | fd4a04eb | ths | update_fcr31(); |
834 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
835 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
836 | fd4a04eb | ths | } |
837 | fd4a04eb | ths | FLOAT_OP(truncw, s) |
838 | fd4a04eb | ths | { |
839 | fd4a04eb | ths | WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); |
840 | fd4a04eb | ths | update_fcr31(); |
841 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
842 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
843 | fd4a04eb | ths | } |
844 | fd4a04eb | ths | |
845 | fd4a04eb | ths | FLOAT_OP(ceill, d) |
846 | fd4a04eb | ths | { |
847 | fd4a04eb | ths | set_float_rounding_mode(float_round_up, &env->fp_status); |
848 | fd4a04eb | ths | DT2 = float64_round_to_int(FDT0, &env->fp_status); |
849 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
850 | fd4a04eb | ths | update_fcr31(); |
851 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
852 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
853 | fd4a04eb | ths | } |
854 | fd4a04eb | ths | FLOAT_OP(ceill, s) |
855 | fd4a04eb | ths | { |
856 | fd4a04eb | ths | set_float_rounding_mode(float_round_up, &env->fp_status); |
857 | fd4a04eb | ths | DT2 = float32_round_to_int(FST0, &env->fp_status); |
858 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
859 | fd4a04eb | ths | update_fcr31(); |
860 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
861 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
862 | fd4a04eb | ths | } |
863 | fd4a04eb | ths | FLOAT_OP(ceilw, d) |
864 | fd4a04eb | ths | { |
865 | fd4a04eb | ths | set_float_rounding_mode(float_round_up, &env->fp_status); |
866 | fd4a04eb | ths | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
867 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
868 | fd4a04eb | ths | update_fcr31(); |
869 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
870 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
871 | fd4a04eb | ths | } |
872 | fd4a04eb | ths | FLOAT_OP(ceilw, s) |
873 | fd4a04eb | ths | { |
874 | fd4a04eb | ths | set_float_rounding_mode(float_round_up, &env->fp_status); |
875 | fd4a04eb | ths | WT2 = float32_round_to_int(FST0, &env->fp_status); |
876 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
877 | fd4a04eb | ths | update_fcr31(); |
878 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
879 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
880 | fd4a04eb | ths | } |
881 | fd4a04eb | ths | |
882 | fd4a04eb | ths | FLOAT_OP(floorl, d) |
883 | fd4a04eb | ths | { |
884 | fd4a04eb | ths | set_float_rounding_mode(float_round_down, &env->fp_status); |
885 | fd4a04eb | ths | DT2 = float64_round_to_int(FDT0, &env->fp_status); |
886 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
887 | fd4a04eb | ths | update_fcr31(); |
888 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
889 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
890 | fd4a04eb | ths | } |
891 | fd4a04eb | ths | FLOAT_OP(floorl, s) |
892 | fd4a04eb | ths | { |
893 | fd4a04eb | ths | set_float_rounding_mode(float_round_down, &env->fp_status); |
894 | fd4a04eb | ths | DT2 = float32_round_to_int(FST0, &env->fp_status); |
895 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
896 | fd4a04eb | ths | update_fcr31(); |
897 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
898 | fd4a04eb | ths | DT2 = 0x7fffffffffffffffULL;
|
899 | fd4a04eb | ths | } |
900 | fd4a04eb | ths | FLOAT_OP(floorw, d) |
901 | fd4a04eb | ths | { |
902 | fd4a04eb | ths | set_float_rounding_mode(float_round_down, &env->fp_status); |
903 | fd4a04eb | ths | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
904 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
905 | fd4a04eb | ths | update_fcr31(); |
906 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
907 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
908 | fd4a04eb | ths | } |
909 | fd4a04eb | ths | FLOAT_OP(floorw, s) |
910 | fd4a04eb | ths | { |
911 | fd4a04eb | ths | set_float_rounding_mode(float_round_down, &env->fp_status); |
912 | fd4a04eb | ths | WT2 = float32_round_to_int(FST0, &env->fp_status); |
913 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
914 | fd4a04eb | ths | update_fcr31(); |
915 | fd4a04eb | ths | if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
916 | fd4a04eb | ths | WT2 = 0x7fffffff;
|
917 | fd4a04eb | ths | } |
918 | fd4a04eb | ths | |
919 | 57fa1fb3 | ths | /* unary operations, MIPS specific, s and d */
|
920 | 57fa1fb3 | ths | #define FLOAT_UNOP(name) \
|
921 | 57fa1fb3 | ths | FLOAT_OP(name, d) \ |
922 | 57fa1fb3 | ths | { \ |
923 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
924 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
925 | 57fa1fb3 | ths | /* FDT2 = float64_ ## name (FDT0, &env->fp_status);*/ \
|
926 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
927 | 57fa1fb3 | ths | update_fcr31(); \ |
928 | 57fa1fb3 | ths | } \ |
929 | 57fa1fb3 | ths | FLOAT_OP(name, s) \ |
930 | 57fa1fb3 | ths | { \ |
931 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
932 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
933 | 57fa1fb3 | ths | /* FST2 = float32_ ## name (FST0, &env->fp_status);*/ \
|
934 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
935 | 57fa1fb3 | ths | update_fcr31(); \ |
936 | 57fa1fb3 | ths | } |
937 | 57fa1fb3 | ths | FLOAT_UNOP(rsqrt) |
938 | 57fa1fb3 | ths | FLOAT_UNOP(recip) |
939 | 57fa1fb3 | ths | #undef FLOAT_UNOP
|
940 | 57fa1fb3 | ths | |
941 | 57fa1fb3 | ths | /* unary operations, MIPS specific, s, d and ps */
|
942 | 57fa1fb3 | ths | #define FLOAT_UNOP(name) \
|
943 | 57fa1fb3 | ths | FLOAT_OP(name, d) \ |
944 | 57fa1fb3 | ths | { \ |
945 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
946 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
947 | 57fa1fb3 | ths | /* FDT2 = float64_ ## name (FDT0, &env->fp_status);*/ \
|
948 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
949 | 57fa1fb3 | ths | update_fcr31(); \ |
950 | 57fa1fb3 | ths | } \ |
951 | 57fa1fb3 | ths | FLOAT_OP(name, s) \ |
952 | 57fa1fb3 | ths | { \ |
953 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
954 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
955 | 57fa1fb3 | ths | /* FST2 = float32_ ## name (FST0, &env->fp_status);*/ \
|
956 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
957 | 57fa1fb3 | ths | update_fcr31(); \ |
958 | 57fa1fb3 | ths | } \ |
959 | 57fa1fb3 | ths | FLOAT_OP(name, ps) \ |
960 | 57fa1fb3 | ths | { \ |
961 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
962 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
963 | 57fa1fb3 | ths | /* FST2 = float32_ ## name (FST0, &env->fp_status);*/ \
|
964 | 57fa1fb3 | ths | /* FSTH2 = float32_ ## name (FSTH0, &env->fp_status);*/ \
|
965 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
966 | 57fa1fb3 | ths | update_fcr31(); \ |
967 | 57fa1fb3 | ths | } |
968 | 57fa1fb3 | ths | FLOAT_UNOP(rsqrt1) |
969 | 57fa1fb3 | ths | FLOAT_UNOP(recip1) |
970 | 57fa1fb3 | ths | #undef FLOAT_UNOP
|
971 | 57fa1fb3 | ths | |
972 | fd4a04eb | ths | /* binary operations */
|
973 | fd4a04eb | ths | #define FLOAT_BINOP(name) \
|
974 | fd4a04eb | ths | FLOAT_OP(name, d) \ |
975 | fd4a04eb | ths | { \ |
976 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status); \
|
977 | fd4a04eb | ths | FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ |
978 | 3a5b360d | ths | update_fcr31(); \ |
979 | 3a5b360d | ths | if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) \
|
980 | 3a5b360d | ths | FDT2 = 0x7ff7ffffffffffffULL; \
|
981 | 3a5b360d | ths | else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) { \ |
982 | 3a5b360d | ths | if ((env->fcr31 & 0x3) == 0) \ |
983 | 3a5b360d | ths | FDT2 &= 0x8000000000000000ULL; \
|
984 | 3a5b360d | ths | } \ |
985 | fd4a04eb | ths | } \ |
986 | fd4a04eb | ths | FLOAT_OP(name, s) \ |
987 | fd4a04eb | ths | { \ |
988 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status); \
|
989 | fd4a04eb | ths | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
990 | 3a5b360d | ths | update_fcr31(); \ |
991 | 3a5b360d | ths | if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) \
|
992 | 3a5b360d | ths | FST2 = 0x7fbfffff; \
|
993 | 3a5b360d | ths | else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) { \ |
994 | 3a5b360d | ths | if ((env->fcr31 & 0x3) == 0) \ |
995 | 3a5b360d | ths | FST2 &= 0x80000000ULL; \
|
996 | 3a5b360d | ths | } \ |
997 | fd4a04eb | ths | } \ |
998 | fd4a04eb | ths | FLOAT_OP(name, ps) \ |
999 | fd4a04eb | ths | { \ |
1000 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status); \
|
1001 | fd4a04eb | ths | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
1002 | fd4a04eb | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status); \ |
1003 | fd4a04eb | ths | update_fcr31(); \ |
1004 | 3a5b360d | ths | if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) { \
|
1005 | 3a5b360d | ths | FST2 = 0x7fbfffff; \
|
1006 | 3a5b360d | ths | FSTH2 = 0x7fbfffff; \
|
1007 | 3a5b360d | ths | } else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) { \ |
1008 | 3a5b360d | ths | if ((env->fcr31 & 0x3) == 0) { \ |
1009 | 3a5b360d | ths | FST2 &= 0x80000000ULL; \
|
1010 | 3a5b360d | ths | FSTH2 &= 0x80000000ULL; \
|
1011 | 3a5b360d | ths | } \ |
1012 | 3a5b360d | ths | } \ |
1013 | fd4a04eb | ths | } |
1014 | fd4a04eb | ths | FLOAT_BINOP(add) |
1015 | fd4a04eb | ths | FLOAT_BINOP(sub) |
1016 | fd4a04eb | ths | FLOAT_BINOP(mul) |
1017 | fd4a04eb | ths | FLOAT_BINOP(div) |
1018 | fd4a04eb | ths | #undef FLOAT_BINOP
|
1019 | fd4a04eb | ths | |
1020 | 57fa1fb3 | ths | /* binary operations, MIPS specific */
|
1021 | 57fa1fb3 | ths | #define FLOAT_BINOP(name) \
|
1022 | 57fa1fb3 | ths | FLOAT_OP(name, d) \ |
1023 | 57fa1fb3 | ths | { \ |
1024 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
1025 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
1026 | 57fa1fb3 | ths | /* FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);*/ \
|
1027 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
1028 | 57fa1fb3 | ths | update_fcr31(); \ |
1029 | 57fa1fb3 | ths | } \ |
1030 | 57fa1fb3 | ths | FLOAT_OP(name, s) \ |
1031 | 57fa1fb3 | ths | { \ |
1032 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
1033 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
1034 | 57fa1fb3 | ths | /* FST2 = float32_ ## name (FST0, FST1, &env->fp_status);*/ \
|
1035 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
1036 | 57fa1fb3 | ths | update_fcr31(); \ |
1037 | 57fa1fb3 | ths | } \ |
1038 | 57fa1fb3 | ths | FLOAT_OP(name, ps) \ |
1039 | 57fa1fb3 | ths | { \ |
1040 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status); \
|
1041 | 57fa1fb3 | ths | /* XXX: not implemented */ \
|
1042 | 57fa1fb3 | ths | /* FST2 = float32_ ## name (FST0, FST1, &env->fp_status);*/ \
|
1043 | 57fa1fb3 | ths | /* FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status);*/ \
|
1044 | 57fa1fb3 | ths | do_raise_exception(EXCP_RI); \ |
1045 | 57fa1fb3 | ths | update_fcr31(); \ |
1046 | 57fa1fb3 | ths | } |
1047 | 57fa1fb3 | ths | FLOAT_BINOP(rsqrt2) |
1048 | 57fa1fb3 | ths | FLOAT_BINOP(recip2) |
1049 | 57fa1fb3 | ths | #undef FLOAT_BINOP
|
1050 | 57fa1fb3 | ths | |
1051 | fd4a04eb | ths | FLOAT_OP(addr, ps) |
1052 | fd4a04eb | ths | { |
1053 | fd4a04eb | ths | set_float_exception_flags(0, &env->fp_status);
|
1054 | fd4a04eb | ths | FST2 = float32_add (FST0, FSTH0, &env->fp_status); |
1055 | fd4a04eb | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fp_status); |
1056 | fd4a04eb | ths | update_fcr31(); |
1057 | fd4a04eb | ths | } |
1058 | fd4a04eb | ths | |
1059 | 57fa1fb3 | ths | FLOAT_OP(mulr, ps) |
1060 | 57fa1fb3 | ths | { |
1061 | 57fa1fb3 | ths | set_float_exception_flags(0, &env->fp_status);
|
1062 | 57fa1fb3 | ths | FST2 = float32_mul (FST0, FSTH0, &env->fp_status); |
1063 | 57fa1fb3 | ths | FSTH2 = float32_mul (FST1, FSTH1, &env->fp_status); |
1064 | 57fa1fb3 | ths | update_fcr31(); |
1065 | 57fa1fb3 | ths | } |
1066 | 57fa1fb3 | ths | |
1067 | fd4a04eb | ths | #define FOP_COND_D(op, cond) \
|
1068 | fd4a04eb | ths | void do_cmp_d_ ## op (long cc) \ |
1069 | fd4a04eb | ths | { \ |
1070 | fd4a04eb | ths | int c = cond; \
|
1071 | fd4a04eb | ths | update_fcr31(); \ |
1072 | fd4a04eb | ths | if (c) \
|
1073 | fd4a04eb | ths | SET_FP_COND(cc, env); \ |
1074 | fd4a04eb | ths | else \
|
1075 | fd4a04eb | ths | CLEAR_FP_COND(cc, env); \ |
1076 | fd4a04eb | ths | } \ |
1077 | fd4a04eb | ths | void do_cmpabs_d_ ## op (long cc) \ |
1078 | fd4a04eb | ths | { \ |
1079 | fd4a04eb | ths | int c; \
|
1080 | fd4a04eb | ths | FDT0 &= ~(1ULL << 63); \ |
1081 | fd4a04eb | ths | FDT1 &= ~(1ULL << 63); \ |
1082 | fd4a04eb | ths | c = cond; \ |
1083 | fd4a04eb | ths | update_fcr31(); \ |
1084 | fd4a04eb | ths | if (c) \
|
1085 | fd4a04eb | ths | SET_FP_COND(cc, env); \ |
1086 | fd4a04eb | ths | else \
|
1087 | fd4a04eb | ths | CLEAR_FP_COND(cc, env); \ |
1088 | fd4a04eb | ths | } |
1089 | fd4a04eb | ths | |
1090 | fd4a04eb | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
1091 | fd4a04eb | ths | { |
1092 | fd4a04eb | ths | if (float64_is_signaling_nan(a) ||
|
1093 | fd4a04eb | ths | float64_is_signaling_nan(b) || |
1094 | fd4a04eb | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
1095 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1096 | fd4a04eb | ths | return 1; |
1097 | fd4a04eb | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
1098 | fd4a04eb | ths | return 1; |
1099 | fd4a04eb | ths | } else {
|
1100 | fd4a04eb | ths | return 0; |
1101 | fd4a04eb | ths | } |
1102 | fd4a04eb | ths | } |
1103 | fd4a04eb | ths | |
1104 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1105 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1106 | fd4a04eb | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fp_status), 0)) |
1107 | fd4a04eb | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fp_status))
|
1108 | fd4a04eb | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
|
1109 | fd4a04eb | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
1110 | fd4a04eb | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
|
1111 | fd4a04eb | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
1112 | fd4a04eb | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
|
1113 | fd4a04eb | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
1114 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1115 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1116 | fd4a04eb | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fp_status), 0)) |
1117 | fd4a04eb | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fp_status))
|
1118 | fd4a04eb | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
|
1119 | fd4a04eb | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
1120 | fd4a04eb | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
|
1121 | fd4a04eb | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
1122 | fd4a04eb | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
|
1123 | fd4a04eb | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
1124 | fd4a04eb | ths | |
1125 | fd4a04eb | ths | #define FOP_COND_S(op, cond) \
|
1126 | fd4a04eb | ths | void do_cmp_s_ ## op (long cc) \ |
1127 | fd4a04eb | ths | { \ |
1128 | fd4a04eb | ths | int c = cond; \
|
1129 | fd4a04eb | ths | update_fcr31(); \ |
1130 | fd4a04eb | ths | if (c) \
|
1131 | fd4a04eb | ths | SET_FP_COND(cc, env); \ |
1132 | fd4a04eb | ths | else \
|
1133 | fd4a04eb | ths | CLEAR_FP_COND(cc, env); \ |
1134 | fd4a04eb | ths | } \ |
1135 | fd4a04eb | ths | void do_cmpabs_s_ ## op (long cc) \ |
1136 | fd4a04eb | ths | { \ |
1137 | fd4a04eb | ths | int c; \
|
1138 | fd4a04eb | ths | FST0 &= ~(1 << 31); \ |
1139 | fd4a04eb | ths | FST1 &= ~(1 << 31); \ |
1140 | fd4a04eb | ths | c = cond; \ |
1141 | fd4a04eb | ths | update_fcr31(); \ |
1142 | fd4a04eb | ths | if (c) \
|
1143 | fd4a04eb | ths | SET_FP_COND(cc, env); \ |
1144 | fd4a04eb | ths | else \
|
1145 | fd4a04eb | ths | CLEAR_FP_COND(cc, env); \ |
1146 | fd4a04eb | ths | } |
1147 | fd4a04eb | ths | |
1148 | fd4a04eb | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
1149 | fd4a04eb | ths | { |
1150 | fd4a04eb | ths | extern flag float32_is_nan(float32 a);
|
1151 | fd4a04eb | ths | if (float32_is_signaling_nan(a) ||
|
1152 | fd4a04eb | ths | float32_is_signaling_nan(b) || |
1153 | fd4a04eb | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
1154 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1155 | fd4a04eb | ths | return 1; |
1156 | fd4a04eb | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
1157 | fd4a04eb | ths | return 1; |
1158 | fd4a04eb | ths | } else {
|
1159 | fd4a04eb | ths | return 0; |
1160 | fd4a04eb | ths | } |
1161 | fd4a04eb | ths | } |
1162 | fd4a04eb | ths | |
1163 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1164 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1165 | fd4a04eb | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0)) |
1166 | fd4a04eb | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fp_status))
|
1167 | fd4a04eb | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
|
1168 | fd4a04eb | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
1169 | fd4a04eb | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
|
1170 | fd4a04eb | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
1171 | fd4a04eb | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
|
1172 | fd4a04eb | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
1173 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1174 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1175 | fd4a04eb | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0)) |
1176 | fd4a04eb | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status))
|
1177 | fd4a04eb | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
|
1178 | fd4a04eb | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
1179 | fd4a04eb | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
|
1180 | fd4a04eb | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
1181 | fd4a04eb | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
|
1182 | fd4a04eb | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
1183 | fd4a04eb | ths | |
1184 | fd4a04eb | ths | #define FOP_COND_PS(op, condl, condh) \
|
1185 | fd4a04eb | ths | void do_cmp_ps_ ## op (long cc) \ |
1186 | fd4a04eb | ths | { \ |
1187 | fd4a04eb | ths | int cl = condl; \
|
1188 | fd4a04eb | ths | int ch = condh; \
|
1189 | fd4a04eb | ths | update_fcr31(); \ |
1190 | fd4a04eb | ths | if (cl) \
|
1191 | fd4a04eb | ths | SET_FP_COND(cc, env); \ |
1192 | fd4a04eb | ths | else \
|
1193 | fd4a04eb | ths | CLEAR_FP_COND(cc, env); \ |
1194 | fd4a04eb | ths | if (ch) \
|
1195 | fd4a04eb | ths | SET_FP_COND(cc + 1, env); \
|
1196 | fd4a04eb | ths | else \
|
1197 | fd4a04eb | ths | CLEAR_FP_COND(cc + 1, env); \
|
1198 | fd4a04eb | ths | } \ |
1199 | fd4a04eb | ths | void do_cmpabs_ps_ ## op (long cc) \ |
1200 | fd4a04eb | ths | { \ |
1201 | fd4a04eb | ths | int cl, ch; \
|
1202 | fd4a04eb | ths | FST0 &= ~(1 << 31); \ |
1203 | fd4a04eb | ths | FSTH0 &= ~(1 << 31); \ |
1204 | fd4a04eb | ths | FST1 &= ~(1 << 31); \ |
1205 | fd4a04eb | ths | FSTH1 &= ~(1 << 31); \ |
1206 | fd4a04eb | ths | cl = condl; \ |
1207 | fd4a04eb | ths | ch = condh; \ |
1208 | fd4a04eb | ths | update_fcr31(); \ |
1209 | fd4a04eb | ths | if (cl) \
|
1210 | fd4a04eb | ths | SET_FP_COND(cc, env); \ |
1211 | fd4a04eb | ths | else \
|
1212 | fd4a04eb | ths | CLEAR_FP_COND(cc, env); \ |
1213 | fd4a04eb | ths | if (ch) \
|
1214 | fd4a04eb | ths | SET_FP_COND(cc + 1, env); \
|
1215 | fd4a04eb | ths | else \
|
1216 | fd4a04eb | ths | CLEAR_FP_COND(cc + 1, env); \
|
1217 | fd4a04eb | ths | } |
1218 | fd4a04eb | ths | |
1219 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1220 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1221 | fd4a04eb | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0), |
1222 | fd4a04eb | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status), 0)) |
1223 | fd4a04eb | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fp_status),
|
1224 | fd4a04eb | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status))
|
1225 | fd4a04eb | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status),
|
1226 | fd4a04eb | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
|
1227 | fd4a04eb | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status),
|
1228 | fd4a04eb | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_eq(FSTH0, FSTH1, &env->fp_status))
|
1229 | fd4a04eb | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status),
|
1230 | fd4a04eb | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
|
1231 | fd4a04eb | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status),
|
1232 | fd4a04eb | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_lt(FSTH0, FSTH1, &env->fp_status))
|
1233 | fd4a04eb | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status),
|
1234 | fd4a04eb | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
|
1235 | fd4a04eb | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status),
|
1236 | fd4a04eb | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_le(FSTH0, FSTH1, &env->fp_status))
|
1237 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1238 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1239 | fd4a04eb | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0), |
1240 | fd4a04eb | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status), 0)) |
1241 | fd4a04eb | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status),
|
1242 | fd4a04eb | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status))
|
1243 | fd4a04eb | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status),
|
1244 | fd4a04eb | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
|
1245 | fd4a04eb | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status),
|
1246 | fd4a04eb | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_eq(FSTH0, FSTH1, &env->fp_status))
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1247 | fd4a04eb | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status),
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1248 | fd4a04eb | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
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1249 | fd4a04eb | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status),
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1250 | fd4a04eb | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_lt(FSTH0, FSTH1, &env->fp_status))
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1251 | fd4a04eb | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status),
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1252 | fd4a04eb | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
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1253 | fd4a04eb | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status),
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1254 | fd4a04eb | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_le(FSTH0, FSTH1, &env->fp_status)) |