Revision 12de9a39 target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 385 | 385 |
/* PowerPC Instructions types definitions */ |
| 386 | 386 |
enum {
|
| 387 | 387 |
PPC_NONE = 0x0000000000000000ULL, |
| 388 |
/* integer operations instructions */ |
|
| 389 |
/* flow control instructions */ |
|
| 390 |
/* virtual memory instructions */ |
|
| 391 |
/* ld/st with reservation instructions */ |
|
| 392 |
/* cache control instructions */ |
|
| 393 |
/* spr/msr access instructions */ |
|
| 388 |
/* PowerPC base instructions set */ |
|
| 394 | 389 |
PPC_INSNS_BASE = 0x0000000000000001ULL, |
| 390 |
/* integer operations instructions */ |
|
| 395 | 391 |
#define PPC_INTEGER PPC_INSNS_BASE |
| 392 |
/* flow control instructions */ |
|
| 396 | 393 |
#define PPC_FLOW PPC_INSNS_BASE |
| 394 |
/* virtual memory instructions */ |
|
| 397 | 395 |
#define PPC_MEM PPC_INSNS_BASE |
| 396 |
/* ld/st with reservation instructions */ |
|
| 398 | 397 |
#define PPC_RES PPC_INSNS_BASE |
| 398 |
/* cache control instructions */ |
|
| 399 | 399 |
#define PPC_CACHE PPC_INSNS_BASE |
| 400 |
/* spr/msr access instructions */ |
|
| 400 | 401 |
#define PPC_MISC PPC_INSNS_BASE |
| 401 |
/* Optional floating point instructions */ |
|
| 402 |
/* Optional floating point instructions */
|
|
| 402 | 403 |
PPC_FLOAT = 0x0000000000000002ULL, |
| 403 | 404 |
PPC_FLOAT_FSQRT = 0x0000000000000004ULL, |
| 404 | 405 |
PPC_FLOAT_FRES = 0x0000000000000008ULL, |
| 405 | 406 |
PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL, |
| 406 | 407 |
PPC_FLOAT_FSEL = 0x0000000000000020ULL, |
| 407 | 408 |
PPC_FLOAT_STFIWX = 0x0000000000000040ULL, |
| 408 |
/* external control instructions */ |
|
| 409 |
/* external control instructions */
|
|
| 409 | 410 |
PPC_EXTERN = 0x0000000000000080ULL, |
| 410 |
/* segment register access instructions */ |
|
| 411 |
/* segment register access instructions */
|
|
| 411 | 412 |
PPC_SEGMENT = 0x0000000000000100ULL, |
| 412 |
/* Optional cache control instruction */ |
|
| 413 |
/* Optional cache control instruction */
|
|
| 413 | 414 |
PPC_CACHE_DCBA = 0x0000000000000200ULL, |
| 414 |
/* Optional memory control instructions */ |
|
| 415 |
/* Optional memory control instructions */
|
|
| 415 | 416 |
PPC_MEM_TLBIA = 0x0000000000000400ULL, |
| 416 | 417 |
PPC_MEM_TLBIE = 0x0000000000000800ULL, |
| 417 | 418 |
PPC_MEM_TLBSYNC = 0x0000000000001000ULL, |
| 418 |
/* eieio & sync */ |
|
| 419 |
/* eieio & sync */
|
|
| 419 | 420 |
PPC_MEM_SYNC = 0x0000000000002000ULL, |
| 420 |
/* PowerPC 6xx TLB management instructions */ |
|
| 421 |
/* PowerPC 6xx TLB management instructions */
|
|
| 421 | 422 |
PPC_6xx_TLB = 0x0000000000004000ULL, |
| 422 |
/* Altivec support */ |
|
| 423 |
/* Altivec support */
|
|
| 423 | 424 |
PPC_ALTIVEC = 0x0000000000008000ULL, |
| 424 |
/* Time base mftb instruction */ |
|
| 425 |
/* Time base mftb instruction */
|
|
| 425 | 426 |
PPC_MFTB = 0x0000000000010000ULL, |
| 426 |
/* Embedded PowerPC dedicated instructions */ |
|
| 427 |
/* Embedded PowerPC dedicated instructions */
|
|
| 427 | 428 |
PPC_EMB_COMMON = 0x0000000000020000ULL, |
| 428 |
/* PowerPC 40x exception model */ |
|
| 429 |
/* PowerPC 40x exception model */
|
|
| 429 | 430 |
PPC_40x_EXCP = 0x0000000000040000ULL, |
| 430 |
/* PowerPC 40x TLB management instructions */ |
|
| 431 |
/* PowerPC 40x TLB management instructions */
|
|
| 431 | 432 |
PPC_40x_TLB = 0x0000000000080000ULL, |
| 432 |
/* PowerPC 405 Mac instructions */ |
|
| 433 |
/* PowerPC 405 Mac instructions */
|
|
| 433 | 434 |
PPC_405_MAC = 0x0000000000100000ULL, |
| 434 |
/* PowerPC 440 specific instructions */ |
|
| 435 |
/* PowerPC 440 specific instructions */
|
|
| 435 | 436 |
PPC_440_SPEC = 0x0000000000200000ULL, |
| 436 |
/* Power-to-PowerPC bridge (601) */ |
|
| 437 |
/* Power-to-PowerPC bridge (601) */
|
|
| 437 | 438 |
PPC_POWER_BR = 0x0000000000400000ULL, |
| 438 |
/* PowerPC 602 specific */ |
|
| 439 |
/* PowerPC 602 specific */
|
|
| 439 | 440 |
PPC_602_SPEC = 0x0000000000800000ULL, |
| 440 |
/* Deprecated instructions */ |
|
| 441 |
/* Original POWER instruction set */ |
|
| 441 |
/* Deprecated instructions */
|
|
| 442 |
/* Original POWER instruction set */
|
|
| 442 | 443 |
PPC_POWER = 0x0000000001000000ULL, |
| 443 |
/* POWER2 instruction set extension */ |
|
| 444 |
/* POWER2 instruction set extension */
|
|
| 444 | 445 |
PPC_POWER2 = 0x0000000002000000ULL, |
| 445 |
/* Power RTC support */ |
|
| 446 |
/* Power RTC support */
|
|
| 446 | 447 |
PPC_POWER_RTC = 0x0000000004000000ULL, |
| 447 |
/* 64 bits PowerPC instructions */ |
|
| 448 |
/* 64 bits PowerPC instruction set */ |
|
| 448 |
/* 64 bits PowerPC instruction set */ |
|
| 449 | 449 |
PPC_64B = 0x0000000008000000ULL, |
| 450 |
/* 64 bits hypervisor extensions */ |
|
| 450 |
/* 64 bits hypervisor extensions */
|
|
| 451 | 451 |
PPC_64H = 0x0000000010000000ULL, |
| 452 |
/* 64 bits PowerPC "bridge" features */
|
|
| 453 |
PPC_64_BRIDGE = 0x0000000020000000ULL,
|
|
| 454 |
/* BookE (embedded) PowerPC specification */ |
|
| 452 |
/* segment register access instructions for PowerPC 64 "bridge" */
|
|
| 453 |
PPC_SEGMENT_64B = 0x0000000020000000ULL,
|
|
| 454 |
/* BookE (embedded) PowerPC specification */
|
|
| 455 | 455 |
PPC_BOOKE = 0x0000000040000000ULL, |
| 456 |
/* eieio */ |
|
| 456 |
/* eieio */
|
|
| 457 | 457 |
PPC_MEM_EIEIO = 0x0000000080000000ULL, |
| 458 |
/* e500 vector instructions */ |
|
| 458 |
/* e500 vector instructions */
|
|
| 459 | 459 |
PPC_E500_VECTOR = 0x0000000100000000ULL, |
| 460 |
/* PowerPC 4xx dedicated instructions */ |
|
| 460 |
/* PowerPC 4xx dedicated instructions */
|
|
| 461 | 461 |
PPC_4xx_COMMON = 0x0000000200000000ULL, |
| 462 |
/* PowerPC 2.03 specification extensions */ |
|
| 462 |
/* PowerPC 2.03 specification extensions */
|
|
| 463 | 463 |
PPC_203 = 0x0000000400000000ULL, |
| 464 |
/* PowerPC 2.03 SPE extension */ |
|
| 464 |
/* PowerPC 2.03 SPE extension */
|
|
| 465 | 465 |
PPC_SPE = 0x0000000800000000ULL, |
| 466 |
/* PowerPC 2.03 SPE floating-point extension */ |
|
| 466 |
/* PowerPC 2.03 SPE floating-point extension */
|
|
| 467 | 467 |
PPC_SPEFPU = 0x0000001000000000ULL, |
| 468 |
/* SLB management */ |
|
| 468 |
/* SLB management */
|
|
| 469 | 469 |
PPC_SLBI = 0x0000002000000000ULL, |
| 470 |
/* PowerPC 40x ibct instructions */ |
|
| 470 |
/* PowerPC 40x ibct instructions */
|
|
| 471 | 471 |
PPC_40x_ICBT = 0x0000004000000000ULL, |
| 472 |
/* PowerPC 74xx TLB management instructions */ |
|
| 472 |
/* PowerPC 74xx TLB management instructions */
|
|
| 473 | 473 |
PPC_74xx_TLB = 0x0000008000000000ULL, |
| 474 |
/* More BookE (embedded) instructions... */ |
|
| 474 |
/* More BookE (embedded) instructions... */
|
|
| 475 | 475 |
PPC_BOOKE_EXT = 0x0000010000000000ULL, |
| 476 |
/* rfmci is not implemented in all BookE PowerPC */ |
|
| 476 |
/* rfmci is not implemented in all BookE PowerPC */
|
|
| 477 | 477 |
PPC_RFMCI = 0x0000020000000000ULL, |
| 478 |
/* user-mode DCR access, implemented in PowerPC 460 */ |
|
| 478 |
/* user-mode DCR access, implemented in PowerPC 460 */
|
|
| 479 | 479 |
PPC_DCRUX = 0x0000040000000000ULL, |
| 480 |
/* New floating-point extensions (PowerPC 2.0x) */ |
|
| 480 |
/* New floating-point extensions (PowerPC 2.0x) */
|
|
| 481 | 481 |
PPC_FLOAT_EXT = 0x0000080000000000ULL, |
| 482 |
/* New wait instruction (PowerPC 2.0x) */ |
|
| 482 |
/* New wait instruction (PowerPC 2.0x) */
|
|
| 483 | 483 |
PPC_WAIT = 0x0000100000000000ULL, |
| 484 |
/* New 64 bits extensions (PowerPC 2.0x) */ |
|
| 484 |
/* New 64 bits extensions (PowerPC 2.0x) */
|
|
| 485 | 485 |
PPC_64BX = 0x0000200000000000ULL, |
| 486 |
/* dcbz instruction with fixed cache line size */ |
|
| 486 |
/* dcbz instruction with fixed cache line size */
|
|
| 487 | 487 |
PPC_CACHE_DCBZ = 0x0000400000000000ULL, |
| 488 |
/* dcbz instruction with tunable cache line size */ |
|
| 488 |
/* dcbz instruction with tunable cache line size */
|
|
| 489 | 489 |
PPC_CACHE_DCBZT = 0x0000800000000000ULL, |
| 490 | 490 |
}; |
| 491 | 491 |
|
| ... | ... | |
| 3931 | 3931 |
#endif |
| 3932 | 3932 |
} |
| 3933 | 3933 |
|
| 3934 |
#if defined(TARGET_PPC64) |
|
| 3935 |
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ |
|
| 3936 |
/* mfsr */ |
|
| 3937 |
GEN_HANDLER(mfsr_64b, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) |
|
| 3938 |
{
|
|
| 3939 |
#if defined(CONFIG_USER_ONLY) |
|
| 3940 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3941 |
#else |
|
| 3942 |
if (unlikely(!ctx->supervisor)) {
|
|
| 3943 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3944 |
return; |
|
| 3945 |
} |
|
| 3946 |
gen_op_set_T1(SR(ctx->opcode)); |
|
| 3947 |
gen_op_load_slb(); |
|
| 3948 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
|
| 3949 |
#endif |
|
| 3950 |
} |
|
| 3951 |
|
|
| 3952 |
/* mfsrin */ |
|
| 3953 |
GEN_HANDLER(mfsrin_64b, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT_64B) |
|
| 3954 |
{
|
|
| 3955 |
#if defined(CONFIG_USER_ONLY) |
|
| 3956 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3957 |
#else |
|
| 3958 |
if (unlikely(!ctx->supervisor)) {
|
|
| 3959 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3960 |
return; |
|
| 3961 |
} |
|
| 3962 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
|
| 3963 |
gen_op_srli_T1(28); |
|
| 3964 |
gen_op_load_slb(); |
|
| 3965 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
|
| 3966 |
#endif |
|
| 3967 |
} |
|
| 3968 |
|
|
| 3969 |
/* mtsr */ |
|
| 3970 |
GEN_HANDLER(mtsr_64b, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) |
|
| 3971 |
{
|
|
| 3972 |
#if defined(CONFIG_USER_ONLY) |
|
| 3973 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3974 |
#else |
|
| 3975 |
if (unlikely(!ctx->supervisor)) {
|
|
| 3976 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3977 |
return; |
|
| 3978 |
} |
|
| 3979 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
|
| 3980 |
gen_op_set_T1(SR(ctx->opcode)); |
|
| 3981 |
gen_op_store_slb(); |
|
| 3982 |
#endif |
|
| 3983 |
} |
|
| 3984 |
|
|
| 3985 |
/* mtsrin */ |
|
| 3986 |
GEN_HANDLER(mtsrin_64b, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B) |
|
| 3987 |
{
|
|
| 3988 |
#if defined(CONFIG_USER_ONLY) |
|
| 3989 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3990 |
#else |
|
| 3991 |
if (unlikely(!ctx->supervisor)) {
|
|
| 3992 |
GEN_EXCP_PRIVREG(ctx); |
|
| 3993 |
return; |
|
| 3994 |
} |
|
| 3995 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
|
| 3996 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
|
| 3997 |
gen_op_srli_T1(28); |
|
| 3998 |
gen_op_store_slb(); |
|
| 3999 |
#endif |
|
| 4000 |
} |
|
| 4001 |
#endif /* defined(TARGET_PPC64) */ |
|
| 4002 |
|
|
| 3934 | 4003 |
/*** Lookaside buffer management ***/ |
| 3935 | 4004 |
/* Optional & supervisor only: */ |
| 3936 | 4005 |
/* tlbia */ |
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