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Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
msix: convert to memory API
The msix table is defined as a subregion, to allow for a BAR thatmixes device specific regions with the msix table.
Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Avi Kivity <avi@redhat.com>...
msix: use specific endian ld/st_phys
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Merge remote-tracking branch 'origin/master' into pci
Conflicts: hw/virtio-pci.c
msix: Use replace local defines with pci_regs versions
This also cleans up an open-coded 64-bit message address readout.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fix typo in code and comments
Replace writeable -> writable
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
msix: simplify write config
use pci_device_deassert_intx().
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. Thetarget endianness is not of their concern, so we need to push thingsdown a level.
This patch adds a parameter to cpu_register_io_memory that allows adevice to choose its endianness. For now, all devices simply choose...
Merge branch 'pci' into for_anthony
msix: clear not only INTA, but all INTx when MSI-X is enabled.
clear not only INTA, but all INTx when MSI-X is enabled.
Introduce range.h
Extract range functions from pci.h. These will be used by later patchesby non-PCI devices. Adjust current users.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
pci: consolidate pci_add_capability_at_offset() into pci_add_capability().
By making pci_add_capability() the special case ofpci_add_capability_at_offset() of offset = 0,consolidate pci_add_capability_at_offset() into pci_add_capability().
Cc: Stefan Weil <weil@mail.berlios.de>...
Remove unused DEBUG defines from hw/msix.c
Remove unused DEBUG defines from hw/msix.c to avoid having anythingdefine the word DEBUG without any additions such as MSIX_DEBUG.
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
msix: remove duplicated defines.
remove defines which are already defined in pci_regs.h
msix: use range helper function.
use range helper function in msix_write_config().
msix: function mask support
Function mask is a mandatory feature in MSIXspec so not implementing it is a spec violation.Implement.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
msix: macro rename for function mask support
rename ENABLE_OFFSET -> CONTROL_OFFSET, sincesame byte includes function mask.This is in preparation for function mask support.
msix: clear pending bit of an unused vector
PCI spec states:if a masked vector has its Pending bit set, and the associatedunderlying interrupt events are somehow satisfied (usually by softwarethough the exact manner is function-specific), the function must clear...
msix: fix reset value for enable bit
On reset, we currently clear all bits in msix control register exceptenable bit. This is wrong: the spec says we should clear writeablebits: function mask and enable bit.Correct this.
msix: fix mask bit state after reset
PCI spec states that mask bit must be 1 after reset.Make it so.
msix: add helper to unuse all msix entries
will be used by virtio on soft reset
pci: introduce pcibus_t to represent pci bus address/size instead of uint32_t
This patch is preliminary for 64 bit BAR support.Introduce dedicated type, pcibus_t, to represent pci bus address/sizeinstead of uint32_t.Later this type will be changed to uint64_t....
qemu/msix: fix table access issues
Fixes a couple of issues with msix table access:- With misbehaving guests, misaligned 4 byte access could overflow msix table and cause qemu to segfault. Since PCI spec requires host to only issue dword-aligned accesses, as a fix,...
qemu: clean up target page usage in msix
Since cpu_register_phys_memory does not require size to be a multiple oftarget page size, simply make msix page size 0x1000. Do this in msix,reverting part of 5e520a7d500ec2569d22d80f9ef4272a34cb3c80, as we nolonger have to pass target page around....
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Compile msix only once
Get page size in device init.
Make CPURead/WriteFunc structure 'const'
qemu: msix nit: clear msix_entries_nr on error
I don't think it's critical to do this, but it'sbest to keep uninit and error recovery consistent.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
qemu/msi: clean used vectors state on load
Clean up msix vector usage state on load. Since guest might have controlover it through the device, the device will have to load this state fromfile.
qemu/msi: missing braces
MSIX present bit is tested incorrectly, and only happens to work becausethe bit we are testing is 0x1. Add braces to fix this.
Reported-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
fix segfault in msix_save
This fixes segfault reported by Kevin Wolf,and simplifies the code in msix_save.
Reported-by: Kevin Wolf <kwolf@redhat.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Fix Sparse warning
qemu/pci: MSI-X support functions
Add functions implementing MSI-X support. First user will be virtio-pci.Note that platform must set a flag to declare MSI supported: thisis a safety measure to avoid breaking platforms which should supportMSI-X but currently lack this in the interrupt controller emulation....