root / target-arm / op_helper.c @ 1497c961
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1 | b7bcbe95 | bellard | /*
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2 | b7bcbe95 | bellard | * ARM helper routines
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3 | 5fafdf24 | ths | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2005-2007 CodeSourcery, LLC
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5 | b7bcbe95 | bellard | *
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6 | b7bcbe95 | bellard | * This library is free software; you can redistribute it and/or
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7 | b7bcbe95 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | b7bcbe95 | bellard | * License as published by the Free Software Foundation; either
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9 | b7bcbe95 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | b7bcbe95 | bellard | *
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11 | b7bcbe95 | bellard | * This library is distributed in the hope that it will be useful,
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12 | b7bcbe95 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b7bcbe95 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b7bcbe95 | bellard | * Lesser General Public License for more details.
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15 | b7bcbe95 | bellard | *
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16 | b7bcbe95 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | b7bcbe95 | bellard | * License along with this library; if not, write to the Free Software
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18 | b7bcbe95 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | b7bcbe95 | bellard | */
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20 | b7bcbe95 | bellard | #include "exec.h" |
21 | 1497c961 | pbrook | #include "helpers.h" |
22 | b7bcbe95 | bellard | |
23 | b7bcbe95 | bellard | void raise_exception(int tt) |
24 | b7bcbe95 | bellard | { |
25 | b7bcbe95 | bellard | env->exception_index = tt; |
26 | b7bcbe95 | bellard | cpu_loop_exit(); |
27 | b7bcbe95 | bellard | } |
28 | b7bcbe95 | bellard | |
29 | b7bcbe95 | bellard | /* thread support */
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30 | b7bcbe95 | bellard | |
31 | b7bcbe95 | bellard | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
32 | b7bcbe95 | bellard | |
33 | b7bcbe95 | bellard | void cpu_lock(void) |
34 | b7bcbe95 | bellard | { |
35 | b7bcbe95 | bellard | spin_lock(&global_cpu_lock); |
36 | b7bcbe95 | bellard | } |
37 | b7bcbe95 | bellard | |
38 | b7bcbe95 | bellard | void cpu_unlock(void) |
39 | b7bcbe95 | bellard | { |
40 | b7bcbe95 | bellard | spin_unlock(&global_cpu_lock); |
41 | b7bcbe95 | bellard | } |
42 | b7bcbe95 | bellard | |
43 | b7bcbe95 | bellard | /* VFP support. */
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44 | b7bcbe95 | bellard | |
45 | b7bcbe95 | bellard | void do_vfp_abss(void) |
46 | b7bcbe95 | bellard | { |
47 | 53cd6637 | bellard | FT0s = float32_abs(FT0s); |
48 | b7bcbe95 | bellard | } |
49 | b7bcbe95 | bellard | |
50 | b7bcbe95 | bellard | void do_vfp_absd(void) |
51 | b7bcbe95 | bellard | { |
52 | 53cd6637 | bellard | FT0d = float64_abs(FT0d); |
53 | b7bcbe95 | bellard | } |
54 | b7bcbe95 | bellard | |
55 | b7bcbe95 | bellard | void do_vfp_sqrts(void) |
56 | b7bcbe95 | bellard | { |
57 | 53cd6637 | bellard | FT0s = float32_sqrt(FT0s, &env->vfp.fp_status); |
58 | b7bcbe95 | bellard | } |
59 | b7bcbe95 | bellard | |
60 | b7bcbe95 | bellard | void do_vfp_sqrtd(void) |
61 | b7bcbe95 | bellard | { |
62 | 53cd6637 | bellard | FT0d = float64_sqrt(FT0d, &env->vfp.fp_status); |
63 | b7bcbe95 | bellard | } |
64 | b7bcbe95 | bellard | |
65 | 53cd6637 | bellard | /* XXX: check quiet/signaling case */
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66 | 53cd6637 | bellard | #define DO_VFP_cmp(p, size) \
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67 | b7bcbe95 | bellard | void do_vfp_cmp##p(void) \ |
68 | b7bcbe95 | bellard | { \ |
69 | b7bcbe95 | bellard | uint32_t flags; \ |
70 | 53cd6637 | bellard | switch(float ## size ## _compare_quiet(FT0##p, FT1##p, &env->vfp.fp_status)) {\ |
71 | 89344d5a | bellard | case 0: flags = 0x6; break;\ |
72 | 53cd6637 | bellard | case -1: flags = 0x8; break;\ |
73 | 53cd6637 | bellard | case 1: flags = 0x2; break;\ |
74 | 53cd6637 | bellard | default: case 2: flags = 0x3; break;\ |
75 | 53cd6637 | bellard | }\ |
76 | 40f137e1 | pbrook | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
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77 | 40f137e1 | pbrook | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
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78 | b7bcbe95 | bellard | FORCE_RET(); \ |
79 | 53cd6637 | bellard | }\ |
80 | 53cd6637 | bellard | \ |
81 | b7bcbe95 | bellard | void do_vfp_cmpe##p(void) \ |
82 | b7bcbe95 | bellard | { \ |
83 | 53cd6637 | bellard | uint32_t flags; \ |
84 | 53cd6637 | bellard | switch(float ## size ## _compare(FT0##p, FT1##p, &env->vfp.fp_status)) {\ |
85 | 89344d5a | bellard | case 0: flags = 0x6; break;\ |
86 | 53cd6637 | bellard | case -1: flags = 0x8; break;\ |
87 | 53cd6637 | bellard | case 1: flags = 0x2; break;\ |
88 | 53cd6637 | bellard | default: case 2: flags = 0x3; break;\ |
89 | 53cd6637 | bellard | }\ |
90 | 40f137e1 | pbrook | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
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91 | 40f137e1 | pbrook | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
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92 | 53cd6637 | bellard | FORCE_RET(); \ |
93 | b7bcbe95 | bellard | } |
94 | 53cd6637 | bellard | DO_VFP_cmp(s, 32)
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95 | 53cd6637 | bellard | DO_VFP_cmp(d, 64)
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96 | 53cd6637 | bellard | #undef DO_VFP_cmp
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97 | b7bcbe95 | bellard | |
98 | b7bcbe95 | bellard | /* Convert host exception flags to vfp form. */
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99 | 53cd6637 | bellard | static inline int vfp_exceptbits_from_host(int host_bits) |
100 | b7bcbe95 | bellard | { |
101 | b7bcbe95 | bellard | int target_bits = 0; |
102 | b7bcbe95 | bellard | |
103 | 53cd6637 | bellard | if (host_bits & float_flag_invalid)
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104 | b7bcbe95 | bellard | target_bits |= 1;
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105 | 53cd6637 | bellard | if (host_bits & float_flag_divbyzero)
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106 | b7bcbe95 | bellard | target_bits |= 2;
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107 | 53cd6637 | bellard | if (host_bits & float_flag_overflow)
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108 | b7bcbe95 | bellard | target_bits |= 4;
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109 | 53cd6637 | bellard | if (host_bits & float_flag_underflow)
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110 | b7bcbe95 | bellard | target_bits |= 8;
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111 | 53cd6637 | bellard | if (host_bits & float_flag_inexact)
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112 | b7bcbe95 | bellard | target_bits |= 0x10;
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113 | b7bcbe95 | bellard | return target_bits;
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114 | b7bcbe95 | bellard | } |
115 | b7bcbe95 | bellard | |
116 | b7bcbe95 | bellard | /* Convert vfp exception flags to target form. */
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117 | 53cd6637 | bellard | static inline int vfp_exceptbits_to_host(int target_bits) |
118 | b7bcbe95 | bellard | { |
119 | b7bcbe95 | bellard | int host_bits = 0; |
120 | b7bcbe95 | bellard | |
121 | b7bcbe95 | bellard | if (target_bits & 1) |
122 | 53cd6637 | bellard | host_bits |= float_flag_invalid; |
123 | b7bcbe95 | bellard | if (target_bits & 2) |
124 | 53cd6637 | bellard | host_bits |= float_flag_divbyzero; |
125 | b7bcbe95 | bellard | if (target_bits & 4) |
126 | 53cd6637 | bellard | host_bits |= float_flag_overflow; |
127 | b7bcbe95 | bellard | if (target_bits & 8) |
128 | 53cd6637 | bellard | host_bits |= float_flag_underflow; |
129 | b7bcbe95 | bellard | if (target_bits & 0x10) |
130 | 53cd6637 | bellard | host_bits |= float_flag_inexact; |
131 | b7bcbe95 | bellard | return host_bits;
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132 | b7bcbe95 | bellard | } |
133 | b7bcbe95 | bellard | |
134 | b7bcbe95 | bellard | void do_vfp_set_fpscr(void) |
135 | b7bcbe95 | bellard | { |
136 | b7bcbe95 | bellard | int i;
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137 | b7bcbe95 | bellard | uint32_t changed; |
138 | b7bcbe95 | bellard | |
139 | 40f137e1 | pbrook | changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
140 | 40f137e1 | pbrook | env->vfp.xregs[ARM_VFP_FPSCR] = (T0 & 0xffc8ffff);
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141 | b7bcbe95 | bellard | env->vfp.vec_len = (T0 >> 16) & 7; |
142 | b7bcbe95 | bellard | env->vfp.vec_stride = (T0 >> 20) & 3; |
143 | b7bcbe95 | bellard | |
144 | b7bcbe95 | bellard | changed ^= T0; |
145 | b7bcbe95 | bellard | if (changed & (3 << 22)) { |
146 | b7bcbe95 | bellard | i = (T0 >> 22) & 3; |
147 | b7bcbe95 | bellard | switch (i) {
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148 | b7bcbe95 | bellard | case 0: |
149 | 53cd6637 | bellard | i = float_round_nearest_even; |
150 | b7bcbe95 | bellard | break;
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151 | b7bcbe95 | bellard | case 1: |
152 | 53cd6637 | bellard | i = float_round_up; |
153 | b7bcbe95 | bellard | break;
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154 | b7bcbe95 | bellard | case 2: |
155 | 53cd6637 | bellard | i = float_round_down; |
156 | b7bcbe95 | bellard | break;
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157 | b7bcbe95 | bellard | case 3: |
158 | 53cd6637 | bellard | i = float_round_to_zero; |
159 | b7bcbe95 | bellard | break;
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160 | b7bcbe95 | bellard | } |
161 | 53cd6637 | bellard | set_float_rounding_mode(i, &env->vfp.fp_status); |
162 | b7bcbe95 | bellard | } |
163 | b7bcbe95 | bellard | |
164 | 53cd6637 | bellard | i = vfp_exceptbits_to_host((T0 >> 8) & 0x1f); |
165 | 53cd6637 | bellard | set_float_exception_flags(i, &env->vfp.fp_status); |
166 | b7bcbe95 | bellard | /* XXX: FZ and DN are not implemented. */
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167 | b7bcbe95 | bellard | } |
168 | b7bcbe95 | bellard | |
169 | b7bcbe95 | bellard | void do_vfp_get_fpscr(void) |
170 | b7bcbe95 | bellard | { |
171 | b7bcbe95 | bellard | int i;
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172 | b7bcbe95 | bellard | |
173 | 40f137e1 | pbrook | T0 = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | (env->vfp.vec_len << 16) |
174 | b7bcbe95 | bellard | | (env->vfp.vec_stride << 20);
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175 | 53cd6637 | bellard | i = get_float_exception_flags(&env->vfp.fp_status); |
176 | b7bcbe95 | bellard | T0 |= vfp_exceptbits_from_host(i); |
177 | b7bcbe95 | bellard | } |
178 | b5ff1b31 | bellard | |
179 | 9ee6e8bb | pbrook | float32 helper_recps_f32(float32 a, float32 b) |
180 | 9ee6e8bb | pbrook | { |
181 | 9ee6e8bb | pbrook | float_status *s = &env->vfp.fp_status; |
182 | 9ee6e8bb | pbrook | float32 two = int32_to_float32(2, s);
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183 | 9ee6e8bb | pbrook | return float32_sub(two, float32_mul(a, b, s), s);
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184 | 9ee6e8bb | pbrook | } |
185 | 9ee6e8bb | pbrook | |
186 | 9ee6e8bb | pbrook | float32 helper_rsqrts_f32(float32 a, float32 b) |
187 | 9ee6e8bb | pbrook | { |
188 | 9ee6e8bb | pbrook | float_status *s = &env->vfp.fp_status; |
189 | 9ee6e8bb | pbrook | float32 three = int32_to_float32(3, s);
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190 | 9ee6e8bb | pbrook | return float32_sub(three, float32_mul(a, b, s), s);
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191 | 9ee6e8bb | pbrook | } |
192 | 9ee6e8bb | pbrook | |
193 | 9ee6e8bb | pbrook | /* TODO: The architecture specifies the value that the estimate functions
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194 | 9ee6e8bb | pbrook | should return. We return the exact reciprocal/root instead. */
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195 | 9ee6e8bb | pbrook | float32 helper_recpe_f32(float32 a) |
196 | 9ee6e8bb | pbrook | { |
197 | 9ee6e8bb | pbrook | float_status *s = &env->vfp.fp_status; |
198 | 9ee6e8bb | pbrook | float32 one = int32_to_float32(1, s);
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199 | 9ee6e8bb | pbrook | return float32_div(one, a, s);
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200 | 9ee6e8bb | pbrook | } |
201 | 9ee6e8bb | pbrook | |
202 | 9ee6e8bb | pbrook | float32 helper_rsqrte_f32(float32 a) |
203 | 9ee6e8bb | pbrook | { |
204 | 9ee6e8bb | pbrook | float_status *s = &env->vfp.fp_status; |
205 | 9ee6e8bb | pbrook | float32 one = int32_to_float32(1, s);
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206 | 9ee6e8bb | pbrook | return float32_div(one, float32_sqrt(a, s), s);
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207 | 9ee6e8bb | pbrook | } |
208 | 9ee6e8bb | pbrook | |
209 | 9ee6e8bb | pbrook | uint32_t helper_recpe_u32(uint32_t a) |
210 | 9ee6e8bb | pbrook | { |
211 | 9ee6e8bb | pbrook | float_status *s = &env->vfp.fp_status; |
212 | 9ee6e8bb | pbrook | float32 tmp; |
213 | 9ee6e8bb | pbrook | tmp = int32_to_float32(a, s); |
214 | 9ee6e8bb | pbrook | tmp = float32_scalbn(tmp, -32, s);
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215 | 9ee6e8bb | pbrook | tmp = helper_recpe_f32(tmp); |
216 | 9ee6e8bb | pbrook | tmp = float32_scalbn(tmp, 31, s);
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217 | 9ee6e8bb | pbrook | return float32_to_int32(tmp, s);
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218 | 9ee6e8bb | pbrook | } |
219 | 9ee6e8bb | pbrook | |
220 | 9ee6e8bb | pbrook | uint32_t helper_rsqrte_u32(uint32_t a) |
221 | 9ee6e8bb | pbrook | { |
222 | 9ee6e8bb | pbrook | float_status *s = &env->vfp.fp_status; |
223 | 9ee6e8bb | pbrook | float32 tmp; |
224 | 9ee6e8bb | pbrook | tmp = int32_to_float32(a, s); |
225 | 9ee6e8bb | pbrook | tmp = float32_scalbn(tmp, -32, s);
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226 | 9ee6e8bb | pbrook | tmp = helper_rsqrte_f32(tmp); |
227 | 9ee6e8bb | pbrook | tmp = float32_scalbn(tmp, 31, s);
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228 | 9ee6e8bb | pbrook | return float32_to_int32(tmp, s);
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229 | 9ee6e8bb | pbrook | } |
230 | 9ee6e8bb | pbrook | |
231 | 9ee6e8bb | pbrook | void helper_neon_tbl(int rn, int maxindex) |
232 | 9ee6e8bb | pbrook | { |
233 | 9ee6e8bb | pbrook | uint32_t val; |
234 | 9ee6e8bb | pbrook | uint32_t mask; |
235 | 9ee6e8bb | pbrook | uint32_t tmp; |
236 | 9ee6e8bb | pbrook | int index;
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237 | 9ee6e8bb | pbrook | int shift;
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238 | 9ee6e8bb | pbrook | uint64_t *table; |
239 | 9ee6e8bb | pbrook | table = (uint64_t *)&env->vfp.regs[rn]; |
240 | 9ee6e8bb | pbrook | val = 0;
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241 | 9ee6e8bb | pbrook | mask = 0;
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242 | 9ee6e8bb | pbrook | for (shift = 0; shift < 32; shift += 8) { |
243 | 9ee6e8bb | pbrook | index = (T1 >> shift) & 0xff;
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244 | 9ee6e8bb | pbrook | if (index <= maxindex) {
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245 | 9ee6e8bb | pbrook | tmp = (table[index >> 3] >> (index & 7)) & 0xff; |
246 | 9ee6e8bb | pbrook | val |= tmp << shift; |
247 | 9ee6e8bb | pbrook | } else {
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248 | 9ee6e8bb | pbrook | val |= T0 & (0xff << shift);
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249 | 9ee6e8bb | pbrook | } |
250 | 9ee6e8bb | pbrook | } |
251 | 9ee6e8bb | pbrook | T0 = val; |
252 | 9ee6e8bb | pbrook | } |
253 | 9ee6e8bb | pbrook | |
254 | b5ff1b31 | bellard | #if !defined(CONFIG_USER_ONLY)
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255 | b5ff1b31 | bellard | |
256 | b5ff1b31 | bellard | #define MMUSUFFIX _mmu
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257 | 273af660 | ths | #ifdef __s390__
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258 | 273af660 | ths | # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
259 | 273af660 | ths | #else
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260 | 273af660 | ths | # define GETPC() (__builtin_return_address(0)) |
261 | 273af660 | ths | #endif
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262 | b5ff1b31 | bellard | |
263 | b5ff1b31 | bellard | #define SHIFT 0 |
264 | b5ff1b31 | bellard | #include "softmmu_template.h" |
265 | b5ff1b31 | bellard | |
266 | b5ff1b31 | bellard | #define SHIFT 1 |
267 | b5ff1b31 | bellard | #include "softmmu_template.h" |
268 | b5ff1b31 | bellard | |
269 | b5ff1b31 | bellard | #define SHIFT 2 |
270 | b5ff1b31 | bellard | #include "softmmu_template.h" |
271 | b5ff1b31 | bellard | |
272 | b5ff1b31 | bellard | #define SHIFT 3 |
273 | b5ff1b31 | bellard | #include "softmmu_template.h" |
274 | b5ff1b31 | bellard | |
275 | b5ff1b31 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
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276 | b5ff1b31 | bellard | NULL, it means that the function was called in C code (i.e. not
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277 | b5ff1b31 | bellard | from generated code or from helper.c) */
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278 | b5ff1b31 | bellard | /* XXX: fix it to restore all registers */
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279 | 6ebbf390 | j_mayer | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
280 | b5ff1b31 | bellard | { |
281 | b5ff1b31 | bellard | TranslationBlock *tb; |
282 | b5ff1b31 | bellard | CPUState *saved_env; |
283 | 44f8625d | bellard | unsigned long pc; |
284 | b5ff1b31 | bellard | int ret;
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285 | b5ff1b31 | bellard | |
286 | b5ff1b31 | bellard | /* XXX: hack to restore env in all cases, even if not called from
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287 | b5ff1b31 | bellard | generated code */
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288 | b5ff1b31 | bellard | saved_env = env; |
289 | b5ff1b31 | bellard | env = cpu_single_env; |
290 | 6ebbf390 | j_mayer | ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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291 | b5ff1b31 | bellard | if (__builtin_expect(ret, 0)) { |
292 | b5ff1b31 | bellard | if (retaddr) {
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293 | b5ff1b31 | bellard | /* now we have a real cpu fault */
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294 | 44f8625d | bellard | pc = (unsigned long)retaddr; |
295 | b5ff1b31 | bellard | tb = tb_find_pc(pc); |
296 | b5ff1b31 | bellard | if (tb) {
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297 | b5ff1b31 | bellard | /* the PC is inside the translated code. It means that we have
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298 | b5ff1b31 | bellard | a virtual CPU fault */
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299 | b5ff1b31 | bellard | cpu_restore_state(tb, env, pc, NULL);
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300 | b5ff1b31 | bellard | } |
301 | b5ff1b31 | bellard | } |
302 | b5ff1b31 | bellard | raise_exception(env->exception_index); |
303 | b5ff1b31 | bellard | } |
304 | b5ff1b31 | bellard | env = saved_env; |
305 | b5ff1b31 | bellard | } |
306 | b5ff1b31 | bellard | #endif
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307 | 1497c961 | pbrook | |
308 | 1497c961 | pbrook | #define SIGNBIT (uint32_t)0x80000000 |
309 | 1497c961 | pbrook | uint32_t HELPER(add_setq)(uint32_t a, uint32_t b) |
310 | 1497c961 | pbrook | { |
311 | 1497c961 | pbrook | uint32_t res = a + b; |
312 | 1497c961 | pbrook | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
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313 | 1497c961 | pbrook | env->QF = 1;
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314 | 1497c961 | pbrook | return res;
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315 | 1497c961 | pbrook | } |
316 | 1497c961 | pbrook | |
317 | 1497c961 | pbrook | uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b) |
318 | 1497c961 | pbrook | { |
319 | 1497c961 | pbrook | uint32_t res = a + b; |
320 | 1497c961 | pbrook | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
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321 | 1497c961 | pbrook | env->QF = 1;
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322 | 1497c961 | pbrook | res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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323 | 1497c961 | pbrook | } |
324 | 1497c961 | pbrook | return res;
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325 | 1497c961 | pbrook | } |
326 | 1497c961 | pbrook | |
327 | 1497c961 | pbrook | uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b) |
328 | 1497c961 | pbrook | { |
329 | 1497c961 | pbrook | uint32_t res = a - b; |
330 | 1497c961 | pbrook | if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
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331 | 1497c961 | pbrook | env->QF = 1;
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332 | 1497c961 | pbrook | res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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333 | 1497c961 | pbrook | } |
334 | 1497c961 | pbrook | return res;
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335 | 1497c961 | pbrook | } |
336 | 1497c961 | pbrook | |
337 | 1497c961 | pbrook | uint32_t HELPER(double_saturate)(int32_t val) |
338 | 1497c961 | pbrook | { |
339 | 1497c961 | pbrook | uint32_t res; |
340 | 1497c961 | pbrook | if (val >= 0x40000000) { |
341 | 1497c961 | pbrook | res = ~SIGNBIT; |
342 | 1497c961 | pbrook | env->QF = 1;
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343 | 1497c961 | pbrook | } else if (val <= (int32_t)0xc0000000) { |
344 | 1497c961 | pbrook | res = SIGNBIT; |
345 | 1497c961 | pbrook | env->QF = 1;
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346 | 1497c961 | pbrook | } else {
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347 | 1497c961 | pbrook | res = val << 1;
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348 | 1497c961 | pbrook | } |
349 | 1497c961 | pbrook | return res;
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350 | 1497c961 | pbrook | } |
351 | 1497c961 | pbrook | |
352 | 1497c961 | pbrook | uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b) |
353 | 1497c961 | pbrook | { |
354 | 1497c961 | pbrook | uint32_t res = a + b; |
355 | 1497c961 | pbrook | if (res < a) {
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356 | 1497c961 | pbrook | env->QF = 1;
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357 | 1497c961 | pbrook | res = ~0;
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358 | 1497c961 | pbrook | } |
359 | 1497c961 | pbrook | return res;
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360 | 1497c961 | pbrook | } |
361 | 1497c961 | pbrook | |
362 | 1497c961 | pbrook | uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b) |
363 | 1497c961 | pbrook | { |
364 | 1497c961 | pbrook | uint32_t res = a - b; |
365 | 1497c961 | pbrook | if (res > a) {
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366 | 1497c961 | pbrook | env->QF = 1;
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367 | 1497c961 | pbrook | res = 0;
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368 | 1497c961 | pbrook | } |
369 | 1497c961 | pbrook | return res;
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370 | 1497c961 | pbrook | } |