Revision 1497c961 target-arm/translate.c
b/target-arm/translate.c | ||
---|---|---|
29 | 29 |
#include "exec-all.h" |
30 | 30 |
#include "disas.h" |
31 | 31 |
#include "tcg-op.h" |
32 |
|
|
33 |
#define GEN_HELPER 1 |
|
32 | 34 |
#include "helpers.h" |
33 | 35 |
|
34 | 36 |
#define ENABLE_ARCH_5J 0 |
... | ... | |
200 | 202 |
#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var) |
201 | 203 |
#define gen_sxth(var) tcg_gen_ext16s_i32(var, var) |
202 | 204 |
|
203 |
#define HELPER_ADDR(x) helper_##x |
|
204 |
|
|
205 |
#define gen_sxtb16(var) tcg_gen_helper_1_1(HELPER_ADDR(sxtb16), var, var) |
|
206 |
#define gen_uxtb16(var) tcg_gen_helper_1_1(HELPER_ADDR(uxtb16), var, var) |
|
205 |
#define gen_sxtb16(var) gen_helper_sxtb16(var, var) |
|
206 |
#define gen_uxtb16(var) gen_helper_uxtb16(var, var) |
|
207 | 207 |
|
208 |
#define gen_op_clz_T0(var) \ |
|
209 |
tcg_gen_helper_1_1(HELPER_ADDR(clz), cpu_T[0], cpu_T[0]) |
|
208 |
#define gen_op_addl_T0_T1_setq() \ |
|
209 |
gen_helper_add_setq(cpu_T[0], cpu_T[0], cpu_T[1]) |
|
210 |
#define gen_op_addl_T0_T1_saturate() \ |
|
211 |
gen_helper_add_saturate(cpu_T[0], cpu_T[0], cpu_T[1]) |
|
212 |
#define gen_op_subl_T0_T1_saturate() \ |
|
213 |
gen_helper_sub_saturate(cpu_T[0], cpu_T[0], cpu_T[1]) |
|
214 |
#define gen_op_addl_T0_T1_usaturate() \ |
|
215 |
gen_helper_add_usaturate(cpu_T[0], cpu_T[0], cpu_T[1]) |
|
216 |
#define gen_op_subl_T0_T1_usaturate() \ |
|
217 |
gen_helper_sub_usaturate(cpu_T[0], cpu_T[0], cpu_T[1]) |
|
210 | 218 |
|
211 | 219 |
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. |
212 | 220 |
tmp = (t0 ^ t1) & 0x8000; |
... | ... | |
4526 | 4534 |
switch (size) { |
4527 | 4535 |
case 0: gen_op_neon_clz_u8(); break; |
4528 | 4536 |
case 1: gen_op_neon_clz_u16(); break; |
4529 |
case 2: gen_op_clz_T0(); break;
|
|
4537 |
case 2: gen_helper_clz(cpu_T[0], cpu_T[0]); break;
|
|
4530 | 4538 |
default: return 1; |
4531 | 4539 |
} |
4532 | 4540 |
break; |
... | ... | |
5021 | 5029 |
} else if (op1 == 3) { |
5022 | 5030 |
/* clz */ |
5023 | 5031 |
rd = (insn >> 12) & 0xf; |
5024 |
gen_movl_T0_reg(s, rm);
|
|
5025 |
gen_op_clz_T0();
|
|
5026 |
gen_movl_reg_T0(s, rd);
|
|
5032 |
tmp = load_reg(s, rm);
|
|
5033 |
gen_helper_clz(tmp, tmp);
|
|
5034 |
store_reg(s, rd, tmp);
|
|
5027 | 5035 |
} else { |
5028 | 5036 |
goto illegal_op; |
5029 | 5037 |
} |
... | ... | |
5055 | 5063 |
gen_movl_T0_reg(s, rm); |
5056 | 5064 |
gen_movl_T1_reg(s, rn); |
5057 | 5065 |
if (op1 & 2) |
5058 |
gen_op_double_T1_saturate();
|
|
5066 |
gen_helper_double_saturate(cpu_T[1], cpu_T[1]);
|
|
5059 | 5067 |
if (op1 & 1) |
5060 | 5068 |
gen_op_subl_T0_T1_saturate(); |
5061 | 5069 |
else |
... | ... | |
6317 | 6325 |
gen_movl_T0_reg(s, rm); |
6318 | 6326 |
gen_movl_T1_reg(s, rn); |
6319 | 6327 |
if (op & 2) |
6320 |
gen_op_double_T1_saturate();
|
|
6328 |
gen_helper_double_saturate(cpu_T[1], cpu_T[1]);
|
|
6321 | 6329 |
if (op & 1) |
6322 | 6330 |
gen_op_subl_T0_T1_saturate(); |
6323 | 6331 |
else |
... | ... | |
6342 | 6350 |
gen_op_sel_T0_T1(); |
6343 | 6351 |
break; |
6344 | 6352 |
case 0x18: /* clz */ |
6345 |
gen_op_clz_T0();
|
|
6353 |
gen_helper_clz(cpu_T[0], cpu_T[0]);
|
|
6346 | 6354 |
break; |
6347 | 6355 |
default: |
6348 | 6356 |
goto illegal_op; |
Also available in: Unified diff