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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h" |
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#include "qemu-common.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h" |
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#endif
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#include "sysemu/sysemu.h" |
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static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
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{ |
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ARMCPU *cpu = ARM_CPU(cs); |
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cpu->env.regs[15] = value;
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} |
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
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{ |
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value; |
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ARMCPU *cpu = opaque; |
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if (ri->type & ARM_CP_SPECIAL) {
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return;
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} |
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if (ri->resetfn) {
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ri->resetfn(&cpu->env, ri); |
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return;
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} |
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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*/
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if (!ri->fieldoffset) {
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return;
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} |
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if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
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} else {
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; |
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} |
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} |
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s) |
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{ |
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ARMCPU *cpu = ARM_CPU(s); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); |
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CPUARMState *env = &cpu->env; |
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acc->parent_reset(s); |
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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} |
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
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env->cp15.c15_cpar = 1;
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} |
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc; |
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uint8_t *rom; |
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env->uncached_cpsr &= ~CPSR_I; |
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom);
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1; |
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} |
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} |
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.fp_status); |
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.standard_fp_status); |
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env); |
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} |
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static inline void set_feature(CPUARMState *env, int feature) |
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{ |
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env->features |= 1ULL << feature;
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} |
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static void arm_cpu_initfn(Object *obj) |
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{ |
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CPUState *cs = CPU(obj); |
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ARMCPU *cpu = ARM_CPU(obj); |
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static bool inited; |
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cs->env_ptr = &cpu->env; |
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cpu_exec_init(&cpu->env); |
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
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g_free, g_free); |
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if (tcg_enabled() && !inited) {
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inited = true;
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arm_translate_init(); |
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} |
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} |
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static void arm_cpu_finalizefn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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g_hash_table_destroy(cpu->cp_regs); |
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} |
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static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
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{ |
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CPUState *cs = CPU(dev); |
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ARMCPU *cpu = ARM_CPU(dev); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); |
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CPUARMState *env = &cpu->env; |
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_ARM_DIV); |
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set_feature(env, ARM_FEATURE_LPAE); |
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} |
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_MPIDR); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K); |
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} else {
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set_feature(env, ARM_FEATURE_V6); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_MVFR); |
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} |
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T); |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP); |
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} |
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP); |
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set_feature(env, ARM_FEATURE_PXN); |
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} |
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register_cp_regs_for_features(cpu); |
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arm_cpu_register_gdb_regs_for_features(cpu); |
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init_cpreg_list(cpu); |
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cpu_reset(cs); |
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qemu_init_vcpu(cs); |
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acc->parent_realize(dev, errp); |
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} |
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/* CPU models */
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static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
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{ |
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ObjectClass *oc; |
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char *typename;
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if (!cpu_model) {
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return NULL; |
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} |
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typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
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oc = object_class_by_name(typename); |
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g_free(typename); |
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if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
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object_class_is_abstract(oc)) { |
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return NULL; |
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} |
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return oc;
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} |
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static void arm926_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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} |
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static void arm946_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_MPU); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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cpu->midr = 0x41059461;
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cpu->ctr = 0x0f004006;
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cpu->reset_sctlr = 0x00000078;
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} |
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static void arm1026_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x4106a262;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
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{ |
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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ARMCPRegInfo ifar = { |
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.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
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.access = PL1_RW, |
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.fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
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.resetvalue = 0
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}; |
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define_one_arm_cp_reg(cpu, &ifar); |
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} |
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} |
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static void arm1136_r2_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
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*/
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set_feature(&cpu->env, ARM_FEATURE_V6); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
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cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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} |
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static void arm1136_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V6K); |
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set_feature(&cpu->env, ARM_FEATURE_V6); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
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cpu->midr = 0x4117b363;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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} |
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static void arm1176_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V6K); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_VAPA); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
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cpu->midr = 0x410fb767;
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x11;
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cpu->id_dfr0 = 0x33;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->id_isar0 = 0x0140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231121;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x01141;
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cpu->reset_auxcr = 7;
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} |
389 |
|
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static void arm11mpcore_initfn(Object *obj) |
391 |
{ |
392 |
ARMCPU *cpu = ARM_CPU(obj); |
393 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
394 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
395 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
396 |
set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
397 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
398 |
cpu->midr = 0x410fb022;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
403 |
cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0;
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cpu->id_afr0 = 0x2;
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
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cpu->id_isar0 = 0x00100011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11221011;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 1;
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} |
417 |
|
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static void cortex_m3_initfn(Object *obj) |
419 |
{ |
420 |
ARMCPU *cpu = ARM_CPU(obj); |
421 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
422 |
set_feature(&cpu->env, ARM_FEATURE_M); |
423 |
cpu->midr = 0x410fc231;
|
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} |
425 |
|
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static void arm_v7m_class_init(ObjectClass *oc, void *data) |
427 |
{ |
428 |
#ifndef CONFIG_USER_ONLY
|
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CPUClass *cc = CPU_CLASS(oc); |
430 |
|
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cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
432 |
#endif
|
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} |
434 |
|
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
436 |
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, |
437 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
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{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
439 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
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REGINFO_SENTINEL |
441 |
}; |
442 |
|
443 |
static void cortex_a8_initfn(Object *obj) |
444 |
{ |
445 |
ARMCPU *cpu = ARM_CPU(obj); |
446 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
447 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
448 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
449 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
450 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
451 |
cpu->midr = 0x410fc080;
|
452 |
cpu->reset_fpsid = 0x410330c0;
|
453 |
cpu->mvfr0 = 0x11110222;
|
454 |
cpu->mvfr1 = 0x00011100;
|
455 |
cpu->ctr = 0x82048004;
|
456 |
cpu->reset_sctlr = 0x00c50078;
|
457 |
cpu->id_pfr0 = 0x1031;
|
458 |
cpu->id_pfr1 = 0x11;
|
459 |
cpu->id_dfr0 = 0x400;
|
460 |
cpu->id_afr0 = 0;
|
461 |
cpu->id_mmfr0 = 0x31100003;
|
462 |
cpu->id_mmfr1 = 0x20000000;
|
463 |
cpu->id_mmfr2 = 0x01202000;
|
464 |
cpu->id_mmfr3 = 0x11;
|
465 |
cpu->id_isar0 = 0x00101111;
|
466 |
cpu->id_isar1 = 0x12112111;
|
467 |
cpu->id_isar2 = 0x21232031;
|
468 |
cpu->id_isar3 = 0x11112131;
|
469 |
cpu->id_isar4 = 0x00111142;
|
470 |
cpu->clidr = (1 << 27) | (2 << 24) | 3; |
471 |
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
472 |
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
473 |
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
474 |
cpu->reset_auxcr = 2;
|
475 |
define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
476 |
} |
477 |
|
478 |
static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
479 |
/* power_control should be set to maximum latency. Again,
|
480 |
* default to 0 and set by private hook
|
481 |
*/
|
482 |
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
483 |
.access = PL1_RW, .resetvalue = 0,
|
484 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, |
485 |
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, |
486 |
.access = PL1_RW, .resetvalue = 0,
|
487 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, |
488 |
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, |
489 |
.access = PL1_RW, .resetvalue = 0,
|
490 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, |
491 |
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, |
492 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
493 |
/* TLB lockdown control */
|
494 |
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, |
495 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
496 |
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, |
497 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
498 |
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, |
499 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
500 |
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, |
501 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
502 |
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, |
503 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
504 |
REGINFO_SENTINEL |
505 |
}; |
506 |
|
507 |
static void cortex_a9_initfn(Object *obj) |
508 |
{ |
509 |
ARMCPU *cpu = ARM_CPU(obj); |
510 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
511 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
512 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
513 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
514 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
515 |
/* Note that A9 supports the MP extensions even for
|
516 |
* A9UP and single-core A9MP (which are both different
|
517 |
* and valid configurations; we don't model A9UP).
|
518 |
*/
|
519 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
520 |
cpu->midr = 0x410fc090;
|
521 |
cpu->reset_fpsid = 0x41033090;
|
522 |
cpu->mvfr0 = 0x11110222;
|
523 |
cpu->mvfr1 = 0x01111111;
|
524 |
cpu->ctr = 0x80038003;
|
525 |
cpu->reset_sctlr = 0x00c50078;
|
526 |
cpu->id_pfr0 = 0x1031;
|
527 |
cpu->id_pfr1 = 0x11;
|
528 |
cpu->id_dfr0 = 0x000;
|
529 |
cpu->id_afr0 = 0;
|
530 |
cpu->id_mmfr0 = 0x00100103;
|
531 |
cpu->id_mmfr1 = 0x20000000;
|
532 |
cpu->id_mmfr2 = 0x01230000;
|
533 |
cpu->id_mmfr3 = 0x00002111;
|
534 |
cpu->id_isar0 = 0x00101111;
|
535 |
cpu->id_isar1 = 0x13112111;
|
536 |
cpu->id_isar2 = 0x21232041;
|
537 |
cpu->id_isar3 = 0x11112131;
|
538 |
cpu->id_isar4 = 0x00111142;
|
539 |
cpu->clidr = (1 << 27) | (1 << 24) | 3; |
540 |
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
541 |
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
542 |
{ |
543 |
ARMCPRegInfo cbar = { |
544 |
.name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, |
545 |
.opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
|
546 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) |
547 |
}; |
548 |
define_one_arm_cp_reg(cpu, &cbar); |
549 |
define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
550 |
} |
551 |
} |
552 |
|
553 |
#ifndef CONFIG_USER_ONLY
|
554 |
static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
555 |
uint64_t *value) |
556 |
{ |
557 |
/* Linux wants the number of processors from here.
|
558 |
* Might as well set the interrupt-controller bit too.
|
559 |
*/
|
560 |
*value = ((smp_cpus - 1) << 24) | (1 << 23); |
561 |
return 0; |
562 |
} |
563 |
#endif
|
564 |
|
565 |
static const ARMCPRegInfo cortexa15_cp_reginfo[] = { |
566 |
#ifndef CONFIG_USER_ONLY
|
567 |
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
568 |
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
569 |
.writefn = arm_cp_write_ignore, }, |
570 |
#endif
|
571 |
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, |
572 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
573 |
REGINFO_SENTINEL |
574 |
}; |
575 |
|
576 |
static void cortex_a15_initfn(Object *obj) |
577 |
{ |
578 |
ARMCPU *cpu = ARM_CPU(obj); |
579 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
580 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
582 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
583 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
584 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
585 |
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
586 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
587 |
set_feature(&cpu->env, ARM_FEATURE_LPAE); |
588 |
cpu->midr = 0x412fc0f1;
|
589 |
cpu->reset_fpsid = 0x410430f0;
|
590 |
cpu->mvfr0 = 0x10110222;
|
591 |
cpu->mvfr1 = 0x11111111;
|
592 |
cpu->ctr = 0x8444c004;
|
593 |
cpu->reset_sctlr = 0x00c50078;
|
594 |
cpu->id_pfr0 = 0x00001131;
|
595 |
cpu->id_pfr1 = 0x00011011;
|
596 |
cpu->id_dfr0 = 0x02010555;
|
597 |
cpu->id_afr0 = 0x00000000;
|
598 |
cpu->id_mmfr0 = 0x10201105;
|
599 |
cpu->id_mmfr1 = 0x20000000;
|
600 |
cpu->id_mmfr2 = 0x01240000;
|
601 |
cpu->id_mmfr3 = 0x02102211;
|
602 |
cpu->id_isar0 = 0x02101110;
|
603 |
cpu->id_isar1 = 0x13112111;
|
604 |
cpu->id_isar2 = 0x21232041;
|
605 |
cpu->id_isar3 = 0x11112131;
|
606 |
cpu->id_isar4 = 0x10011142;
|
607 |
cpu->clidr = 0x0a200023;
|
608 |
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
609 |
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
610 |
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
611 |
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
612 |
} |
613 |
|
614 |
static void ti925t_initfn(Object *obj) |
615 |
{ |
616 |
ARMCPU *cpu = ARM_CPU(obj); |
617 |
set_feature(&cpu->env, ARM_FEATURE_V4T); |
618 |
set_feature(&cpu->env, ARM_FEATURE_OMAPCP); |
619 |
cpu->midr = ARM_CPUID_TI925T; |
620 |
cpu->ctr = 0x5109149;
|
621 |
cpu->reset_sctlr = 0x00000070;
|
622 |
} |
623 |
|
624 |
static void sa1100_initfn(Object *obj) |
625 |
{ |
626 |
ARMCPU *cpu = ARM_CPU(obj); |
627 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
628 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
629 |
cpu->midr = 0x4401A11B;
|
630 |
cpu->reset_sctlr = 0x00000070;
|
631 |
} |
632 |
|
633 |
static void sa1110_initfn(Object *obj) |
634 |
{ |
635 |
ARMCPU *cpu = ARM_CPU(obj); |
636 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
637 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
638 |
cpu->midr = 0x6901B119;
|
639 |
cpu->reset_sctlr = 0x00000070;
|
640 |
} |
641 |
|
642 |
static void pxa250_initfn(Object *obj) |
643 |
{ |
644 |
ARMCPU *cpu = ARM_CPU(obj); |
645 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
646 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
647 |
cpu->midr = 0x69052100;
|
648 |
cpu->ctr = 0xd172172;
|
649 |
cpu->reset_sctlr = 0x00000078;
|
650 |
} |
651 |
|
652 |
static void pxa255_initfn(Object *obj) |
653 |
{ |
654 |
ARMCPU *cpu = ARM_CPU(obj); |
655 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
656 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
657 |
cpu->midr = 0x69052d00;
|
658 |
cpu->ctr = 0xd172172;
|
659 |
cpu->reset_sctlr = 0x00000078;
|
660 |
} |
661 |
|
662 |
static void pxa260_initfn(Object *obj) |
663 |
{ |
664 |
ARMCPU *cpu = ARM_CPU(obj); |
665 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
666 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
667 |
cpu->midr = 0x69052903;
|
668 |
cpu->ctr = 0xd172172;
|
669 |
cpu->reset_sctlr = 0x00000078;
|
670 |
} |
671 |
|
672 |
static void pxa261_initfn(Object *obj) |
673 |
{ |
674 |
ARMCPU *cpu = ARM_CPU(obj); |
675 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
676 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
677 |
cpu->midr = 0x69052d05;
|
678 |
cpu->ctr = 0xd172172;
|
679 |
cpu->reset_sctlr = 0x00000078;
|
680 |
} |
681 |
|
682 |
static void pxa262_initfn(Object *obj) |
683 |
{ |
684 |
ARMCPU *cpu = ARM_CPU(obj); |
685 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
686 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
687 |
cpu->midr = 0x69052d06;
|
688 |
cpu->ctr = 0xd172172;
|
689 |
cpu->reset_sctlr = 0x00000078;
|
690 |
} |
691 |
|
692 |
static void pxa270a0_initfn(Object *obj) |
693 |
{ |
694 |
ARMCPU *cpu = ARM_CPU(obj); |
695 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
696 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
697 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
698 |
cpu->midr = 0x69054110;
|
699 |
cpu->ctr = 0xd172172;
|
700 |
cpu->reset_sctlr = 0x00000078;
|
701 |
} |
702 |
|
703 |
static void pxa270a1_initfn(Object *obj) |
704 |
{ |
705 |
ARMCPU *cpu = ARM_CPU(obj); |
706 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
707 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
708 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
709 |
cpu->midr = 0x69054111;
|
710 |
cpu->ctr = 0xd172172;
|
711 |
cpu->reset_sctlr = 0x00000078;
|
712 |
} |
713 |
|
714 |
static void pxa270b0_initfn(Object *obj) |
715 |
{ |
716 |
ARMCPU *cpu = ARM_CPU(obj); |
717 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
718 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
719 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
720 |
cpu->midr = 0x69054112;
|
721 |
cpu->ctr = 0xd172172;
|
722 |
cpu->reset_sctlr = 0x00000078;
|
723 |
} |
724 |
|
725 |
static void pxa270b1_initfn(Object *obj) |
726 |
{ |
727 |
ARMCPU *cpu = ARM_CPU(obj); |
728 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
729 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
730 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
731 |
cpu->midr = 0x69054113;
|
732 |
cpu->ctr = 0xd172172;
|
733 |
cpu->reset_sctlr = 0x00000078;
|
734 |
} |
735 |
|
736 |
static void pxa270c0_initfn(Object *obj) |
737 |
{ |
738 |
ARMCPU *cpu = ARM_CPU(obj); |
739 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
740 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
741 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
742 |
cpu->midr = 0x69054114;
|
743 |
cpu->ctr = 0xd172172;
|
744 |
cpu->reset_sctlr = 0x00000078;
|
745 |
} |
746 |
|
747 |
static void pxa270c5_initfn(Object *obj) |
748 |
{ |
749 |
ARMCPU *cpu = ARM_CPU(obj); |
750 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
751 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
752 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
753 |
cpu->midr = 0x69054117;
|
754 |
cpu->ctr = 0xd172172;
|
755 |
cpu->reset_sctlr = 0x00000078;
|
756 |
} |
757 |
|
758 |
static void arm_any_initfn(Object *obj) |
759 |
{ |
760 |
ARMCPU *cpu = ARM_CPU(obj); |
761 |
set_feature(&cpu->env, ARM_FEATURE_V8); |
762 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
763 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
764 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
765 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
766 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
767 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
768 |
cpu->midr = 0xffffffff;
|
769 |
} |
770 |
|
771 |
typedef struct ARMCPUInfo { |
772 |
const char *name; |
773 |
void (*initfn)(Object *obj);
|
774 |
void (*class_init)(ObjectClass *oc, void *data); |
775 |
} ARMCPUInfo; |
776 |
|
777 |
static const ARMCPUInfo arm_cpus[] = { |
778 |
{ .name = "arm926", .initfn = arm926_initfn },
|
779 |
{ .name = "arm946", .initfn = arm946_initfn },
|
780 |
{ .name = "arm1026", .initfn = arm1026_initfn },
|
781 |
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
782 |
* older core than plain "arm1136". In particular this does not
|
783 |
* have the v6K features.
|
784 |
*/
|
785 |
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
786 |
{ .name = "arm1136", .initfn = arm1136_initfn },
|
787 |
{ .name = "arm1176", .initfn = arm1176_initfn },
|
788 |
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
789 |
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
790 |
.class_init = arm_v7m_class_init }, |
791 |
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
792 |
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
793 |
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
794 |
{ .name = "ti925t", .initfn = ti925t_initfn },
|
795 |
{ .name = "sa1100", .initfn = sa1100_initfn },
|
796 |
{ .name = "sa1110", .initfn = sa1110_initfn },
|
797 |
{ .name = "pxa250", .initfn = pxa250_initfn },
|
798 |
{ .name = "pxa255", .initfn = pxa255_initfn },
|
799 |
{ .name = "pxa260", .initfn = pxa260_initfn },
|
800 |
{ .name = "pxa261", .initfn = pxa261_initfn },
|
801 |
{ .name = "pxa262", .initfn = pxa262_initfn },
|
802 |
/* "pxa270" is an alias for "pxa270-a0" */
|
803 |
{ .name = "pxa270", .initfn = pxa270a0_initfn },
|
804 |
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
805 |
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
806 |
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
807 |
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
808 |
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
809 |
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
810 |
{ .name = "any", .initfn = arm_any_initfn },
|
811 |
}; |
812 |
|
813 |
static void arm_cpu_class_init(ObjectClass *oc, void *data) |
814 |
{ |
815 |
ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
816 |
CPUClass *cc = CPU_CLASS(acc); |
817 |
DeviceClass *dc = DEVICE_CLASS(oc); |
818 |
|
819 |
acc->parent_realize = dc->realize; |
820 |
dc->realize = arm_cpu_realizefn; |
821 |
|
822 |
acc->parent_reset = cc->reset; |
823 |
cc->reset = arm_cpu_reset; |
824 |
|
825 |
cc->class_by_name = arm_cpu_class_by_name; |
826 |
cc->do_interrupt = arm_cpu_do_interrupt; |
827 |
cc->dump_state = arm_cpu_dump_state; |
828 |
cc->set_pc = arm_cpu_set_pc; |
829 |
cc->gdb_read_register = arm_cpu_gdb_read_register; |
830 |
cc->gdb_write_register = arm_cpu_gdb_write_register; |
831 |
#ifndef CONFIG_USER_ONLY
|
832 |
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
833 |
cc->vmsd = &vmstate_arm_cpu; |
834 |
#endif
|
835 |
cc->gdb_num_core_regs = 26;
|
836 |
cc->gdb_core_xml_file = "arm-core.xml";
|
837 |
} |
838 |
|
839 |
static void cpu_register(const ARMCPUInfo *info) |
840 |
{ |
841 |
TypeInfo type_info = { |
842 |
.parent = TYPE_ARM_CPU, |
843 |
.instance_size = sizeof(ARMCPU),
|
844 |
.instance_init = info->initfn, |
845 |
.class_size = sizeof(ARMCPUClass),
|
846 |
.class_init = info->class_init, |
847 |
}; |
848 |
|
849 |
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
850 |
type_register(&type_info); |
851 |
g_free((void *)type_info.name);
|
852 |
} |
853 |
|
854 |
static const TypeInfo arm_cpu_type_info = { |
855 |
.name = TYPE_ARM_CPU, |
856 |
.parent = TYPE_CPU, |
857 |
.instance_size = sizeof(ARMCPU),
|
858 |
.instance_init = arm_cpu_initfn, |
859 |
.instance_finalize = arm_cpu_finalizefn, |
860 |
.abstract = true,
|
861 |
.class_size = sizeof(ARMCPUClass),
|
862 |
.class_init = arm_cpu_class_init, |
863 |
}; |
864 |
|
865 |
static void arm_cpu_register_types(void) |
866 |
{ |
867 |
int i;
|
868 |
|
869 |
type_register_static(&arm_cpu_type_info); |
870 |
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
871 |
cpu_register(&arm_cpus[i]); |
872 |
} |
873 |
} |
874 |
|
875 |
type_init(arm_cpu_register_types) |