root / target-cris / cpu.c @ 14a10fc3
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/*
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* QEMU CRIS CPU
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*
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* Copyright (c) 2008 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h" |
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#include "qemu-common.h" |
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#include "mmu.h" |
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static void cris_cpu_set_pc(CPUState *cs, vaddr value) |
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{ |
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CRISCPU *cpu = CRIS_CPU(cs); |
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cpu->env.pc = value; |
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} |
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/* CPUClass::reset() */
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static void cris_cpu_reset(CPUState *s) |
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{ |
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CRISCPU *cpu = CRIS_CPU(s); |
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); |
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CPUCRISState *env = &cpu->env; |
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uint32_t vr; |
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ccc->parent_reset(s); |
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vr = env->pregs[PR_VR]; |
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memset(env, 0, offsetof(CPUCRISState, breakpoints));
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env->pregs[PR_VR] = vr; |
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tlb_flush(env, 1);
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; |
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#else
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cris_mmu_init(env); |
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env->pregs[PR_CCS] = 0;
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#endif
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} |
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static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) |
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{ |
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ObjectClass *oc; |
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char *typename;
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if (cpu_model == NULL) { |
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return NULL; |
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} |
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typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
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oc = object_class_by_name(typename); |
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g_free(typename); |
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || |
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object_class_is_abstract(oc))) { |
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oc = NULL;
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} |
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return oc;
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} |
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CRISCPU *cpu_cris_init(const char *cpu_model) |
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{ |
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CRISCPU *cpu; |
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ObjectClass *oc; |
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oc = cris_cpu_class_by_name(cpu_model); |
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if (oc == NULL) { |
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return NULL; |
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} |
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cpu = CRIS_CPU(object_new(object_class_get_name(oc))); |
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
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return cpu;
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} |
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/* Sort alphabetically by VR. */
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static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
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{ |
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CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); |
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CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); |
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/* */
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if (ccc_a->vr > ccc_b->vr) {
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return 1; |
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} else if (ccc_a->vr < ccc_b->vr) { |
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return -1; |
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} else {
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return 0; |
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} |
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} |
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static void cris_cpu_list_entry(gpointer data, gpointer user_data) |
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{ |
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ObjectClass *oc = data; |
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CPUListState *s = user_data; |
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const char *typename = object_class_get_name(oc); |
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char *name;
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name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
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(*s->cpu_fprintf)(s->file, " %s\n", name);
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g_free(name); |
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} |
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void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{ |
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CPUListState s = { |
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.file = f, |
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.cpu_fprintf = cpu_fprintf, |
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}; |
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GSList *list; |
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list = object_class_get_list(TYPE_CRIS_CPU, false);
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list = g_slist_sort(list, cris_cpu_list_compare); |
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, cris_cpu_list_entry, &s); |
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g_slist_free(list); |
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} |
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static void cris_cpu_realizefn(DeviceState *dev, Error **errp) |
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{ |
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CPUState *cs = CPU(dev); |
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); |
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cpu_reset(cs); |
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qemu_init_vcpu(cs); |
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ccc->parent_realize(dev, errp); |
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} |
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static void cris_cpu_initfn(Object *obj) |
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{ |
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CPUState *cs = CPU(obj); |
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CRISCPU *cpu = CRIS_CPU(obj); |
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CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); |
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CPUCRISState *env = &cpu->env; |
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static bool tcg_initialized; |
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cs->env_ptr = env; |
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cpu_exec_init(env); |
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env->pregs[PR_VR] = ccc->vr; |
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if (tcg_enabled() && !tcg_initialized) {
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tcg_initialized = true;
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if (env->pregs[PR_VR] < 32) { |
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cris_initialize_crisv10_tcg(); |
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} else {
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cris_initialize_tcg(); |
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} |
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} |
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} |
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static void crisv8_cpu_class_init(ObjectClass *oc, void *data) |
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{ |
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CPUClass *cc = CPU_CLASS(oc); |
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
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ccc->vr = 8;
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cc->do_interrupt = crisv10_cpu_do_interrupt; |
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cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
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} |
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static void crisv9_cpu_class_init(ObjectClass *oc, void *data) |
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{ |
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CPUClass *cc = CPU_CLASS(oc); |
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
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ccc->vr = 9;
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cc->do_interrupt = crisv10_cpu_do_interrupt; |
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cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
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} |
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static void crisv10_cpu_class_init(ObjectClass *oc, void *data) |
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{ |
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CPUClass *cc = CPU_CLASS(oc); |
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
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ccc->vr = 10;
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cc->do_interrupt = crisv10_cpu_do_interrupt; |
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cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
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} |
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static void crisv11_cpu_class_init(ObjectClass *oc, void *data) |
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{ |
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CPUClass *cc = CPU_CLASS(oc); |
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
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ccc->vr = 11;
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cc->do_interrupt = crisv10_cpu_do_interrupt; |
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cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
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} |
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static void crisv32_cpu_class_init(ObjectClass *oc, void *data) |
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{ |
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
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ccc->vr = 32;
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} |
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#define TYPE(model) model "-" TYPE_CRIS_CPU |
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static const TypeInfo cris_cpu_model_type_infos[] = { |
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{ |
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.name = TYPE("crisv8"),
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.parent = TYPE_CRIS_CPU, |
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.class_init = crisv8_cpu_class_init, |
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}, { |
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.name = TYPE("crisv9"),
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.parent = TYPE_CRIS_CPU, |
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.class_init = crisv9_cpu_class_init, |
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}, { |
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.name = TYPE("crisv10"),
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.parent = TYPE_CRIS_CPU, |
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.class_init = crisv10_cpu_class_init, |
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}, { |
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.name = TYPE("crisv11"),
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.parent = TYPE_CRIS_CPU, |
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.class_init = crisv11_cpu_class_init, |
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}, { |
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.name = TYPE("crisv32"),
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.parent = TYPE_CRIS_CPU, |
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.class_init = crisv32_cpu_class_init, |
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} |
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}; |
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#undef TYPE
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static void cris_cpu_class_init(ObjectClass *oc, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(oc); |
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CPUClass *cc = CPU_CLASS(oc); |
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CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
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ccc->parent_realize = dc->realize; |
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dc->realize = cris_cpu_realizefn; |
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ccc->parent_reset = cc->reset; |
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cc->reset = cris_cpu_reset; |
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cc->class_by_name = cris_cpu_class_by_name; |
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cc->do_interrupt = cris_cpu_do_interrupt; |
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cc->dump_state = cris_cpu_dump_state; |
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cc->set_pc = cris_cpu_set_pc; |
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cc->gdb_read_register = cris_cpu_gdb_read_register; |
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cc->gdb_write_register = cris_cpu_gdb_write_register; |
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#ifndef CONFIG_USER_ONLY
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cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; |
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#endif
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cc->gdb_num_core_regs = 49;
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} |
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static const TypeInfo cris_cpu_type_info = { |
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.name = TYPE_CRIS_CPU, |
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.parent = TYPE_CPU, |
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.instance_size = sizeof(CRISCPU),
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.instance_init = cris_cpu_initfn, |
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.abstract = true,
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.class_size = sizeof(CRISCPUClass),
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.class_init = cris_cpu_class_init, |
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}; |
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static void cris_cpu_register_types(void) |
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{ |
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int i;
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type_register_static(&cris_cpu_type_info); |
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for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) { |
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type_register_static(&cris_cpu_model_type_infos[i]); |
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} |
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} |
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type_init(cris_cpu_register_types) |